DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 10/26/2025, without traverse to prosecute the claims of Invention I, claims 1-18 (plus new claims 21-22) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/24/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by 주 시 닝 et al. (KR 20210138468 A).
Re Claim 14 주 시 닝 teaches a method for forming a nanosheet device, comprising:
epitaxially growing a conformal semiconductor layer (161, page 10 par 2 states, “…the cladding semiconductor layer 161 may be formed by an epitaxial growth process…”) from a first stack of semiconductor layers (156 on left, FIG. 8, page 9 par 3) and a second stack of the semiconductor layers (156 on right FIG. 8), wherein each of the first and second stack of semiconductor layers includes a plurality of first semiconductor layers (152, page 11 par 3) and a plurality of second semiconductor layers (154, page 11 par 3) alternately stacked on each other (FIG. 8 & 10);
filling a space between the first and second stacks of semiconductor layers with a dielectric fin (132, FIG. 11, page 10 par 4 “In some embodiments, dielectric liner 130, intermediate isolation structure 132, and lower isolation structure 160 are each formed of a low-k dielectric material…”);
removing the conformal semiconductor layer (161, FIG. 12) and the second semiconductor layers (154, FIG. 13B, page 11 par 3 “…154 may be shortened along the x direction…”); and
forming a metal gate structure (104, page 14 par 4) over the first semiconductor layers (152) and the dielectric fin (132, 130 is over 132, and 104 over 130), the metal gate structure filling openings created by removal of the conformal semiconductor layer (161) and the second semiconductor layers (154, FIG. 19C).
Re Claim 15 주 시 닝 teaches the method of Claim 14, further comprising performing a process on the metal gate structure to form an isolation (136, page 10 par 4) between the portions of the metal gate structure (104) being separated by a patterning process (FIG. 19C).
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US 9608116 B2, given in IDS).
Re Claim 21 Ching teaches a method of forming a semiconductor structure, comprising:
forming a pair of nanosheet channel structures (24/stack of 26, col 3 line 22) each having a plurality of nanosheets (26, col 3 line 30) spaced apart with each other (FIG. 3);
forming a plurality of separate dielectric fins (60, col 14 line 1) extending between the pair of nanosheet channel structures (stack of 26, FIG. 11), wherein the dielectric fins (60) have a top surface at a level higher than a top surface of each of the nanosheet channel structures (24/26, FIG. 11); and
forming a metal gate structure (72, col 7 line 40) over the pair of nanosheet channel structures (stack of 26) and the dielectric fins (60) to fill spaces between the dielectric fins (60) and the pair of nanosheet channel structures (stack of 26, FIG. 21A and FIG. 21C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, given in IDS) in view of Jiang et al. (US 9502265 B1, given in IDS).
Re Claim 1 Ching teaches a method of forming a semiconductor structure (FIG. 3), comprising:
forming a pair of stacks (24, col 3 line 22, FIG. 6) of semiconductor layers (26 & 28) each including a plurality of first semiconductor layers (26, col 3 line 24) and a plurality of second semiconductor layers (28, col 3 line 34) alternately stacked with each other along a first direction (see modified FIG. 3 below), wherein the pair of stacks (24) of semiconductor layers are adjacent to each other along a second direction (see modified FIG. 3 below);
forming a pair of epitaxial regions (58, col 5 line 28) at two opposite ends of each stack of semiconductor layers (24, FIG. 10) along a third direction (see modified FIG. 3 below);
filling a space between pair of stacks of semiconductor layers (26) with a dielectric fin (60, col 5 line 51, FIG. 11);
removing the second semiconductors (28, co3l 6 line 9, FIG. 9, process does not require dielectric fin be created for removing 2nd semiconductor layers); and
forming a gate electrode layer (72, col 7 line 40) over the stacks of semiconductor layers (26), the gate electrode layer (72) filling openings the second semiconductor layers (28, FIG. 16A) (Ching does not teach the conformal semiconductor layers, but the electrode being formed where it was is not critical to the method and chip functionality).
Modified FIG. 3 below shows 1st, 2nd, and 3rd directions
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Ching does not teach forming a conformal semiconductor layer on each stack of semiconductor layers; and
removing the conformal semiconductor layer.
Jiang teaches forming a conformal semiconductor layer (218, col 6 line 7, FIG. 6) on each stack of semiconductor layers (208A/210A & 208B/210B, col 5 line 54); and
removing the conformal semiconductor layer (218, FIG. 10).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jiang into the structure of Ching since both patents teach gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Jiang in combination with Ching in the above manner for the motivation of forming a conformal semiconductor layer to be used as an etch stop layer. Col 5 line 66 states, “Referring first to FIG. 6, a contact etch stop layer (CESL) 218 is deposited over a top surface and sidewalls of nanowires 212A and 212B.”
Re Claim 2 Ching in view of Jiang teaches the method of Claim 1, further comprising forming the first semiconductor layers (Ching, 26, col 3 line 24) with Si and the second semiconductor layers (28, col 3 line 34) with SiGe.
Re Claim 3 Ching in view of Jiang teaches the method of Claim 2, further comprising epitaxially (Ching, col 3 line 8 “…semiconductor stack 24 are formed over substrate 20 through epitaxy.”) forming first and second semiconductors (24 contains 26 & 28).
Re Claim 8 Ching in view of Jiang teaches the method of Claim 1, further comprising forming the dielectric fin (Ching, 60) with a top surface and a bottom surface larger than a central portion (use portion of 60 that is level with 58 side corners) thereof (FIG.11).
Re Claim 9 Ching in view of Jiang teaches the method of Claim 1, wherein the epitaxy regions (Ching, 58, col 5 line 28) include source/drain regions.
Re Claim 10 Ching in view of Jiang teaches the method of Claim 1, further comprising forming a gate dielectric layer (Ching, 70, col 7 line 10) before forming the gate electrode layer (FIG. 22).
Re Claim 13 Ching in view of Jiang teaches the method of Claim 1, wherein the first direction, the second direction, and the third direction extend along three orthogonal axes in a 3-dimensional coordinate (see Ching modified FIG. 3 under claim 1 reply).
Claims 4-6 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, given in IDS) in view of Jiang et al. (US 9502265 B1, given in IDS) and further in view of 주 시 닝 et al. (KR 20210138468 A).
Re Claim 4 Ching in view of Jiang teaches the method of Claim 2, but does not teach the conformal semiconductor layer with SiGe.
주 시 닝 teaches the conformal semiconductor layer (161) with SiGe (page 10 par 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by 주 시 닝 into the structure of Ching in view of Jiang since 주 시 닝 is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify 주 시 닝 in combination with Ching in view of Jiang in the above manner for the motivation of using SiGe for the conformal semiconductor layer to optimize the materials around the channel region of the transistor as device size continues to trend down. Page 3 par 2 states, “The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuits than the previous generation.”
Re Claim 5 Ching in view of Jiang teaches the method of Claim 1, but does not teach forming the conformal semiconductor layer with a thickness of about 5 nm to about 10 nm.
주 시 닝 teaches the first semiconductor layer 152 to be 3nm to 15 nm (page 9 par 1 “In some embodiments, the thickness of the first semiconductor layers 152 is in a range from about 3 nm to about 15 nm.”). The conformal semiconductor layer (161) is close to the same thickness of 152 only a little thicker. 161 is likely therefore about 5 nm to 10 nm thick (FIG. 11).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by 주 시 닝 into the structure of Ching in view of Jiang since 주 시 닝 is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify 주 시 닝 in combination with Ching in view of Jiang in the above manner for the motivation of reaching optimal conformal semiconductor layer thickness,
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal thickness for the conformal semiconductor layer.
Re Claim 6 Ching in view of Jiang teaches the method of Claim 1, but does not teach epitaxially growing the conformal semiconductor layer on exposed surfaces of the stacks of semiconductor layers.
주 시 닝 teaches epitaxially growing the conformal semiconductor layer (161, FIG. 10) on exposed surfaces of the stacks of semiconductor layers (page 10 par 2 states, “…the cladding semiconductor layer 161 may be formed by an epitaxial growth process…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by 주 시 닝 into the structure of Ching in view of Jiang since 주 시 닝 is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify 주 시 닝 in combination with Ching in view of Jiang in the above manner for the motivation of using a epitaxial growth process to form the conformal semiconductor layer around the channel region to optimally integrate the layers together as device size continues to trend down. Page 3 par 2 states, “The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuits than the previous generation.”
Re Claim 11 Ching in view of Jiang teaches the method of Claim 1, but does not teach patterning the gate electrode layer into a plurality of separate gate structures.
주 시 닝 teaches patterning the gate electrode layer (주 시 닝, 230) into a plurality of separate gate structures (FIG. 19C).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by 주 시 닝 into the structure of Ching in view of Jiang since 주 시 닝 is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify 주 시 닝 in combination with Ching in view of Jiang in the above manner for the motivation of forming multiple gate electrode to all one to fit multiple semiconductors onto a single structure as space is limited. Page 3 par 2 states, “The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuits than the previous generation.”
Re Claim 12 Ching in view of Jiang and 주 시 닝 teaches the method of Claim 11, further comprising forming an isolation structure (주 시 닝, 136, page 10 par 4) on the dielectric fin (132, FIG. 19C).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, given in IDS) in view of Jiang et al. (US 9502265 B1, given in IDS) and further in view of Li et al. (CN 113921471 A).
Re Claim 7 Ching in view of Jiang teaches the method of Claim 1, but does not teach forming the conformal semiconductor layer with four tapered corners.
Li forming the conformal semiconductor layer (106, page 19 par 3) with four tapered corners (FIG. 19A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of Ching in view of Jiang since Li is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify Li in combination with Ching in view of Jiang in the above manner for the motivation of tapering the corners of the conformal layer to help optimize the space in the semiconductor chip. Page 2 last par states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area.”
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over 주 시 닝 et al. (KR 20210138468 A) in view of Li et al. (CN 113921471 A).
Re Claim 16 주 시 닝 teaches the method of Claim 15, but does not teach forming the conformal semiconductor layer with four tapered corners.
Li forming the conformal semiconductor layer (106, page 19 par 3) with four tapered corners (FIG. 19A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of 주 시 닝 since Li is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify Li in combination with 주 시 닝 in the above manner for the motivation of tapering the corners of the conformal layer to help optimize the space in the semiconductor chip. Page 2 last par states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area.”
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over 주 시 닝 et al. (KR 20210138468 A) in view of Li (CN 113921471 A) and further in view of Yang et al. (CN 113764409).
Re Claim 17 주 시 닝 in view of Li teaches the method of Claim 16, but does not teach a portion of the metal gate structure filling the openings has four tapered corners.
Yang teaches a portion of the metal gate structure (260, page 18 par 3) filling the openings (250, page 17 par 2) has four tapered corners (FIG. 14 and 15).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yang into the structure of 주 시 닝 in view of Li since Yang is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify Yang in combination with 주 시 닝 in view of Li in the above manner for the motivation of tapering the corners the gate metal to help optimize the space to help the semiconductor device shrink in size and still function at a peak level. Page 3 par 3 states, “The technical progress of IC material and IC design produces many IC generations, each IC generation has smaller and more complex circuit than the last IC generation.”
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over 주 시 닝 et al. (KR 20210138468 A) in view of Li (CN 113921471 A) and Yang et al. (CN 113764409) and further in view of Ching et al. (US 9608116 B2, given in IDS).
Re Claim 18 주 시 닝 in view of Li and Yang teaches the method of Claim 17, but does not teach the dielectric fin with a wider top surface, a wider bottom surface, and a narrower middle body extending between the top and bottom surfaces.
Ching teaches the dielectric fin (60, col 14 line 1) with a wider top surface, a wider bottom surface, and a narrower middle body (use portions of 60 level with widest portions of 58) extending between the top and bottom surfaces (FIG. 15A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ching into the structure of 주 시 닝 in view of Li and Yang since Ching is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify Ching in combination with 주 시 닝 in view of Ling and Yang in the above manner for the motivation of having the dielectric fin wider on the top and bottom surface compared to the middle of the dielectric fin to help optimizer the architecture of the semiconductor device to help make smaller IC’s. Col 1 line 23 states, “Technological advances in Integrated Circuit (IC) materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generations.”
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, given in IDS) in view of 주 시 닝 et al. (KR 20210138468 A).
Re Claim 22 Ching teaches the method of Claim 21, but does not teach forming an isolation structure on the top surface of the dielectric fins.
teaches forming an isolation structure (160, page 7 par 4, FIG. 25C) on the top surface of the dielectric fins (132, page 7 par 4, FIG. 17C).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by 주 시 닝 into the structure of Ching since 주 시 닝 is also a patent that teaches a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify 주 시 닝 in combination with Ching in the above manner for the motivation of integrating an isolation structure over the dielectric fins to help optimize the available space in the semiconductor device. Page 3 par 2 states, “The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuits than the previous generation.”
Conclusion
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 1/29/26