DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/16/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patalay et al (US 20100124248) in view of Elleuch et al (US 2024/0203733), Ishii (US 2018/0053653) and Ishikawa et al (US 2022/0364229).
Patalay et al teaches a method of substrate processing comprising flowing one or more process reactive gases into an upper volume (upper portion 722) of a processing chamber 712 upper body via a process inlet passage (gas inlet manifold 730 with passage 760, i.e. flow module) that is in fluid communication with the upper volume of the processing chamber and guiding the one or more process reactive gases to the upper volume of the processing chamber by one or more flow guides (passage 760); and while flowing the one or more process reactive gases into the upper volume of the processing chamber, flowing purging gas 799 into a lower volume 724 of a lower body the processing chamber via a purge inlet 761 that is in fluid communication with the lower volume of the processing chamber (Fig 7-8; [0045]-[0060]). Patalay et al teaches a process gas may include a silicon source, HCl and an inert gas and Si epitaxial film growth ([0023], [0053]-[0055]).
Patalay et al teaches purging a pipe with a flow rate between of 200 sccm and 8 slm ([0091], [0097]); and the inert purge gas 799 is fed into the lower chamber portion 724 at a rate which develops a positive pressure within lower chamber portion 724 with respect to the process gas pressure in the upper chamber portion 722 ([0056]). Patalay et al does not explicitly teach at a flow rate of more than 2 slm. Patalay et al teaches the purge gas flow rate is a result effective variable and purging with flow rates greater than 2 slm; therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Patalay et al by optimizing the inert gas flow rate by conducting routine experimentation of a result effective variable to obtain an inert gas flow rate of greater than 2 slm (MPEP 2144.05) and overlapping ranges are prima facie obvious (MPEP 2144.05). Patalay et al teaches an upper chamber and lower chamber and gap and an inert purge gas ([0056]), which clearly suggests diluting a portion of the process gas leaked into the lower volume of the processing chamber.
Patalay et al teaches epitaxial silicon growth. Patalay et al does not teach epitaxially growing alternating layers of silicon (Si) and silicon germanium (SiGe).
Elleuch et al teaches a method for substrate processing, comprising: flowing one or more process reactive gases (first material precursor 116/ second material precursor 118) into an upper volume of a processing chamber (upper chamber 166); flowing cleaning gas (etchant source 122/carrier diluent source 120) into a lower volume of the processing chamber (lower chamber 168); and a plurality of temperature sensors 132, 134, 136A-136C ( Fig 2; [0035]-[0055]). Elleuch et al teaches an epitaxial material layer stack 200 comprising a first material layer pair 202 comprising a first silicon-germanium layer 206 and a first silicon material layer 208, and the material layer stack 200 may be more than 20 material layer pairs (Fig 3; [0055]-[0060]). Elleuch et al teaches a first material layer precursor comprising a silicon material layer precursor (trisilane) and a second material layer precursor also include a germanium-containing precursor (germane) ([0043]). Elleuch et al teaches material layer stacks are used to fabricate semiconductor devices ([0035]). Elleuch et al teaches one or more temperature sensors, upstream temperature sensor 136A and a downstream temperature sensor 136C, may be in contact with a divider and in thermal communication therethrough with the interior 160 of the chamber body 126; and a first non-contact temperature sensor 132 be optically coupled to an upper surface 4 of the substrate 2 and configured to acquire a first temperature of the substrate 2; a second non-contact temperature sensor 134 is further configured to optically acquire a second temperature measurement from within the chamber arrangement 104; and contact temperature sensors 136A-136C are arranged within the interior 160 of the chamber body 126 and are configured to acquire tactile temperature measurements from within the interior 160 of the chamber body 126 ([0048]-[0055]). Elleuch et al also teaches a controller 108 includes a device interface 186 and the device interface 186 may operably connect the upper heater element array 128, and/or the lower heater element array 130; and controlling temperature with a plurality of temperature sensors ([0053], [0088]-[0098]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Patalay et al by epitaxially growing alternating layers of silicon (Si) and silicon germanium (SiGe), as taught by Elleuch et al, to grow a material stack suitable for manufacturing devices.
The combination of Patalay et al and Elleuch et al does not explicitly teach a process inlet formed within the flow module and a purge inlet passage that is formed within the flow module separately from the process inlet passage. Patalay et al teaches a base ring 114 for purge inlet 162 and a gas inject ring 116 for gas injector 108 ([0034]; Fig 1A).
In a method and apparatus for vapor deposition, Ishii teaches a process chamber 1200 may be used to process one or more substrates 1208; a substrate support 1206 within the process chamber 1200 between an upper dome 1214 and a lower dome 1212; a base ring (flow module) 1218 that is disposed between the upper dome 1214 and lower dome 1212; base ring 1218 includes a substrate loading port, a process gas inlet 1236, and a gas outlet 1242, a purge gas inlet 1226 formed in the sidewall of the base ring 1218, wherein purge gas inlet 1226 is disposed at an elevation below the process gas inlet 1236 (Fig 2; [0016]-[0033]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Patalay et al and Elleuch et al by making the base ring and gas inject ring into a single flow module because making elements integral is prima facie obvious (MPEP 2144.04 V. B.) and Ishii teaches providing the process gas inlet and the purge gas inlet within a single flow module (base ring); therefore, the integration of the base ring and gas inject ring into a single base ring was conventionally known in the art at the time of the invention.
The combination of Patalay et al, Elleuch et al and Ishii does not explicitly teach a purge outlet passage formed within the flow module separately from the process outlet passage, wherein the portion of the one or more process reactive gases is diluted with the purge gas. The combination of Patalay et al, Elleuch et al and Ishii teaches an upper outlet 792, a lower outlet 796 and a common exhaust 794 (Patalay Fig 7; [0054]).
In a method and apparatus for vapor deposition, Ishikawa et al teaches a process chamber assembly 100 includes a chamber body 101 containing a process volume 110 which includes an upper chamber region 111 and a lower chamber region 113; one or more upper chamber exhaust passages 426, and a lower chamber exhaust passage 164; the one or more upper chamber exhaust passages 426 and the lower chamber exhaust passage 164 are coupled to one or more exhaust pumps; and the pressure of the lower chamber region 113 is maintained at a value greater than the pressure of the upper chamber region 111 by increasing an exhaust rate of the process gas 204 through the upper gas outlet 212 during the epitaxy process to minimize or reduce thee diffusion of the gases between the upper chamber region 111 and the lower chamber region 113 (Fig 2A; [0025]-[0056]). Ishikawa et al teaches a process gas 204 in the upper chamber region 111 and the purge gas 208 in the lower chamber region 113 are simultaneously flowing during the epitaxy process (Fig 2A; [0052]); therefore, the diffusion of gases from the upper to the lower chamber clearly suggests a portion of the one or more process reactive gases is diluted with the purge gas. Ishikawa et al also teaches epitaxially depositing silicon, germanium of silicon-germanium ([0050]-[0055]). A comparison of applicant’s Fig 1 and Ishii Fig 2 is provided below to show the similarities in the flow module and base ring.
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It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Patalay et al, Elleuch et al and Ishii by having a purge outlet passage formed within the flow module separately from the process outlet passage, as taught by Ishikawa et al, to minimize or reduce diffusion of gases from the upper chamber to the lower chamber.
Referring to claim 2, the combination of Patalay et al, Elleuch et al, Ishii and Ishikawa et al teaches an etchant fluid may be co-flowed with the first material layer precursor and the second material layer precursor; and an etchant conduit 124 to provide etchant fluid 20 as a lower chamber purge flow (Elleuch [0045], [0070]), which clearly suggests flowing of the one or more process reactive gases into the upper volume of the processing chamber and the flowing of the cleaning gas into the lower volume of the processing chamber are performed simultaneously.
Referring to claim 3, the combination of Patalay et al, Elleuch et al, Ishii and Ishikawa et al teaches monosilane or a high order silane; or germane (Elleuch [0043], [0079]), which clearly suggests the one or more process reactive gases comprise a silicon or germanium containing precursor.
Referring to claim 4, the combination of Patalay et al, Elleuch et al, Ishii and Ishikawa et al teaches a material stack 200 includes a material pair comprising silicon-germanium 206 and a silicon layer 208, wherein the first silicon material thickness of less than 100 nm and the silicon-germanium layer ha a thickness of less than 25 nm (Elleuch [0055]-[0060]) which clearly suggests layers deposited by the flowing of the one or more process reactive gases comprise more than 2 pairs of alternating layers of silicon (Si) and silicon germanium (SiGe), each layer having a thickness of between 50A and 1000A because overlapping ranges are prima facie obvious (MPEP 2144.05).
Referring to claim 5 and 7, the combination of Patalay et al, Elleuch et al, Ishii and Ishikawa et al teaches an HCl etchant gas and H2 carrier/diluent (Elleuch [0044]-[0045]). The selection of a known material based on its suitability for its intended purpose is prima facie obvious (MPEP 2144.07).
Claim(s) 8, 11, 12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patalay et al (US 20100124248) in view of Elleuch et al (US 2024/0203733), Ishii (US 2018/0053653) and Ishikawa et al (US 2022/0364229), as applied to claims 1-5 and 7 above, and further in view of Leow et al (US 2020/0080894).
The combination of Patalay et al, Elleuch et al, Ishii and Ishikawa et al teaches all of the limitations of claim 8, as discussed above, except the combination of Patalay et al, Elleuch et al and Ishikawa et al does not explicitly teach measuring temperature of a bottom inner surface of the lower volume of the processing chamber; and adjusting a temperature of the epitaxial deposition process, based on the measured temperature.
In an apparatus for semiconductor processing, Leow et al teaches a process chamber for chemical vapor deposition; a heating system comprising linear radiant heating elements 13, 14; and a temperature controller 17 can be provided to control the temperature within the reaction chamber 12 based on feedback signal(s) received from temperature sensors, and/or from signals received from the lamps ([0018]-[0026]; Fig 1). Leow et al also teaches sensors 21a, 21b, 21b′, 21b″ are described as measuring the temperature of the chamber wall 11 and the wafer 16 (e.g., directly or by way of measuring the temperature of the susceptor 20), respectively, in other embodiments, one or more non-contact temperature sensors (e.g., pyrometers) can be used to measure the temperature of other components of the process apparatus 10, such as the temperature of upper or lower quartz walls ([0024]), which clearly suggests measuring the bottom inner surface of the processing chamber. Loew et al teaches it is important to accurately control the wafer temperature to bring the wafer to the desired temperature before the treatment begins and to maintain desired temperatures throughout the process; and to accurately control the wafer temperature, it can be important to accurately measure the temperature of the wafer or other components of the process chamber (such as chamber walls, the susceptor, etc.) ([0003]-[0004]), which clearly suggests measuring temperature of a bottom inner surface of the lower volume of the processing chamber; and adjusting a temperature of the epitaxial deposition process, based on the measured temperature.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Patalay et al, Elleuch et al, Ishii and Ishikawa et al by providing temperature sensors to monitor and control the temperature of the reaction chamber by measuring the inner bottom wall and adjusting a temperature of the epitaxial deposition process, based on the measured temperature, as taught by Leow et al, and to maintain desired temperatures throughout the process.
Referring to claim 11, the combination of Patalay et al, Elleuch et al, Ishii, Ishikawa et al and Leow et al teaches monosilane or a high order silane; or germane (Elleuch [0043], [0079]), which clearly suggests the one or more process reactive gases comprise a silicon or germanium containing precursor.
Referring to claim 12, the combination of Patalay et al, Elleuch et al, Ishii, Ishikawa et al and Leow et al teaches a material stack 200 includes a material pair comprising silicon-germanium 206 and a silicon layer 208, wherein the first silicon material thickness of less than 100 nm and the silicon-germanium layer ha a thickness of less than 25 nm (Elleuch [0055]-[0060]) which clearly suggests layers deposited by the flowing of the one or more process reactive gases comprise more than 2 pairs of alternating layers of silicon (Si) and silicon germanium (SiGe), each layer having a thickness of between 50A and 1000A because overlapping ranges are prima facie obvious (MPEP 2144.05).
Referring to claim 15, the combination of Patalay et al, Elleuch et al, Ishii, Ishikawa et al and Leow et al teaches an HCl etchant gas and H2 carrier/diluent (Elleuch [0044]-[0045]). The selection of a known material based on its suitability for its intended purpose is prima facie obvious (MPEP 2144.07).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7, 8, 11, 12, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hansson (US 6,316,361) teaches a chamber comprising isolated upper and lower chambers (Fig 2; abstract).
Goodwin et al (US 4,874,464) teaches a reaction chamber is purged with hydrogen to which a flow of HCl is added at about 20 slm and hydrogen flow is increased to 20 to 100 slm to etch a reactor chamber of accumulated residues and a final hydrogen purge of 100 slm (col 5, ln 1-65). Overlapping ranges are prima facie obvious (MPEP 2144.05).
JP 2006049503 teaches an epitaxial growth chamber comprising an upper space and a lower space dividing by a susceptor wherein gas is supply to an upper space and lower space with an upper discharge port and a lower discharge port (Fig 1 and 7).
Ranish (US 20130284097) teaches an vapor growth chamber comprising an upper space and a lower space dividing by a susceptor wherein gas is supply to an upper space and lower space with an upper discharge port and a lower discharge port (Fig 1; [0017]-[0028]).
Brenninger et al (US 2012/0263875) teaches an upper chamber with upper inlet and upper exhaust, and a lower chamber with a lower inlet and lower exhaust (Fig 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J SONG whose telephone number is (571)272-1468. The examiner can normally be reached Monday-Friday 10AM-6PM.
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/ Primary Examiner, Art Unit 1714
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