DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-14, and 17-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Qiushi Chen et. al. (US 20100199236 A1).
Chen et. al. discloses
A method comprising: receiving a circuit design comprising a first die and a second die positioned on the first die;
(Chen et. al., page 2, DETAILED DESCRIPTION, Process for Performing an RLC Extraction for a 3D-IC Design: [0098] “During operation, the system receives a 3D-IC die description.”)
(Chen et. al., page 2, BRIEF DESCRIPTION OF THE FIGURES, [0024] “FIG. 2 illustrates a 3D-IC comprised of two vertically stacked dies …”)
generating, by a processing device, a first virtual interface block comprising a portion of the first die and a first virtual die positioned adjacent to the first die, wherein a layer of the first virtual die closest to the first die comprises first tracks filled with virtual metal;
(Chen et. al., page 1, SUMMARY, [0017] “In some embodiments, the system transforms the die stack into at least two separate dies by first identifying a transform boundary between the first die and the second die, and then separating the first die from the second die to create a first transformed die and a second transformed die, respectively. Note that the first transformed die includes the first die and at least one metal layer adjacent to the transform boundary in the second die.”)
and performing parasitic extraction based at least in part on the first virtual interface block to generate a first model of inter-die coupling between the first die and the first virtual die.
(Chen et. al., page 2, DETAILED DESCRIPTION, Process for Performing an RLC Extraction for a 3D-IC Design [0098] “During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description (step 604). Note that this equivalency can include both electrical property equivalency and connectivity equivalency. Furthermore, the set of 2D-IC die descriptions include the effects of inter-die couplings within the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file (step 606).”).
Regarding claim 2 Chen et. al. discloses
The method of Claim 1, further comprising: generating a second virtual interface block comprising a portion of the second die and a second virtual die, wherein a layer of the second virtual die closest to the second die comprises second tracks filled with virtual metal;
(Chen et. al., page 1, SUMMARY [0017] “… The second transformed die includes the second die and at least one metal layer adjacent to the transform boundary in the first die.”)
and performing parasitic extraction based at least in part on the second virtual interface block to generate a second model of inter-die coupling between the second die and the second virtual die.
(Chen et. al., DETAILED DESCRIPTION, page 6, RLC Extraction Based on Extraction Units, Flat Transform Invariant Extraction [0092] “FIG. 5B illustrates an extraction model for performing RLC extractions on the transformed dies in FIG. 5A in accordance with an embodiment of the present invention.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Process for Performing an RLC Extraction for a 3D-IC Design, [0098] “… The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description (step 604). Note that this equivalency can include both electrical property equivalency and connectivity equivalency. Furthermore, the set of 2D-IC die descriptions include the effects of inter-die couplings within the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file (step 606).”)
Regarding claim 3 Chen et. al. discloses
The method of Claim 2, further comprising, performing static timing analysis for the second die using the second model of inter-die coupling between the second die and the second virtual die.
(Chen et. al., DETAILED DESCRIPTION, Integrated Circuit Design Flow, page 3 [0051] “Embodiments of the present invention can be used during one or more of the above-described steps. Specifically, one embodiment of the present invention can be used during the analysis and extraction step 124 and physical verification step 126.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Hierarchical Transform Invariant Extraction [0094] “For inter-die RLC couplings, the parasitic values can be represented in form of an inter-die parasitic library file. When extractions are completed, simulation and analysis tools can be used to perform hierarchical simulations and analyses using the aforementioned parasitic RLC netlist files and the inter-die parasitic library files.”)
Regarding claim 4 Chen et. al. discloses
The method of Claim 1, wherein the portion of the first die comprises one or more of a first layer, a second layer positioned on the first layer, and a third layer positioned on the second layer.
(Chen et. al., DETAILED DESCRIPTION, Multi-Die Stack Transform, page 6 “FIG. 5A illustrates transforming a three-die stack into individual extraction units in accordance with an embodiment of the present invention.” [0089] “As illustrated in FIG. 5A, 3D-IC stack 500 includes an upper die 502, which is stacked on top of a middle die 504, which is stacked on top of a lower die 506. During a transform process, die-to-die interface 508 between die 502 and die 504 becomes the first transform boundary, and die-to-die interface 510 between die 504 and die 506 becomes the second transform boundary.”)
Regarding claim 5 Chen et. al. discloses
The method of Claim 1, wherein performing parasitic extraction based at least in part on the first virtual interface block comprises generating coupling capacitors from the portion of the first die to the first tracks filled with virtual metal.
(Chen et. al., DETAILED DESCRIPTION, page 3, RLC Extraction for a 2D-IC Design [0058] “In the following discussion, the terms "RLC extraction" and "parasitic extraction" are used interchangeably to mean electrical property extraction from an IC die. Such electrical property can include, but is not limited to resistance (R), inductance (L), and capacitance (C).”)
Regarding claim 6 Chen et. al. discloses
The method of Claim 1, further comprising performing static timing analysis for the first die using the first model of inter-die coupling between the first die and the first virtual die.
(Chen et. al., DETAILED DESCRIPTION, Integrated Circuit Design Flow, page 3 [0051] “Embodiments of the present invention can be used during one or more of the above-described steps. Specifically, one embodiment of the present invention can be used during the analysis and extraction step 124 and physical verification step 126.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Hierarchical Transform Invariant Extraction [0094] “For inter-die RLC couplings, the parasitic values can be represented in form of an inter-die parasitic library file. When extractions are completed, simulation and analysis tools can be used to perform hierarchical simulations and analyses using the aforementioned parasitic RLC netlist files and the inter-die parasitic library files.”)
Regarding claim 9 Chen et. al. discloses
A system comprising: a memory; and a processor communicatively coupled to the memory, the processor configured to:
(Chen et. al., page 2, DETAILED DESCRIPTION [0038] “The data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing computer-readable media now known or later developed.”)
receive a circuit design comprising a first die and a second die positioned on the first die;
(Chen et. al., page 2, DETAILED DESCRIPTION, Process for Performing an RLC Extraction for a 3D-IC Design: [0098] “During operation, the system receives a 3D-IC die description.”)
(Chen et. al., page 2, BRIEF DESCRIPTION OF THE FIGURES, [0024] “FIG. 2 illustrates a 3D-IC comprised of two vertically stacked dies …”)
generate a first virtual interface block comprising a portion of the first die and a first virtual die positioned on the first die, wherein a layer of the first virtual die closest to the first die comprises tracks filled with virtual metal;
(Chen et. al., page 1, SUMMARY, [0017] “In some embodiments, the system transforms the die stack into at least two separate dies by first identifying a transform boundary between the first die and the second die, and then separating the first die from the second die to create a first transformed die and a second transformed die, respectively. Note that the first transformed die includes the first die and at least one metal layer adjacent to the transform boundary in the second die.”)
and perform parasitic extraction based at least in part on the first virtual interface block to generate a first model of inter-die coupling between the first die and the first virtual die.
(Chen et. al., page 2, DETAILED DESCRIPTION, Process for Performing an RLC Extraction for a 3D-IC Design [0098] “During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description (step 604). Note that this equivalency can include both electrical property equivalency and connectivity equivalency. Furthermore, the set of 2D-IC die descriptions include the effects of inter-die couplings within the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file (step 606).”)
Regarding claim 10 Chen et. al. discloses
The system of Claim 9, wherein the processor is further configured to: generate a second virtual interface block comprising a portion of the second die and a second virtual die, wherein a layer of the second virtual die closest to the second die comprises tracks filled with virtual metal;
(Chen et. al., page 1, SUMMARY [0017] “… The second transformed die includes the second die and at least one metal layer adjacent to the transform boundary in the first die.”)
and perform parasitic extraction based at least in part on the second virtual interface block to generate a second model of inter-die coupling between the second die and the second virtual die.
(Chen et. al., DETAILED DESCRIPTION, page 6, RLC Extraction Based on Extraction Units, Flat Transform Invariant Extraction [0092] “FIG. 5B illustrates an extraction model for performing RLC extractions on the transformed dies in FIG. 5A in accordance with an embodiment of the present invention.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Process for Performing an RLC Extraction for a 3D-IC Design, [0098] “… The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description (step 604). Note that this equivalency can include both electrical property equivalency and connectivity equivalency. Furthermore, the set of 2D-IC die descriptions include the effects of inter-die couplings within the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file (step 606).”)
Regarding claim 11 Chen et. al. discloses
The system of Claim 10, wherein the processor is further configured to perform static timing analysis for the second die using the second model of inter-die coupling between the second die and the second virtual die.
(Chen et. al., DETAILED DESCRIPTION, Integrated Circuit Design Flow, page 3 [0051] “Embodiments of the present invention can be used during one or more of the above-described steps. Specifically, one embodiment of the present invention can be used during the analysis and extraction step 124 and physical verification step 126.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Hierarchical Transform Invariant Extraction [0094] “For inter-die RLC couplings, the parasitic values can be represented in form of an inter-die parasitic library file. When extractions are completed, simulation and analysis tools can be used to perform hierarchical simulations and analyses using the aforementioned parasitic RLC netlist files and the inter-die parasitic library files.”)
Regarding claim 12 Chen et. al. discloses
The system of Claim 9, wherein the portion of the first die comprises a first layer, a second layer positioned on the first layer, and a third layer positioned on the second layer.
(Chen et. al., DETAILED DESCRIPTION, Multi-Die Stack Transform, page 6 “FIG. 5A illustrates transforming a three-die stack into individual extraction units in accordance with an embodiment of the present invention.” [0089] “As illustrated in FIG. 5A, 3D-IC stack 500 includes an upper die 502, which is stacked on top of a middle die 504, which is stacked on top of a lower die 506. During a transform process, die-to-die interface 508 between die 502 and die 504 becomes the first transform boundary, and die-to-die interface 510 between die 504 and die 506 becomes the second transform boundary.”)
Regarding claim 13 Chen et. al. discloses
The system of Claim 9, wherein performing parasitic extraction based at least in part on the first virtual interface block comprises generating coupling capacitors from the portion of the first die to the tracks filled with virtual metal.
(Chen et. al., DETAILED DESCRIPTION, page 3, RLC Extraction for a 2D-IC Design [0058] “In the following discussion, the terms "RLC extraction" and "parasitic extraction" are used interchangeably to mean electrical property extraction from an IC die. Such electrical property can include, but is not limited to resistance (R), inductance (L), and capacitance (C).”)
Regarding claim 14 Chen et. al. discloses
The system of Claim 9, wherein the processor is further configured to perform static timing analysis for the first die using the first model of inter-die coupling between the first die and the first virtual die.
(Chen et. al., DETAILED DESCRIPTION, Integrated Circuit Design Flow, page 3 [0051] “Embodiments of the present invention can be used during one or more of the above-described steps. Specifically, one embodiment of the present invention can be used during the analysis and extraction step 124 and physical verification step 126.”)
(DETAILED DESCRIPTION, page 6, Hierarchical Transform Invariant Extraction [0094] “For inter-die RLC couplings, the parasitic values can be represented in form of an inter-die parasitic library file. When extractions are completed, simulation and analysis tools can be used to perform hierarchical simulations and analyses using the aforementioned parasitic RLC netlist files and the inter-die parasitic library files.”)
Regarding claim 17 Chen et. al. discloses
A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to:
(Chen et. al., page 2, DETAILED DESCRIPTION [0038] “The data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing computer-readable media now known or later developed.”)
generate a first virtual interface block comprising a portion of a first die of a plurality of stacked dies and a first virtual die positioned on the first die, wherein a layer of the first virtual die closest to the first die comprises tracks filled with virtual metal;
(Chen et. al., page 1, SUMMARY, [0017] “In some embodiments, the system transforms the die stack into at least two separate dies by first identifying a transform boundary between the first die and the second die, and then separating the first die from the second die to create a first transformed die and a second transformed die, respectively. Note that the first transformed die includes the first die and at least one metal layer adjacent to the transform boundary in the second die.”)
and generate a first model of inter-die coupling between the first die and the first virtual die.
(Chen et. al., page 2, DETAILED DESCRIPTION, Process for Performing an RLC Extraction for a 3D-IC Design [0098] “During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description (step 604). Note that this equivalency can include both electrical property equivalency and connectivity equivalency. Furthermore, the set of 2D-IC die descriptions include the effects of inter-die couplings within the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file (step 606).”)
Regarding claim 18 Chen et. al. discloses
The computer readable medium of Claim 17, wherein the processor further: generates a second virtual interface block comprising a portion of a second die of the plurality of stacked dies and a second virtual die, wherein a layer of the second virtual die closest to the second die comprises tracks filled with virtual metal;
(Chen et. al., page 1, SUMMARY [0017] “… The second transformed die includes the second die and at least one metal layer adjacent to the transform boundary in the first die.”)
and generates a second model of inter-die coupling between the second die and the second virtual die.
(Chen et. al., DETAILED DESCRIPTION, page 6, RLC Extraction Based on Extraction Units, Flat Transform Invariant Extraction [0092] “FIG. 5B illustrates an extraction model for performing RLC extractions on the transformed dies in FIG. 5A in accordance with an embodiment of the present invention.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Process for Performing an RLC Extraction for a 3D-IC Design, [0098] “… The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description (step 604). Note that this equivalency can include both electrical property equivalency and connectivity equivalency. Furthermore, the set of 2D-IC die descriptions include the effects of inter-die couplings within the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file (step 606).”)
Regarding claim 19 Chen et. al. discloses
The computer readable medium of Claim 18, wherein the processor further performs static timing analysis for the second die using the second model of inter-die coupling between the second die and the second virtual die.
(Chen et. al., DETAILED DESCRIPTION, Integrated Circuit Design Flow, page 3 [0051] “Embodiments of the present invention can be used during one or more of the above-described steps. Specifically, one embodiment of the present invention can be used during the analysis and extraction step 124 and physical verification step 126.”)
(Chen et. al., DETAILED DESCRIPTION, page 6, Hierarchical Transform Invariant Extraction [0094] “For inter-die RLC couplings, the parasitic values can be represented in form of an inter-die parasitic library file. When extractions are completed, simulation and analysis tools can be used to perform hierarchical simulations and analyses using the aforementioned parasitic RLC netlist files and the inter-die parasitic library files.”)
Regarding claim 20 Chen et. al. discloses
The computer readable medium of Claim 17, wherein performing parasitic extraction based at least in part on the first virtual interface block comprises generating coupling capacitors from the portion of the first die to the tracks filled with virtual metal.
(Chen et. al., DETAILED DESCRIPTION, page 3, RLC Extraction for a 2D-IC Design [0058] “In the following discussion, the terms "RLC extraction" and "parasitic extraction" are used interchangeably to mean electrical property extraction from an IC die. Such electrical property can include, but is not limited to resistance (R), inductance (L), and capacitance (C).”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20100199236) in view of James C. Gregerson et. al. (US 9542524 B2).
Regarding claim 7
Chen et. al. teaches all features of claims 1 through 6 as disclosed above, and further shows a third die (Chen Fig. 5, third die 506; see also the first die 502 and second die 504 recited in claim 1).
Chen et. al. does not teach
The method of Claim 6, further comprising, in response to determining that a third die of the circuit design is the same as the first die, using, for the third die, results of the static timing analysis for the first die.
However, Gregerson et. al. discloses:
(Gregerson: col. 14, lines 29-37 “For purposes of this disclosure, a hierarchical entity refers to a block of logic (also referred to herein as a lower-level entity or macro). The multiple hierarchical entities can, for example, comprise different hierarchical entities as well as multiple instances of the same hierarchical entity. That is, the same hierarchical entity (i.e., a hierarchical entity with a specific design) may be reused at various different locations within the full top-level design 111 for the integrated circuit.”; Noted Grgerson’s IC design is treated as die design)
(Gregerson: col. 1, lines 29-41 “With a hierarchical approach, STA is performed …; In the hierarchical approach described above, each timing abstraction for each specific hierarchical entity only contains relevant timing information required for incorporating that specific hierarchical entity into the full top-level design or into a block at the higher level of hierarchy”.)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen et. al. and of Gregerson et. al. to reuse the static timing analysis done for the first die for the third die to reduce the analysis time and resources, as the third die is determined to be the same.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20100199236) in view of view of James C. Gregerson et. al. (US 9542524 B2) and Steven Teig (US 668788).
Regarding claim 8
The combination of Chen and Gregerson teaches et. al. teaches performing static timing analysis (see comments in claim 7 above).
The combination of Chen and Gregerson does not teach:
The method of Claim 6, wherein performing static timing analysis for the first die comprises, when the layer filled with virtual metal is an aggressor net, treating the layer filled with virtual metal as being connected to a victim net in the first virtual die and disconnected from other nets in the first virtual die.
However, Steven Teig et. al. teaches:
(DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT, col 15, A Capacitance Extraction Example, lines 35-39 “The layout example of FIG. 8A contains four different "nets" (interconnect wires) 810, 820, 830, and 840. Each net illustrated in FIG. 8A is constructed only from horizontal interconnect wire segments and vertical interconnect wire segments as is required by Manhattan wire routing.” And lines 49-54 “To provide an example of capacitance extraction, the capacitance of a first horizontal portion of critical net 810 in FIG. 8A will be determined. In common capacitance extraction parlance, the interconnect wiring of net 810 will be the "aggressor" wire and the other wire segments that effect the capacitance of net 810 will be the "victim" wires.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of the combination of Chen and Gregerson and the teaching of Teig et. al. to naturally treat interconnect wiring such as the metal filled layer as aggressor net connected to the victim net consisting of first die and perform static timing analysis.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20100199236) in view of James C. Gregerson et. al. (US 9542524 B2).
Regarding claim 15
Chen et. al. teaches all features of claims 9 through 14 as disclosed above, and further shows a third die (Chen Fig. 5, third die 506; see also the first die 502 and second die 504 recited in claim 1).
Chen et. al. does not teach
The system of Claim 14, wherein the processor is further configured to, in response to determining that a third die of the circuit design is the same as the first die, use, for the third die, results of the static timing analysis for the first die.
However, Gregerson et. al. discloses
(Gregerson: col. 14, lines 29-37 “For purposes of this disclosure, a hierarchical entity refers to a block of logic (also referred to herein as a lower-level entity or macro). The multiple hierarchical entities can, for example, comprise different hierarchical entities as well as multiple instances of the same hierarchical entity. That is, the same hierarchical entity (i.e., a hierarchical entity with a specific design) may be reused at various different locations within the full top-level design 111 for the integrated circuit.”. Noted Grgerson’s IC design is treated as die design)
(Gregerson: col. 1, lines 29-41 “With a hierarchical approach, STA is performed …; In the hierarchical approach described above, each timing abstraction for each specific hierarchical entity only contains relevant timing information required for incorporating that specific hierarchical entity into the full top-level design or into a block at the higher level of hierarchy”.)).
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen et. al. and of Gregerson et. al. to reuse the static timing analysis done for the first die for the third die to reduce the analysis time and resources, as the third die is determined to be the same.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20100199236) in view of view of James C. Gregerson et. al. (US 9542524 B2) and Steven Teig (US 668788).
Regarding claim 16
The combination of Chen and Gregerson teaches et. al. teaches performing static timing analysis (see comments in claim 15 above).
The combination of Chen and Gregerson does not teach:The system of Claim 14, wherein performing static timing analysis for the first die comprises, when the layer filled with virtual metal is an aggressor net, treating the layer filled with virtual metal as being connected to a victim net in the first virtual die and disconnected from other nets in the first virtual die.
However, Steven Teig et. al. teaches:
(DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT, col 15, A Capacitance Extraction Example, lines 35-39 “The layout example of FIG. 8A contains four different "nets" (interconnect wires) 810, 820, 830, and 840. Each net illustrated in FIG. 8A is constructed only from horizontal interconnect wire segments and vertical interconnect wire segments as is required by Manhattan wire routing.” And lines 49-54 “To provide an example of capacitance extraction, the capacitance of a first horizontal portion of critical net 810 in FIG. 8A will be determined. In common capacitance extraction parlance, the interconnect wiring of net 810 will be the "aggressor" wire and the other wire segments that effect the capacitance of net 810 will be the "victim" wires.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of the combination of Chen and Gregerson and the teaching of Teig et. al. to naturally treat interconnect wiring such as the metal filled layer as aggressor net connected to the victim net consisting of first die and perform static timing analysis.
Conclusion
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851