Prosecution Insights
Last updated: October 23, 2026
Application No. 18/101,676

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

Final Rejection §103
Filed
Jan 26, 2023
Priority
Feb 02, 2022 — JP 2022-015012
Examiner
CROWELL, ANNA M
Art Unit
1716
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Tokyo Electron Limited
OA Round
2 (Final)
44%
Grant Probability
Moderate
3-4
OA Rounds
1m
Est. Remaining
75%
With Interview

Examiner Intelligence

Grants 44% of resolved cases
44%
Career Allowance Rate
196 granted / 440 resolved
-20.5% vs TC avg
Strong +31% interview lift
Without
With
+30.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
26 currently pending
Career history
482
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
57.9%
+17.9% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
13.8%
-26.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 440 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species I in the reply filed on January 6, 2026 is acknowledged. Claims 2 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Priority Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216. Claim Interpretation With respect to claim 1, the 112f claim interpretation of the “heating part” has been withdrawn since “heating part” has been deleted from the claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 3, 9-11, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fu et al. (U.S. 2024/0170254) in view of Kishimoto et al. (U.S. 2011/0312167). Referring to Figures 5-7 and paragraphs [0058]-[0064], Fu et al. disclose a plasma processing apparatus comprising: a substrate holder 218 configured to place a plurality of substrates in a multi-stage structure in a height direction on the substrate holder (Fig. 7); and a processing container 100 configured to accommodate the substrate holder in the processing container and heat the plurality of substrates (pars.[0037],[0080]), wherein the substrate holder includes a plurality of stages, which are made of a dielectric material (pars.[0058]-[0059]), and a first electrode layer 214 and a second electrode layer 216 embedded in the plurality of stages (par.[0062]), wherein radio frequency power 250 is supplied to the first electrode layer, and the second electrode layer is connected to a ground 255 (par.[0058], [0062]). Fu et al. is silent on wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer. Referring to Figure 1 and paragraphs [0093]-[0096], Kishimoto et al. teach a plasma processing apparatus wherein uppermost 4 and lowermost 2 electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer in order to bring the plasma discharges occurring at a plurality of the discharge portion into a state where they uniformly match to one another (pars.[0033]-[0036]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Fu et al. with wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer as taught by Kishimoto et al. in order to bring the plasma discharges occurring at a plurality of the discharge portion into a state where they uniformly match to one another. The resulting apparatus of Fu et al. in view of Kishimoto et al. would yield wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer. With respect to claim 3, the plasma processing apparatus of Fu et al. further includes wherein at least one of the first electrode layer 214 and the second electrode layer 216 has a mesh shape (Fig. 7) or a film shape (Fig. 5). With respect to claim 9, the plasma processing apparatus of Fu et al. further includes wherein each of the plurality of stages of the substrate holder 218 has a placement surface on which the substrate is placed (Fig. 7). With respect to claim 10, the plasma processing apparatus of Fu et al. further includes wherein the first electrode layer 214 and the second electrode layer 216 have circular outer edges, and the circular outer edges of the first electrode layer and the second electrode layer are larger than or the same as an outer edge of the placement surface (Fig. 5). With respect to claim 11, the plasma processing apparatus of Fu et al. further includes wherein the outer edge of the first electrode layer and the outer edge of the second electrode layer have the same size (Figs. 5-7). With respect to claim 16, the plasma processing apparatus of Fu et al. further includes comprising: a radio frequency power supply 250 configured to output a radio frequency power; and a distributor (i.e. feed lines from RF power supply 250) configured to distribute the radio frequency power output from the radio frequency power supply, wherein the radio frequency power is distributed and supplied to a plurality of first electrode layers 214 in the plurality of stages (Figs. 5-7, pars.[0061]-[0062]). With respect to claim 17, the plasma processing apparatus of Fu et al. further includes wherein, among the plurality of stages, the second electrode layer 216 is arranged above the first electrode layer 214 in the plurality of stages 218 (Figs. 5-7). Claim(s) 1, 3, 7, 8-14, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maher, Jr. et al. (U.S. 4,381,965) in view of Kim et al. (KR101394110B1), Ravi et al. (2021/0032753), and Kishimoto et al. (U.S. 2011/0312167). Referring to Figures 4-5 and column 5 , line 24-column 7, line 18, Maher, Jr. et al. disclose a plasma processing apparatus comprising: a substrate holder 19c-25c configured to place a plurality of substrates 15 in a multi-stage structure in a height direction on the substrate holder (Fig. 4); and a processing container 10, 43 configured to accommodate the substrate holder in the processing container (col. 4, lines 1-10, col. 6, lines 36-40), wherein the substrate holder includes a plurality of stages, 19c-25c which are made of a dielectric material (col. 6, lines 7-9), and a first electrode layer 19b-25b and a second electrode layer 19a-25a on the plurality of stages (col. 6, line 50-col. 7, line 4), and wherein radio frequency power 44 is supplied to the first electrode layer, and the second electrode layer is connected to a ground (col. 6, line 50-col. 7, line 18). Maher, Jr. et al. is silent on a processing container that heats the plurality of substrates. Referring to page 6, paragraph 3, Kim et al. teach a plasma processing apparatus wherein a processing container that heats the plurality of substrates for substrate processing. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the processing container of Maher, Jr. et al. to heat the plurality of substrates as taught by Kim et al. in order to control the substrate temperature during substrate processing. Maher, Jr. et al. fail to each a first electrode layer and a second electrode layer embedded in the plurality of stages. Referring to paragraphs [0026], Ravi et al. teach that is conventionally known in the art for a plasma processing apparatus to include an electrode 168 embedded in the stage 108. Additionally, electrodes 140, 190, 192 are embedded in supports (pars.[0028]-[0029]). Embedding the electrode layer within the stage will protect the electrode layer from the plasma environment. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified a first electrode layer and a second electrode layer Maher, Jr. et al. with embedding in the stage as taught Ravi et al. in order to protect the electrode layers from the plasma environment. The resulting apparatus of Maher, Jr. et al. in view of Ravi et all. includes a first electrode layer and a second electrode layer embedded in the plurality of stages. Maher, Jr. et al. is silent on wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer. Referring to Figure 1 and paragraphs [0093]-[0096], Kishimoto et al. teach a plasma processing apparatus wherein uppermost 4 and lowermost 2 electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer in order to bring the plasma discharges occurring at a plurality of the discharge portion into a state where they uniformly match to one another (pars.[0033]-[0036]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Maher, Jr. et al. with wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer as taught by Kishimoto et al. in order to bring the plasma discharges occurring at a plurality of the discharge portion into a state where they uniformly match to one another. The resulting apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. would yield wherein a processing container that heats the plurality of substrates; wherein a first electrode layer and a second electrode layer embedded in the plurality of stages; and wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer. With respect to claim 3, the plasma processing apparatus of Maher, Jr. et al. further includes wherein at least one of the first electrode layer 19b-25b and the second electrode layer 19a-25a has a mesh shape or a film shape (Fig. 4). With respect to claim 7, the plasma processing apparatus of Maher, Jr. et al. further includes wherein the first electrode layer 19b-25b in a first stage among the plurality of stages faces the second electrode layer 19a-25a in a second stage adjacent to the first stage with a plasma processing space interposed between the first electrode layer 19b-25b and the second electrode layer 19a-25a, and the second electrode layer 19a-25a in the first stage faces the first electrode layer19b-25b in a third stage adjacent to the first stage with the plasma processing space interposed between the second electrode layer 19a-25a and the first electrode layer 19b-25b, and wherein the substrate holder 19c-25c is configured to generate plasma in the plasma processing space between the first stage and the second stage and between the first stage and the third stage, and perform a plasma processing on the plurality of substrates when the radio frequency power 44 is supplied to the first electrode layers 19b-25b in the first stage and in the third stage (Fig. 4, col. 6, line 50-col. 7, line 4). With respect to claim 8, Maher, Jr. et al. in view of Ravi et al. is silent on wherein the substrate holder 20 includes a lift pin mechanism 21 configured to transfer the plurality of substrates to the plurality of stages, respectively. Referring to page 6, paragraph 2, Kim et al. teach a plasma processing apparatus wherein the substrate holder 20 includes a lift pin mechanism 21 configured to transfer the plurality of substrates to the plurality of stages, respectively. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the substrate holder of Maher, Jr. et al. a lift pin mechanism configured to transfer the plurality of substrates to the plurality of stages, respectively as taught by Kim et al. for substrate lifting. With respect to claim 9, the plasma processing apparatus of Maher, Jr. et al. further includes wherein each of the plurality of stages of the substrate holder 19c-25c has a placement surface on which the substrate is placed (Fig. 4). With respect to claim 10, the plasma processing apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. further includes wherein the first electrode layer 50 and the second electrode layer 20 have circular outer edges, and the circular outer edges of the first electrode layer and the second electrode layer are larger than or the same as an outer edge of the placement surface (Kim et al., Fig. 2). With respect to claim 11, the plasma processing apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. further includes wherein the outer edge of the first electrode layer and the outer edge of the second electrode layer have the same size (Kim et al., Fig. 2). With respect to claim 12, Maher, Jr. et al. in view of Ravi et al. is silent on wherein the substrate holder includes a plurality of hollow post members made of the dielectric material and provided to extend in the height direction at an outer peripheral side of the placement surface. Referring to page 8, paragraphs 2-3 and page 9, paragraph 10-page 10, paragraph 1, Kim et al. teach a plasma processing apparatus wherein the substrate holder includes a plurality of hollow post members 49, 79 made of the dielectric material and provided to extend in the height direction at an outer peripheral side of the placement surface as a means to provide RF power 75 and ground lines 45 to the substrate holder. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the substrate holder of Maher, Jr. et al. in view of Ravi et al. to include a plurality of hollow post members made of the dielectric material and provided to extend in the height direction at an outer peripheral side of the placement surface as taught by Kim. et al. as a means to provide RF power and ground lines to the substrate holder. With respect to claim 13, the plasma processing apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. further includes wherein a ground line 45 connected to the second electrode layer in the plurality of stages is accommodated in at least one of the plurality of hollow post members 40 (Kim et al.-Fig. 4a). With respect to claim 14, the plasma processing apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. further comprising: a radio frequency power supply configured to output radio frequency power, wherein a feeder line 75 that connects the radio frequency power supply and the first electrode layer in the plurality of stages is accommodated in at least one of the plurality of hollow post members 70 (Kim et al.-page 9, paragraph 10-page 10, paragraph 1). With respect to claim 16, the plasma processing apparatus of Maher, Jr. et al. further includes comprising: a radio frequency power supply 44 configured to output a radio frequency power; and a distributor (i.e. feed lines from RF power supply 44) configured to distribute the radio frequency power output from the radio frequency power supply, wherein the radio frequency power is distributed and supplied to a plurality of first electrode layers 19b-25b in the plurality of stages (Fig. 4, col. 6, lines 55-63). With respect to claim 17, the plasma processing apparatus of Maher, Jr. et al. further includes wherein, among the plurality of stages, the second electrode layer 19a-25a is arranged above the first electrode layer 19b-25b in the plurality of stages 19c-25c (Fig. 4). Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maher, Jr. et al. (U.S. 4,381,965) in view of Kim et al. (KR101394110B1), Ravi et al. (2021/0032753), and Kishimoto et al. (U.S. 2011/0312167) as applied to claims 1, 3, 7, 8-14, and 16-17 above, and further in view of Ishisaka et al. (U.S. 8,197,638). The teachings of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. have been discussed above. Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. fail to teach wherein, when the at least one of the first electrode layer and the second electrode layer has the mesh shape, a dielectric pillar is arranged to pass through a gap in the mesh shape. Referring to Figure 2 and column 4, lines 27-59, column 6, line 61-column 7, line 59, Ishisaka an electrode layer 51 has the mesh shape and a dielectric pillar 50 is arranged to pass through a gap in the mesh shape in order to provide support to the substrate holder and provide uniform voltage distribution across the entire substrate holder to promote process uniformity. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the substrate holder of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al.to include at least one of the first electrode layer and the second electrode layer has the mesh shape, a dielectric pillar is arranged to pass through a gap in the mesh shape as taught by Ishisaka et al. in order to provide support to the substrate holder and provide uniform voltage distribution across the entire substrate holder to promote process uniformity. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maher, Jr. et al. (U.S. 4,381,965) in view of Kim et al. (KR101394110B1), Ravi et al. (2021/0032753), and Kishimoto et al. (U.S. 2011/0312167) as applied to claims 1, 3, 7, 8-14, and 16-17 above, and further in view of Sadjadi et al. (U.S. 2015/0311105). The teachings of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. have been discussed above. Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. fail to teach wherein the second electrode layer is connected to the ground via an impedance adjuster. Referring to Figure 4 and paragraphs [0062]-[0063], Sadjadi et al. teach a plasma processing apparatus wherein the second electrode layer 140 is connected to the ground via an impedance adjuster 410 in order to enable precise process control during substrate processing. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the substrate holder of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. with wherein the second electrode layer is connected to the ground via an impedance adjuster as taught by Sadjadi et al. in order to enable precise process control during substrate processing. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maher, Jr. et al. (U.S. 4,381,965) in view of Kim et al. (KR101394110B1), Ravi et al. (2021/0032753), and Kishimoto et al. (U.S. 2011/0312167) as applied to claims 1, 3, 7, 8-14, and 16-17 above, and further in view of Hanawa et al. (U.S. 2004/0027781). The teachings of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. have been discussed above. Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. fail to teach wherein an inner wall of the plurality of hollow post members is covered with a metal film or a metal cylindrical member, and wherein the metal film or the metal cylindrical member is connected to a ground and functions as a ground line that grounds the second electrode layer in the plurality of stages. With respect to claim 15, referring to paragraphs [0025]-[0027], the plasma processing apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. teaches the concept of a substrate stage having a co-axial structure of a metal cylindrical member 285 that is connected to ground surrounding an RF feeder line 230 for the purpose of switching from a two wire structure to a coaxial structure to virtually eliminate (or avoid) losses due to RF heating of other components or other materials. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the ground line of Maher, Jr. et al. in view of Kim et al., Ravi et al. and Kishimoto et al. with the metal cylindrical member is connected to a ground and functions as a ground line that grounds the second electrode layer in the stage as taught by Hanawa et al. for the purpose of switching from a two wire structure to a coaxial structure to virtually eliminate (or avoid) losses due to RF heating of other components or other materials. The resulting apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al., Kishimoto et al. and Hanawa et al. further includes wherein an inner wall of the plurality of hollow post members is covered with a metal film or a metal cylindrical member, and wherein the metal film or the metal cylindrical member is connected to a ground and functions as a ground line that grounds the second electrode layer in the plurality of stages. Response to Arguments Applicant's arguments filed July 7, 2026 have been fully considered but they are not persuasive. With regards to applicant’s argument that Fu et al. does not qualify as prior art, as stated above, applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. Therefore, Fu et al. currently is considered prior art and hence the apparatus of Fu et al. in view of Kishimoto et al. satisfies the claimed requirements. Applicant’s arguments with respect to Maher, Jr. et al. in view of Kim et al., Ravi et al., and Kishimoto et al. have been considered but are moot because the new reference Kishimoto et al. teaches wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer. Therefore, the apparatus of Maher, Jr. et al. in view of Kim et al., Ravi et al., and Kishimoto et al. satisfy the claimed requirements. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Torregrosa et al.’695, Engle’598, and Babu et al.’359 teach wherein uppermost and lowermost electrode layers among the first electrode layer and the second electrode layer embedded in the plurality of stages constitute the second electrode layer. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michelle CROWELL whose telephone number is (571)272-1432. The examiner can normally be reached Monday-Thursday 10:00am-6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Parviz Hassanzadeh can be reached at 571-272-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michelle CROWELL/Examiner, Art Unit 1716 /SYLVIA MACARTHUR/Primary Examiner, Art Unit 1716
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Prosecution Timeline

Jan 26, 2023
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §103
Jul 07, 2026
Response Filed
Oct 09, 2026
Final Rejection mailed — §103 (current)

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