Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 9-15, 17 and 19-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Lee (US 2019/0228128)
Regarding claims 1-2, the prior art discloses:
A method comprising:
determining by a design tool (fig 1, CAD tool (par 5-6)) whether or not an initial value specified for a candidate register can be removed (i.e., determine initial/power-up logic/state/condition of a register can or cannot be preserved/eliminated (see par 21-24, 32-22, 45, 49-51 and/or fig 5-17) based on an input logic cone to the candidate register and an output logic cone from the candidate register ( see fan-in/merging, fan-out (fig 5-8, 12-16),
wherein the candidate register is a register in a critical path (par 31, 43-45 and/or fig 3-6) in a circuit design;
retiming, by including backward retiming the candidate register (see par 17-18, 23-27 and/or fig 7-8, 13-117) into a retimed register by the design tool in response to determining that the initial value specified for the candidate register can be removed (see par 17-18, 23-27 and/or fig 7-8, 13-117);
deriving a new initial value for the retimed register (see one or more of changing/computing new power-up states for retimed registers (par 5, 48-50, 54-55, 61),changed the power-up state for one of the registers to enable backwards retiming (par 18),initial state of the register is changed to 1 to preserve the initial condition (par 19);compute new initial states (e.g., power-up) for all registers in the retimed circuit using the initial states (par 32)) by the design tool based on initial values of registers in a logic cone of the retimed register;
and assigning the new initial value to the retimed register by the design tool (see one or more of changing/computing new power-up states for retimed registers (par 5, 48-50, 54-55, 61),changed the power-up state for one of the registers to enable backwards retiming (par 18),initial state of the register is changed to 1 to preserve the initial condition (par 19);compute new initial states (e.g., power-up) for all registers in the retimed circuit using the initial states (par 32)).
(Claims 3-4) wherein the deriving the new initial value includes deriving the new initial value based on initial values of starting points of the input logic cone (upstream/source of merging/fan-in (fig 5-8, 12-17); wherein the retiming includes forward retiming the candidate register (par 44-45, 50-52 and/or fig 6, 12).
(Claim 5) wherein the deriving the new initial value includes deriving the new initial value based on initial values of reachable endpoints (downstream/sink/arriving /destination points (one or more of fig 3-17) of the output logic cone.
(Claim 7) wherein the deriving the new initial value includes: determining whether or not a known logic value is output from combinational logic (fig 5-6, 9-13, 17) connected to an output of the candidate register, independent of an initial value of the retimed register; and indicating that the new initial value can be either logic 0 or logic 1 (par 47-53, 55-60) in response to determining that the known logic value is output.
(Claim 9) evaluating the circuit design to determine whether or not a timing constraint is satisfied after retiming the candidate register (fig 2); and restoring the candidate register to and deleting the retimed register from the circuit design in response to determining that the timing constraint is not satisfied (fig 3-17).
(Claim 10) placing and routing (fig 2) the circuit design; and generating configuration data after the placing and routing for implementing an IC ()
Claims 11-15, 17, and 19-20 recite similar subject matter and are rejected for the same reason
Claims 1-5, 7, 9-15, 17 and 19-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Iyer (US 2018/0349544)
Regarding claims 1-2, the prior art discloses:
A method comprising:
determining by a design tool (computer / CAD Tool EDA tool/ Circuit design too (fig 4-5, Par 51) whether or not an initial value specified for a candidate register can be removed ( because when the integrated circuit is powered up, these digital flip-flops may be powered to an unknown initial stat or integrated circuit may be powered up in any number of legal or illegal states (par 4, 80, 82) and maintaining initial states can restrict retiming (par 16, 93)) based on an input logic cone to the candidate register and an output logic cone from the candidate register (see fan-in, fan-out in fig 8-10, 12),
wherein the candidate register is a register in a critical path (par 38) in a circuit design;
retiming (title), by including backward retiming (see one or more of abstract, fig 12, par 37, 63, 94, 103-110, 120-121) the candidate register into a retimed register by the design tool in response to determining that the initial value specified for the candidate register can be removed;
deriving a new initial value for the retimed register by the design tool based on initial values of registers in a logic cone of the retimed register; (see one or more of the following:
abstract: When performing backward retiming, initial states of the retimed registers may be computed that is consistent with the original initial state,
Par 82: IC may be powered up in any number of legal or illegal states, the reset sequence may ensure that the integrated circuit reaches the reset state, and the integrated circuit may then be operated in any of the legal
Par 92: retimer to compute and respect register initial states,
Par 103: FIG. 12A illustrates an example where all of pre-retimed registers 1202 (e.g., flip-flops or other clocked storage element) have a don't-care (X) value. The output registers 1202 may be backward retimed across combinational logic 1200, as indicated by arrow 1206. Since all of the original pre-retimed registers 1202 have X values, all of the retimed registers 1204 may also exhibit don't-care (X) values.
Par 106: retimed register 1260′ may have a corresponding initial state of “1” to maintain the pre-retimed initial state for register 1260-2. Such initial state assignment might be pessimistic since it assumes that a logic “1” is still required at the bottom branch of fan-out node 1250.
Par 107:After performing backward retiming, retimed register 1260′ may have a corresponding initial state of “0” to maintain the pre-retimed initial state for register 1260-2. Such initial state assignment might be pessimistic since it assumes that a logic “0” is still required at the bottom branch of fan-out node 1250.
Par 116-117: retimed registers 1360-1 and 1360-2 may each have a corresponding initial state of “1” to maintain the pre-retimed initial state for register 1360.
Par 121:backward retiming is performed while preserving the computed input initial state values (e.g., the retimed registers will be powered up in the computed initial states
and assigning the new initial value to the retimed register by the design tool ( see one or more of par 92, 103, 106-107, 116-117, 121)
(Claims 3-4) wherein the deriving the new initial value includes deriving the new initial value based on initial values of starting points of the input logic cone (fan-in in fig 8); wherein the retiming includes forward retiming (see one or more of par: 39, 63, 110-118, 135-136, 144, 154) the candidate register.
(Claim 5) wherein the deriving the new initial value includes deriving the new initial value based on initial values of reachable endpoints (see termination/arriving/down-stream/sink points in one or more of fig 2, 8-10, 12-13 ) of the output logic cone.
(Claim 7) wherein the deriving the new initial value includes: determining whether or not a known logic value is output from combinational logic (fig 2, 8, 10, 12-13) connected to an output of the candidate register, independent of an initial value of the retimed register; and indicating that the new initial value can be either logic 0 or logic 1 (see one or more of par 97-118) in response to determining that the known logic value is output.
(Claim 9) evaluating the circuit design to determine whether or not a timing constraint is satisfied after retiming the candidate register; and restoring the candidate register to and deleting the retimed register from the circuit design in response to determining that the timing constraint is not satisfied (fig 5-6 and related text).
(Claim 10) placing and routing the circuit design; and generating configuration data after the placing and routing for implementing an IC (fig 5-6)
Claims 11-15, 17, and 19-20 recite similar subject matter and are rejected for the same reason.
Allowable Subject Matter
Claims 6, 8, 16, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6, 8, 16, 18 would be allowable because the prior art of record does not teach or suggest the limitations in:
Claim 6 and similarly recited claim 16; and
Claim 8 and similarly recited claim 18
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/Primary Examiner, Art Unit 2851