Prosecution Insights
Last updated: April 19, 2026
Application No. 18/102,808

SEMICONDUCTOR DEVICE

Non-Final OA §103§112§DP
Filed
Jan 30, 2023
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co. Ltd.
OA Round
3 (Non-Final)
40%
Grant Probability
At Risk
3-4
OA Rounds
3y 7m
To Grant
70%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allow Rate
148 granted / 375 resolved
-28.5% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
61 currently pending
Career history
436
Total Applications
across all art units

Statute-Specific Performance

§103
42.1%
+2.1% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
33.1%
-6.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§103 §112 §DP
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/10/2025 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claims 1 and 4, the limitation “in the channel length direction, a width of the first gate electrode is larger than a width of the second gate electrode,” does not appear to have support in the originally filed disclosure. Specifically, there is no disclosure of the relative widths of the gates. It is noted that drawings are not to scale (see MPEP 2125 and [0027] of Applicant’s disclosure). For the claimed invention which requires the relative extension of the semiconductor layer beyond the semiconductor layer and second gate beyond the semiconductor layer, as recited in claims 1 and 4 (see also elected Fig. 15A-C and page 4, para. 1 of Applicant remarks filed 11/10/2025), the relative widths of the gates cannot be ascertained from the figures other than in an attempt to determine the widths based on scale. Note the dependent claims do not cure the deficiencies of the claims on which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakata et al. (US 2011/0003418; herein “Sakata”) in view of Huang et al. (US 5,917,210; herein “Huang”). Regarding claims 1 and 4, Sakata discloses in Fig. 1C and related text a semiconductor device comprising: a second gate (401C, see [0130]) electrode over a substrate (400); a semiconductor layer (403, see [0069]) over the second gate electrode; a source electrode and a drain electrode (405a/b, see [0115]), each over and in contact with the semiconductor layer; and a first gate electrode (409C, see [0130]) over the source electrode and the drain electrode, wherein the first gate electrode (409C) overlaps both of the source electrode and the drain electrode (405a/b), wherein, in a channel length direction (horizontal as shown in Fig. 1C), one end of the semiconductor layer (e.g. left end of 403) extends beyond one end of the first gate electrode (e.g. left end of 409C), and another end of the semiconductor layer (e.g. right end of 403) extends beyond another end of the first gate electrode (e.g. right end of 409C), and wherein, in the channel length direction, one end of the second gate electrode (e.g. left end of 401C) extends beyond the one end of the semiconductor layer (the left end 403); and wherein each of the first gate electrode (409C), the second gate electrode (401C), the source electrode and the drain electrode (405a/b) extends in a channel width direction. Sakata does not explicitly disclose in the channel length direction, another end of the second gate electrode does not extend beyond another end of the semiconductor layer; wherein, in the channel length direction, a width of the first gate electrode is larger than a width of the second gate electrode. In the same field of endeavor, Huang teaches in Fig. 4 and related text a semiconductor device comprising a second gate electrode (e.g. left 31, see col. 5 line 14), wherein, in the channel length direction, one end of the second gate electrode (e.g. left end of left 31) extends beyond the one end of the semiconductor layer (33, see col. 5 line 17) another end of the second gate electrode (e.g. right end of left 31) does not extend beyond another end of the semiconductor layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sakata by having another end of the second gate electrode does not extend beyond another end of the semiconductor layer in the channel length direction, as taught by Huang, in order to reduce parasitic capacitance in the transistor (see col. 1 lines 4-7). Further, it would have been obvious to modify the device of Sakata and Huang to have the width of the first gate electrode be larger than the width of the second gate electrode because it would have been an obvious matter of design, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Additionally, it would have been obvious for the purpose of choosing from a finite number of identified, predictable solutions (i.e. larger than, smaller than, or equal to), with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)). Lastly, note that one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the width to be a result effective variable affecting parasitic capacitance of the gate and control of the channel. Thus, it would have been obvious to modify the device of Sakata and Huang to have the widths within the claimed range in order to achieve a desired balance parasitic capacitance and control of the channel, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Regarding claims 2 and 5, Sakata further discloses wherein a gate insulating layer (402/407, see [0069]) is provided between the second gate electrode (401C) and the semiconductor layer (403), and between the semiconductor layer and the first gate electrode (409C). Regarding claims 3 and 6, Sakata further discloses wherein the semiconductor layer (403) is an oxide semiconductor layer (see [0069]). Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6 of U.S. Patent No. 11,581,439 in view of Sakata. Regarding claims 1 and 4, claim 1 of ‘439 teaches all of the claimed limitations of the instant application except for both ends of the semiconductor layer extend beyond both ends of the first gate electrode and the width of the first gate electrode be larger than the width of the second gate electrode. In the same field of endeavor, Sakata teaches the limitation in the manner outlined above. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claims of ‘439 by having both ends of the semiconductor layer extend beyond both ends of the first gate electrode, as taught by Sakata because Sakata shows that both ends of the semiconductor layer extending beyond both ends of the first gate electrode is equivalent to both ends of the semiconductor layer not extending beyond both ends of the first gate electrode are equivalent structures known in the art (see Figs. 1A-C). Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute the both ends of the semiconductor layer extending beyond both ends of the first gate electrode for another structure without the feature. Note that the first gate electrode, the second gate electrode, the source electrode, and the drain electrode extending in a channel width direction is understood to be a feature that would be present in any three-dimensional object. Therefore, while it is not explicitly recited in the claims of ‘439, it is understood to be a feature of the electrodes recited. Further, it would have been obvious to modify the device of Sakata and Huang to have the width of the first gate electrode be larger than the width of the second gate electrode because it would have been an obvious matter of design, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Additionally, it would have been obvious for the purpose of choosing from a finite number of identified, predictable solutions (i.e. larger than, smaller than, or equal to), with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)). Lastly, note that one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the width to be a result effective variable affecting parasitic capacitance of the gate and control of the channel. Thus, it would have been obvious to modify the device of Sakata and Huang to have the widths within the claimed range in order to achieve a desired balance parasitic capacitance and control of the channel, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Regarding claims 2 and 5, the additional limitation of the instant application is further taught by claim 1 of ‘439. Regarding claims 3 and 6, the additional limitation of the instant application is taught by claim 6 of ‘439. Response to Arguments Applicant's arguments filed 11/10/2025 have been fully considered but are moot in view of the new grounds of rejection presented above, in particular the newly presented obviousness rationale as it relates to the relative widths of the gates. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 2/3/2026
Read full office action

Prosecution Timeline

Jan 30, 2023
Application Filed
May 05, 2025
Non-Final Rejection — §103, §112, §DP
Jul 29, 2025
Response Filed
Aug 12, 2025
Final Rejection — §103, §112, §DP
Nov 10, 2025
Request for Continued Examination
Nov 14, 2025
Response after Non-Final Action
Feb 03, 2026
Non-Final Rejection — §103, §112, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
40%
Grant Probability
70%
With Interview (+30.7%)
3y 7m
Median Time to Grant
High
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allow rate.

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