DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Remarks files February 17th, 2026 in response to the Non-Final Office Action mailed 11/19/2025 are noted.
3. Claims 2 and 5-6 are now canceled; Claims 1, 3-4, and 7-20 remain pending in the application; Claims 1, 3-4, and 7-14 are now withdrawn.
4. Claims 15-20 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Moder (U.S. PG Pub No US2020/0286730A1) (of record) in view of Sakaguchi (U.S. PG Pub No US2001/0044216A1) (of record) and Lochtefeld (U.S. PG Pub No US2012/0067423A1) (of record). *Kudymov (U.S. PG Pub No US 2019/0096877A1) (of record) is provided as evidentiary support for claim 20*
Regarding claim 15, Moder teaches a method [see figs. 4A-4C, 0079, 0109] of fabricating a layered structure (900) fig. 4C [0113] comprising steps to:
grow an epitaxial layer (comprising 710, 720) fig. 4A [0080] (“obtained by epitaxy”) on a substrate (705 of 700) fig. 4A [0084], wherein the substrate (705) is silicon [0029, 0084], wherein the epitaxial layer (comprising 710) has a first resistivity proximal (in lower portion of 710 nearer to 705) to the substrate (705) and a second resistivity distal (in upper portion of 710 further from 705) from the substrate (705), and wherein the second resistivity is less than the first resistivity (710 could be implemented with a “non-uniform vertical dopant profile” [0084] having greater concentration of dopants in upper end than lower end, resulting in greater conductivity/lower resistivity in upper/distal portion of 710) (further, many different dopant distributions in 710, 720 may be contemplated [0053-0063, 0068, 0082-0087, 0110]);
porosify [0088, 0112] the epitaxial layer (comprising 710, 720) to form a porous layer (820) fig. 4B [0088, 0107, 0112] with porosity greater than 30% proximal (in lower end of “coarse-porous” 710/821 [0088, 0107, 0112] – porosity may be 30-80% [0041-0042]) the substrate (705) and porosity less than or equal to 25% (may be 5-25% in “fine-porous” [0088, 0107, 0112] upper end of 825/720 [0041-0042]) distal from the substrate (705); and
epitaxially grow [0112] a semiconductor layer (730) fig. 4C [0112] over the porous layer (820).
However, Moder does not explicitly disclose wherein the substrate (705) is silicon (and) wherein the epitaxial layer (710, 720) is silicon (epitaxial layer may be GaAs [0052] instead),
and wherein the first resistivity is in a range between 0.4 ohm-cm and 10 ohm-cm and the second resistivity is in a range between 0.01 ohm-cm and 0.4 ohm-cm (of n-doped epitaxial layer 710, 720).
Sakaguchi teaches a method [see title, 0100] wherein the substrate (comprising 501) fig. 3B [0100]is silicon, wherein the epitaxial [0070] layer (503) fig. 3B [0100] is silicon (or GaAs) [0100, 0278].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Moder such that the epitaxial layer is formed of single-crystal silicon [0070, 0100, 0278] instead of epitaxially-grown, single crystal GaAs [0278] in order to enable the formation of different types of devices possibly better suited for silicon material, such as MOSFETs [0100, 0287], as well as silicon’s favorable etching characteristics [0279], as taught by Sakaguchi.
However, Moder in view of Sakaguchi does not explicitly disclose wherein the first resistivity is in a range between 0.4 ohm-cm and 10 ohm-cm and the second resistivity is in a range between 0.01 ohm-cm and 0.4 ohm-cm (does not explicitly disclose resistivity of n-doped silicon epitaxial layer 710, 720).
Lochtefeld teaches a method [see title, 0029] wherein the first resistivity (of 104) fig. 1B [0029] is in a range between 0.4 ohm-cm and 10 ohm-cm (0.1-5 ohm-cm) [0029] and the second resistivity (of 104) fig. 1B [0029] is in a range between 0.01 ohm-cm and 0.4 ohm-cm (0.1-5 ohm-cm) [0029].
[0029] of Lochtefeld indicates that n-doped epitaxial silicon film 104 may have a resistivities of 0.1-5 ohm-cm [0029] throughout; when implemented in the non-uniform vertical dopant profile of Moder’s n-doped silicon layer, the first resistivity could be ~3 ohm-cm while the second resistivity is ~0.3 ohm-cm, falling within both the claimed range and those disclosed by [0029] of Lochtefeld.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Moder in view of Sakaguchi such that the epitaxial layer formed of non-uniformly n-doped single-crystal silicon has a resistivity in the range of 0.1-5 ohm-cm [0029] promote low-resistance connections with adjacent layers [0029] according to art-recognized resistivity and implied doping levels [0029], as taught by Lochtefeld.
Regarding claim 16, Moder teaches the method [see figs. 4A-4C, 0079, 0109] of claim 15. Moder also teaches further comprising doping the epitaxial layer (comprising 710, 720) fig. 4A [0080] during the step to grow the epitaxial layer (epitaxial 710, 720 provided as doped-layers [0080-0086]).
Regarding claim 17, Moder teaches the method [see figs. 4A-4C, 0079, 0109] of claim 16. Moder also teaches wherein the doping comprises doping the epitaxial layer (comprising 710) fig. 4A [0080] with a lower level of dopant (710 could be implemented with a “non-uniform vertical dopant profile” [0084] having greater concentration of dopants in upper end than lower end) proximal to the substrate (705) fig. 4A [0084] than adjacent to the channel layer.
Regarding claim 18, Moder teaches the method [see figs. 4A-4C, 0079, 0109] of claim 15. Moder also teaches further comprising a step to ion implant [see figs. 4A, 0109-0110] at least part of the epitaxial layer (comprising 710, 720) fig. 4A [0080] (to form 725 regions) [fig. 4A, 0110] prior to the step to porosify [see fig. 4B, 0112] the epitaxial layer (to form 820) fig. 4B [0088-0089, 0112].
Regarding claim 19, Moder teaches the method [see figs. 4A-4C, 0079, 0109] of claim 15. Moder also teaches further wherein the step to porosify [see fig, 4B, 0088-0089, 0112] the epitaxial layer (comprising 710, 720) fig. 4A [0080] further comprises porosifying (base layer 705 could also be porsofied [0089]) at least an upper part of the substrate (705) fig. 4A [0084], wherein the upper part of the substrate (705) has the first resistivity (as part of 710 --- prior to porsification, 705 could have same dopant concentration as 710 [0085]).
Regarding claim 20, Moder teaches the method [see figs. 4A-4C, 0079, 0109] of claim 15. Moder also teaches further comprising a step to provide a source, a drain, and a gate over the semiconductor layer (730) fig. 4C [0090-0091] to form a switch [0091], wherein the semiconductor layer (730) fig. 4C [0090-0091] forms a channel layer [0091].
With respect to the underlined, Moder does not explicitly depict a source, drain, gate and channel. However, [0093] of Moder indicates that epitaxial layer 730 is used to form a “power switch”, and the claimed components (i.e., a source, a drain, a gate, a channel …) are well-known for a power-switch transistor. As evidence of this, see [0019-0024] of Kudymov (U.S. PG Pub No US 2019/0096877A1) as well as exemplary embodiments such as fig. 5 of Kudymov.
Response to Arguments
Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive.
With respect to Applicant’s argument(s) regarding the combination of references under 35 U.S.C. 103 - Moder (U.S. PG Pub No US2020/0286730A1) (of record) in view of Sakaguchi (U.S. PG Pub No US2001/0044216A1) (of record) and Lochtefeld (U.S. PG Pub No US2012/0067423A1) (of record) - that “Thus, Lochtefeld neither discloses steps to "grow an epitaxial layer on a substrate" nor an epitaxial layer having two resistivities with the claimed ranges. Rather, at most Lochtefeld discloses a substrate with a single resistivity being porosified to two porosities. Therefore, Lochtefeld does not disclose an epitaxial layer on a substrate having the claimed two resistivity ranges, and does not remedy the deficiencies of the Office's proposed combination of Moder-Sakaguchi.“ the only limitation(s) missing from the combination of Moder in view of Sakaguchi is/are “wherein the first resistivity is in a range between 0.4 ohm-cm and 10 ohm-cm and the second resistivity is in a range between 0.01 ohm-cm and 0.4 ohm-cm” – because Moder in view of Sakaguchi does not explicitly disclose the “resistivity of n-doped silicon epitaxial layer 710, 720” as was acknowledged in the rejection of record, maintained above.
Lochefeld need not specifically address the various qualities of the layer cited by Applicant in their Remarks (such as the porosity of the layer, whether it is grown on the claimed substrate) because Moder in view of Sakaguchi already discloses these features. Rather, Lochefeld is only used to evidence that the n-doped silicon film(s) of Moder in view of Sakaguchi may be implemented as “[0029 Lochefeld] an n-doped epitaxial silicon film 104 … with in-situ doping to give resistivity of e.g. 0.1-5.0 ohm-cm” --- Moder in view of Sakaguchi already teaches the other aspects of the claimed invention recited in independent claim 14. The difference in method of production between the Lochefeld and Moder in view of Sakaguchi is irrelevant with respect to the missing limitations of Lochefeld in the context of claim 14, as these are already addressed by Moder in view of Sakaguchi.
Again, Lochefeld is only used to evidence that ‘the first resistivity (of the n-doped epitaxial silicon material could be) in a range between 0.4 ohm-cm and 10 ohm-cm and the second resistivity (of the n-doped epitaxial silicon material could be) in a range between 0.01 ohm-cm and 0.4 ohm-cm” by explicitly disclosing ‘[0029 Lochefeld] an n-doped epitaxial silicon film 104 … with in-situ doping to give resistivity of e.g. 0.1-5.0 ohm-cm’, thereby establishing that the resistivity ranges recited by Applicant in claim 14 are reasonable and art-recognized for an n-doped epitaxial silicon material, such as that of Moder in view of Sakaguchi.
Therefore, the 35 U.S.C. 103 of claim 14 is maintained over the combination of Moder (U.S. PG Pub No US2020/0286730A1) (of record) in view of Sakaguchi (U.S. PG Pub No US2001/0044216A1) (of record) and Lochtefeld (U.S. PG Pub No US2012/0067423A1) (of record).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature semiconductor devices with porous layers.
Ravi (US 20130180578 A1) (of record) teaches a porous-stacked structure in which the epitaxial silicon layer has upper and lower portions with resistivities on the order of the claimed ranges. See, for example, fig. 5 of Ravi below.
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THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/11/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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