DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 31-40 are rejected under U.S.C. 103 as being unpatentable over Toyama et al.; US 2014/0226415 A1; 02/2014 in view of Chen et al.; US 2021/0280591 A1; 03/2020 and further in view of Lin et al.; US 2021/0328034 A1; 04/2020
Claim 1: Toyama discloses, a memory device ( [0034] a non-volatile memory ), comprising: a first well region ( [0034] the bit line switch transistors may be formed in a first triple well including a first well, a second well, and a substrate) , a second well region ( [0034] the bit line switch transistors may be formed in a first triple well including a first well, a second well, and a substrate), and a plurality of third well regions disposed within a substrate ( [0034] the memory array may be formed in a second triple well including a third well, a fourth well and the substrate), wherein the second well region (Fig. 3 n-well region #434) is interposed between the first region (Fig. 3 p-type substrate region #436 ) and the plurality of third well regions (Fig. 3 p-well region #432) along a first lateral direction ( Fig. 3 control gates of storage elements 408, 410, …, 422) and wherein the plurality of third well regions are separated from one another along a second lateral direction perpendicular to the first lateral direction ( [0043] WL0, WL1, …, WL7 can extend via the control gates of storage elements 408, 410, …, 422); a plurality of floating gates ( [0036] Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate) disposed over the first to third well regions ( [0038] The word lines comprise the rows of the array or set. Each word line connects the control gates of each storage element in the row)
Toyama does not appear to disclose in an axial direction perpendicular to the first lateral direction and the second lateral direction; each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first lateral direction; a bit line write region disposed within the second well region, wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates; and a bit line read region disposed within the second well region and spaced from the bit line write region along the first lateral direction, wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates.
Lin discloses in an axial direction perpendicular to the first lateral direction and the second lateral direction ( [0063] The active regions (62,66) may include axial active regions 62 that are laterally offset from a most proximal one of the floating gate electrodes 22 along the axial direction )
Lin does not appear to disclose each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first lateral direction; a bit line write region disposed within the second well region, wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates; and a bit line read region disposed within the second well region and spaced from the bit line write region along the first lateral direction, wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates.
However, Chen teaches each of the plurality of floating gates ( Fig. 5 FG1 and FG2) continuously extends from the first well region( Fig. 5 #104 ) to a corresponding one of the third well regions ( Fig. 5 #108) along the first lateral direction ( as shown in Fig. 5 ); a bit line write region ( [0030] the first BL1 and/or the bit line write region (e.g. 112 of Fig. 1A) may be utilized during a write operation. During the write operation, an unselect bias voltage may be applied to the second bit line BL2, such that the bit line read region (e.g. 114 of Fig. 1A) is unselected ) disposed within the second well region ( Fig. 1A #112 ), wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates ( Fig. 1A #112); and a bit line read region ( [0030] the first BL1 and/or the bit line write region (e.g. 112 of Fig. 1A) may be utilized during a write operation. During the write operation, an unselect bias voltage may be applied to the second bit line BL2, such that the bit line read region (e.g. 114 of Fig. 1A) is unselected) disposed within the second well region ( F9g. 1A #114 ) and spaced from the bit line write region along the first lateral direction ( Fig. 2 BL1 and BL2) , wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates ( Fig. 1A #114).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Lin and Toyama to implement each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first lateral direction; a bit line write region disposed within the second well region, wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates; and a bit line read region disposed within the second well region and spaced from the bit line write region along the first lateral direction, wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates because the continuous extension of each floating gate from the first well region to a corresponding one of a third well region is a specific design feature typically found in NAND flash memory devices, and placing a bit line within a specific well could help isolate it reducing potential interference and improving the operation reliability.
Claim 2: Toyama, Lin, and Chen disclose the memory device of claim 1 (as discussed above).
Neither Toyama nor Lin appear to disclose the first lateral direction, a width of the bit line write region is less than a width of the bit line read region.
However, Chen teaches the first lateral direction, a width of the bit line write region ([0023] In some embodiments, a width Ww of the bit line write region 112 is less than a width Wr of the bit line read region) is less than a width of the bit line read region (Fig. 1A: Wr).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the first lateral direction, a width of the bit line write region is less than a width of the bit line read region because a narrow write region makes it easier to write data by reducing the latch during writing without negatively impacting the cell’s ability during read operations.
Claim 3: Toyama, Lin, and Chen disclose the memory device of claim 1 (as discussed above).
Neither Toyama nor Lin appear to disclose the second lateral direction, each of the floating gates has a first width over the first well region, a second width over the second well region, and a third width over each of the third well regions, wherein the first width is less than the second width and the second width is less than or equal to the third width.
However, Chen teaches the second lateral direction, each of the floating gates has a first width over the first well region (Fig. 1A (FG) 120 over #104), a second width over the second well region ( Fig. 1A FG1 and FG2 over #106), and a third width over each of the third well regions (Fig. 1A #126), wherein the first width is less than the second width (Fig. 1A first width is shown to be less than second width) and the second width is less than or equal to the third width (Fig. 1A second width is shown to be less than third width).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the second lateral direction, each of the floating gates has a first width over the first well region, a second width over the second well region, and a third width over each of the third well regions, wherein the first width is less than the second width and the second width is less than or equal to the third width because this approach fine-tunes the threshold voltage for each region.
Claim 4: Toyama, Lin, and Chen disclose the memory device of claim 1 (as discussed above).
Neither Toyama nor Lin appear to disclose an isolation structure disposed within a front-side surface of the substrate, wherein the isolation structure laterally surrounds the first well region, the second well region, and the third well regions.
However, Chen teaches an isolation structure (Fig. 1A isolation structure #103) disposed within a front-side surface of the substrate ( [0017] An isolation structure #103 extends from the front-side #102f of the substrate #102 to a point below the front-side #102f ), wherein the isolation structure laterally surrounds the first well region (Fig. 1A #103 surrounds #104), the second well region (Fig. 1A #103 surrounds #106), and the third well regions (Fig. 1A #103 surrounds #108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement an isolation structure disposed within a front-side surface of the substrate, wherein the isolation structure laterally surrounds the first well region, the second well region, and the third well regions because isolation structures are used to prevent latch-up and reduce electrical interference.
Claim 5: Toyama, Lin, and Chen disclose the memory device of claim 1 (as discussed above).
Neither Toyama nor Lin appear to disclose a plurality of dielectric structures disposed between the substrate and a corresponding one of the plurality of floating gates.
However, Chen teaches a plurality of dielectric structures (Fig. 1A dielectric structure #134) disposed between the substrate (Fig. 1A #102) and a corresponding one of the plurality of floating gates (Fig. 1A: FG).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement a plurality of dielectric structures disposed between the substrate and a corresponding one of the plurality of floating gates because this approach enables charge storage and prevent the stored charge from leaking away.
Claim 6: Toyama, Lin, and Chen disclose the memory device of claim 1 (as discussed above).
Neither Toyama nor Lin appear to disclose a single select gate continuously extending across the bit line write region and the bit line read region.
However, Chen teaches a single select gate (Fig. 1A: (SG) 116) continuously extending across the bit line write region (Fig. 1A: BL1) and the bit line read region (Fig. 1A: BL2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement a single select gate continuously extending across the bit line write region and the bit line read region because in NAND flash a continuous select gate serves as a crucial control element for accessing and isolating individual NAND strings.
Claim 7: Toyama, Lin, and Chen disclose the memory device of claim 1 (as discussed above).
Neither Toyama nor Lin appear to disclose the floating gates and a corresponding pair of the first source/drain regions operatively function as a first storage transistor of a corresponding one of a plurality of memory cells, and each of the floating gates and a corresponding pair of the second source/drain regions operatively function as a second storage transistor of the corresponding memory cell.
However, Chen teaches the floating gates and a corresponding pair of the first source/drain regions operatively function as a first storage transistor ( [0015] The first storage and selector transistors include a bit line write active region) of a corresponding one of a plurality of memory cells ( [0029] The memory array is electrically coupled to support circuitry that is configured to perform a write operation and/or a read operation on the plurality of memory cells (MCs)), and each of the floating gates and a corresponding pair of the second source/drain regions operatively function as a second storage transistor ( [0015] the second storage and selector transistors include a bit line and read active region) of the corresponding memory cell (Fig. 2 circuit #200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the floating gates and a corresponding pair of the first source/drain regions operatively function as a first storage transistor of a corresponding one of a plurality of memory cells, and each of the floating gates and a corresponding pair of the second source/drain regions operatively function as a second storage transistor of the corresponding memory cell because the ability of the floating gate to retain charge non-volatilely is key to its function as a storage transistor.
Claim 8: Toyama, Lin, and Chen disclose the memory device of claim 7 (as discussed above).
Neither Toyama nor Lin appear to disclose the floating gates and at least one of a doped region in the first well region or the first well region operatively function as a first plate and a second plate of a first capacitor of the corresponding memory cell, respectively.
However, Chen teaches the floating gates ( [0019] the first FG portion #122) and at least one of a doped region in the first well region (Fig. 1A #104) or the first well region operatively function as a first plate (Fig. 1A contact region #110a) and a second plate ( Fig. 1A contact region #110b) of a first capacitor ( [0019] A first capacitor active region #110 is disposed within the first well region #104) of the corresponding memory cell (Fig. 1A #100), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the floating gates and at least one of a doped region in the first well region or the first well region operatively function as a first plate and a second plate of a first capacitor of the corresponding memory cell, respectively because the floating gate and doped region within a well can act as a capacitor due to their physical structure and the presence of an insulating layer.
Claim 9: Toyama, Lin, and Chen disclose the memory device of claim 8 (as discussed above).
Neither Toyama nor Lin appear to disclose the floating gates and at least one of a doped region in each of the third well regions or the corresponding third well region operatively function as a first plate and a second plate of a second capacitor of the corresponding memory cell, respectively.
However, Chen teaches the floating gates and at least one of a doped region in each of the third well regions (Fig. 1A #108) or the corresponding third well region (Fig. 1A #108) operatively function as a first plate ( Fig. 1A top conductive vias #130 ) and a second plate ( Fig. 1A bottom conductive vias #130 )of a second capacitor ( [0024] a second capacitor active region #117 is disposed within the third well region #108) of the corresponding memory cell, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the floating gates and at least one of a doped region in each of the third well regions or the corresponding third well region operatively function as a first plate and a second plate of a second capacitor of the corresponding memory cell, respectively because the floating gate and doped region within a well can act as a capacitor due to their physical structure and the presence of an insulating layer.
Claim 10: Toyama, Lin, and Chen disclose the memory device of claim 9 (as discussed above).
Neither Toyama nor Lin appear to disclose the plurality of memory cells and operatively coupled to one another as a NAND memory string.
However, Chen teaches the plurality of memory cells (Fig. 2) and operatively coupled to one another as a NAND memory string ( [0028] each of the MCs may be configured as a non-volatile memory (NVM) multi-time programmable (MTP) cell ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the plurality of memory cells and operatively coupled to one another as a NAND memory string because this approach achieves higher storage density and improved performance in non-volatile memory devices.
Claim 31: Toyama discloses, a memory device ( [0034] a non-volatile memory ), comprising: a first well region ( [0034] the bit line switch transistors may be formed in a first triple well including a first well, a second well, and a substrate) , a second well region ( [0034] the bit line switch transistors may be formed in a first triple well including a first well, a second well, and a substrate), and a plurality of third well regions disposed along a first lateral direction ( as shown in Fig. 3 ) within a substrate ( [0034] the memory array may be formed in a second triple well including a third well, a fourth well and the substrate), wherein the second well region (Fig. 3 n-well region #434) is interposed between the first region (Fig. 3 p-type substrate region #436 ) and the plurality of third well regions (Fig. 3 p-well region #432) along the first lateral direction ( as shown in Fig. 3 ), and wherein the plurality of third well regions are separated from one another along a second lateral direction perpendicular to the first direction ( [0043] WL0, WL1, …, WL7 can extend via the control gates of storage elements 408, 410, …, 422); a plurality of floating gates ( [0036] Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate) disposed over the first to third well regions ( [0038] The word lines comprise the rows of the array or set. Each word line connects the control gates of each storage element in the row)
Toyama does not appear to disclose in an axial direction perpendicular to the first lateral direction and the second lateral direction; each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first lateral direction; a bit line write region disposed within the second well region, wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates; and a bit line read region disposed within the second well region and spaced from the bit line write region along the first lateral direction, wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates.
Lin discloses in an axial direction perpendicular to the first lateral direction and the second lateral direction ( [0063] The active regions (62,66) may include axial active regions 62 that are laterally offset from a most proximal one of the floating gate electrodes 22 along the axial direction )
Lin does not appear to disclose each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first lateral direction; a bit line write region disposed within the second well region, wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates; and a bit line read region disposed within the second well region and spaced from the bit line write region along the first lateral direction, wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates
However, Chen teaches each of the plurality of floating gates ( Fig. 5 FG1 and FG2) continuously extends from the first well region ( Fig. 5 #104 ) to a corresponding one of the third well regions ( Fig. 5 #108) along the first direction ( as shown in Fig. 5 ); a bit line write region ( [0030] the first BL1 and/or the bit line write region (e.g. 112 of Fig. 1A) may be utilized during a write operation. During the write operation, an unselect bias voltage may be applied to the second bit line BL2, such that the bit line read region (e.g. 114 of Fig. 1A) is unselected ) disposed within the second well region ( Fig. 1A #112 ); and a bit line read region ( [0030] the first BL1 and/or the bit line write region (e.g. 112 of Fig. 1A) may be utilized during a write operation. During the write operation, an unselect bias voltage may be applied to the second bit line BL2, such that the bit line read region (e.g. 114 of Fig. 1A) is unselected) disposed within the second well region ( F9g. 1A #114 ) and spaced from the bit line write region along the first direction ( Fig. 2 BL1 and BL2) , wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates ( Fig. 1A #114).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first lateral direction; a bit line write region disposed within the second well region, wherein the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates; and a bit line read region disposed within the second well region and spaced from the bit line write region along the first lateral direction, wherein the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates because the continuous extension of each floating gate from the first well region to a corresponding one of a third well region is a specific design feature typically found in NAND flash memory devices, and placing a bit line within a specific well could help isolate it reducing potential interference and improving the operation reliability.
Claim 32: Toyama, Lin, and Chen disclose the memory device of claim 31 ( as discussed above).
Neither Toyama nor Lin appear to disclose the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates.
However, Chen teaches the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates ( Fig. 1A #112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the bit line write region comprises first source/drain regions disposed on opposite sides of each of the plurality of floating gates because this creates a channel through which electrons flow during programming, erasing, and reading operations.
Claim 33: Toyama, Lin, and Chen disclose the memory device of claim 31 ( as discussed above).
Neither Toyama nor Lin appear to disclose the bit line read region comprises second source/drain regions disposed on opposite sides of each of the plurality of floating gates.
However, Chen teaches the bit line read region comprises second source/drain regions disposed on the opposite sides of each of the plurality of floating gates ( Fig. 1A #114).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement the bit line read region comprises second source/drain regions disposed on opposite sides of each of the plurality of floating gates because this would enable the reading of individual memory cells.
Claim 34: Toyama, Lin, and Chen disclose the memory device of claim 31 ( as discussed above).
Neither Toyama nor Lin appear to disclose an isolation structure disposed within a front-side surface of the substrate, wherein the isolation structure laterally surrounds the first well region, the second well region, and the third well regions.
However, Chen teaches an isolation structure (Fig. 1A isolation structure #103) disposed within a front-side surface of the substrate ( [0017] An isolation structure #103 extends from the front-side #102f of the substrate #102 to a point below the front-side #102f ), wherein the isolation structure laterally surrounds the first well region (Fig. 1A #103 surrounds #104), the second well region (Fig. 1A #103 surrounds #106), and the third well regions (Fig. 1A #103 surrounds #108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement an isolation structure disposed within a front-side surface of the substrate, wherein the isolation structure laterally surrounds the first well region, the second well region, and the third well regions because isolation structures are used to prevent latch-up and reduce electrical interference.
Claim 35: Toyama, Lin, and Chen disclose the memory device of claim 31 (as discussed above).
Neither Toyama nor Lin appear to disclose a plurality of dielectric structures disposed between the substrate and a corresponding one of the plurality of floating gates.
However, Chen teaches a plurality of dielectric structures (Fig. 1A dielectric structure #134) disposed between the substrate (Fig. 1A #102) and a corresponding one of the plurality of floating gates (Fig. 1A: FG).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and <to implement a plurality of dielectric structures disposed between the substrate and a corresponding one of the plurality of floating gates because this approach enables charge storage and prevent the stored charge from leaking away.
Claim 36: Toyama discloses, a memory device ( [0034] a non-volatile memory ), comprising: a first well region ( [0034] the bit line switch transistors may be formed in a first triple well including a first well, a second well, and a substrate), a second well region ( [0034] the bit line switch transistors may be formed in a first triple well including a first well, a second well, and a substrate), and a plurality of third well regions disposed within a substrate ( [0034] the memory array may be formed in a second triple well including a third well, a fourth well and the substrate), wherein the second well region (Fig. 3 n-well region #434) is interposed between the first region (Fig. 3 p-type substrate region #436 ) and the plurality of third well regions (Fig. 3 p-well region #432) along a first lateral direction ( Fig. 3 control gates of storage elements 408, 410, …, 422), and wherein the plurality of third well regions are separated from one another along a second lateral direction perpendicular to the first lateral direction ( [0043] WL0, WL1, …, WL7 can extend via the control gates of storage elements 408, 410, …, 422); a plurality of floating gates ( [0036] Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate) disposed over the first to third well regions ( [0038] The word lines comprise the rows of the array or set. Each word line connects the control gates of each storage element in the row).
Toyama does not appear to disclose in an axial direction perpendicular to the first lateral direction and the second lateral direction; each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first direction; and a plurality of source/drain regions disposed on opposite sides of each of the plurality of floating gates.
Lin discloses in an axial direction perpendicular to the first lateral direction and the second lateral direction
Lin does not appear to disclose each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first direction; and a plurality of source/drain regions disposed on opposite sides of each of the plurality of floating gates.
However, Chen teaches each of the plurality of floating gates ( Fig. 5 FG1 and FG2) continuously extends from the first well region ( Fig. 5 #104 ) to a corresponding one of the third well regions ( Fig. 5 #108) along the first direction ( as shown in Fig. 5 ); and a plurality of source/drain regions disposed on opposite sides of each of the plurality of floating gates ( Fig. 1A #112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement each of the plurality of floating gates continuously extends from the first well region to a corresponding one of the third well regions along the first direction; and a plurality of source/drain regions disposed on opposite sides of each of the plurality of floating gates because this configuration is characteristic of a specific non-volatile memory architecture, likely a type of split-gate flash memory.
Claim 37: Toyama, Lin, and Chen disclose the memory device of claim 36 ( as discussed above).
Toyama teaches the plurality of source/drain regions form a first bit line region ( Fig. 2 bit line 321 ) and a second bit line region ( Fig. 2 bit line 341 ).
Claim 38: Toyama, Lin, and Chen disclose the memory device of claim 37 ( as discussed above ).
Toyama teaches the first bit line region is a bit line write region ( Fig. 10a; [0065] two adjacent bit line switch transistors 502a and 502b during an example of a program operation ) and the second bit line region is a bit line read region ( Fig. 10b; [0067] the gates of the BL switch transistors are biased to the select voltage Vselect. The SB terminal of each BL switch transistor is biased to a pre-charge voltage Vpc to enable sensing for reading a corresponding memory cell ).
Claim 39: Toyama, Lin, and Chen disclose the memory device of claim 38 ( as discussed above).
Neither Toyama nor Lin appear to disclose a single select gate continuously extending across the bit line write region and the bit line read region.
However, Chen teaches a single select gate (Fig. 1A: (SG) 116) continuously extending across the bit line write region (Fig. 1A: BL1) and the bit line read region (Fig. 1A: BL2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement a single select gate continuously extending across the bit line write region and the bit line read region because in NAND flash a continuous select gate serves as a crucial control element for accessing and isolating individual NAND strings.
Claim 40: Toyama, Lin, and Chen disclose the memory device of claim 36 (as discussed above).
Toyama discloses each of the plurality of floating gates ( [0036] Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate)
Neither Toyama nor Lin appear to disclose corresponding first pair of the plurality of source/drain regions operatively function as a first storage transistor of a corresponding one of a plurality of memory cells, and each of the plurality of floating gates and a corresponding second pair of the plurality of source/drain regions operatively function as a second storage transistor of the corresponding memory cell.
However, Chen teaches corresponding first pair of the plurality of source/drain regions operatively function as a first storage transistor ( [0015] The first storage and selector transistors include a bit line write active region) of a corresponding one of a plurality of memory cells ( [0029] The memory array is electrically coupled to support circuitry that is configured to perform a write operation and/or a read operation on the plurality of memory cells (MCs)), and each of the plurality of floating gates and a corresponding second pair of the plurality of source/drain regions operatively function as a second storage transistor ( [0015] the second storage and selector transistors include a bit line and read active region) of the corresponding memory cell (Fig. 2 circuit #200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Toyama and Lin to implement corresponding first pair of the plurality of source/drain regions operatively function as a first storage transistor of a corresponding one of a plurality of memory cells, and each of the plurality of floating gates and a corresponding second pair of the plurality of source/drain regions operatively function as a second storage transistor of the corresponding memory cell because the ability of the floating gate to retain charge non-volatilely is key to its function as a storage transistor.
Response to Amendment/Arguments
Applicant’s arguments, see page 7 of the remarks, filed 03/05/26, with respect to Drawings have been fully considered and are persuasive. The objection of 12/08/25 has been withdrawn.
Applicant’s arguments, see pages 7-8 of the remarks, filed 03/05/26, with respect to 35 U.S.C. 112 have been fully considered and are persuasive. The rejection of 12/08/25 has been withdrawn.
Applicant’s arguments, see pages 8-10 of the remarks, filed 03/05/26, with respect to the rejection of claims 1, 31, and 36 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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