Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restriction - Response to Amendment
1. Applicant’s election without traverse of Group I, claims 1-14. Applicant's amendment dated 10/16/2025 in which claims 15-20 were canceled has been entered of record. Because applicant's amendment has canceled claims drawn to a distinct invention, the restriction requirement (dated 08/28/2025) is now moot. New claims 21-26 were added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-11, 13-14 and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Hashemi et al. (US 2019/0326288; hereinafter Hashemi) in view of Ostermayr et al. (US 2023/0163170; hereinafter Ostermayr).
Regarding claim 1, Hashemi, in fig. 10, discloses a memory device, comprising: a semiconductor substrate 10; a stack of channel layers 14P’over the semiconductor substrate 10; a word line structure 34R interleaved with the stack of channel layers 14P’; and a source feature 26/28 and a drain feature 26/28 on both sides of the stack of channel layers 14P’.
Hashemi discloses a memory device as above but fails to discloses each channel layer including a conductive oxide material.
However, Ostermayr discloses channel layer 104 including a conductive oxide material (fig. 1 & [0032]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a conductive oxide channel as taught by Ostermayr. A conductive oxide material has the advantage of a high mobility for greater switching performance and without concern for electron or hole tunneling.
Regarding claim 2, Ostermayr discloses wherein each channel layer is an N-type channel layer, and wherein the conductive oxide material includes indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), tin oxide (SnO2), or combinations thereof ([0030] & [0032]).
Regarding claim 3, Ostermayr discloses wherein each channel layer is a P-type channel layer, and wherein the conductive oxide material includes nickel oxide (NiO), copper oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper indium oxide (CuInO2), strontium copper oxide (SrCu2O2), tin oxide (SnO), or combinations thereof ([0030] & [0032]).
Regarding claim 4, Ostermayr discloses wherein the conductive oxide material is a first conductive oxide material, and wherein the source feature 114 and the drain feature 114 each include a metal layer over a contact layer, the contact layer including a second conductive oxide material ([0037] & [0038]).
Regarding claim 5, Ostermayr discloses wherein the first conductive oxide material is the same as the second conductive oxide material ([0037] & [0038]).
Regarding claim 6, Ostermayr discloses wherein the first conductive oxide material includes a first oxygen concentration and the second conductive oxide material includes a second oxygen concentration, and wherein the second oxygen concentration is less than the first oxygen concentration ([0037] & [0038]).
Regarding claim 7, Ostermayr discloses further comprising a dielectric layer 112 disposed along a sidewall of each of the source feature 114-1 and the drain feature 114-2 (fig. 1).
Regarding claim 8, Hashemi, in fig. 10, discloses a memory device, comprising: a semiconductor substrate 10; and a memory cell over the semiconductor substrate, including: a stack of channel layers 14P’over the semiconductor substrate 10; a word line structure 34R wrapping around each channel layer 14P’; and a source metal electrode 36A/26/28 and a drain metal electrode 36B/26/28 on both sides of the stack of channel layers 14P’.
Hashemi discloses a memory device as above but fails to discloses each channel layer including a conductive oxide material.
However, Ostermayr discloses channel layer 104 including a conductive oxide material (fig. 1 & [0032]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a conductive oxide channel as taught by Ostermayr. A conductive oxide material has the advantage of a high mobility for greater switching performance and without concern for electron or hole tunneling.
Regarding claim 9, Hashemi discloses wherein the memory cell is a first memory cell, the memory device further comprising a second memory cell adjacent the first memory cell, and wherein the first memory cell and the second memory cell are separated by a dielectric layer ([0068]).
Regarding claim 10, Hashemi discloses wherein the memory cell is a first memory cell, the memory device further comprising a second memory cell adjacent the first memory cell, and wherein the drain metal electrode of the first memory cell is a common drain electrode shared between the first memory cell and the second memory cell (fig. 10).
Regarding claim 11, Hashemi discloses wherein the memory cell is a first memory cell and the word line structure is a first word line structure, and wherein the memory cell further includes a second word line structure disposed at a cell boundary (fig. 10).
Regarding claim 12, Hashemi discloses further comprising a bit line structure electrically connected to the drain metal electrode through a first via and a storage capacitor electrically connected to the source metal electrode through a second via ([0069]).
Regarding claim 13, Ostermayr discloses wherein the metal oxide is a first metal oxide, and wherein the source metal electrode and the drain metal electrode each include a contact layer having a second metal oxide ([0037] & [0038]).
Regarding claim 14, Ostermayr discloses wherein the metal oxide is a first metal oxide (oxide semiconductor, [0032]), and Hashemi discloses wherein the word line structure 34R includes a conductive electrode (fig. 10 & [0064]) over a dielectric layer 32R having a second metal oxide (high-k dielectric, [0062]), the first metal oxide and the second metal oxide having different compositions.
Regarding claim 21, Hashemi, in fig. 10, discloses a memory device, comprising: a semiconductor substrate 10; and a memory cell over the semiconductor substrate, including: a stack of channel layers 14P’over the semiconductor substrate 10; a word line structure 34R wrapping around each channel layer 14P’ or interleaved with the stack of channel layers 14P’; and a source feature 26/28 and a drain feature 26/28 on both sides of the stack of channel layers 14P’.
Hashemi discloses a memory device as above but fails to discloses each channel layer including a conductive oxide material.
However, Ostermayr discloses channel layer 104 including a N- or P-type conductive oxide material, the oxide include zinc, indium, gallium, tin, antimony, titanium, ruthenium, tungsten, indium gallium zinc oxide (IGZO), cobalt, copper, nickel, niobium, molybdenite. The channel layer 104 may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium (fig. 1 & [0032]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a conductive oxide channel as taught by Ostermayr. A conductive oxide material has the advantage of a high mobility for greater switching performance and without concern for electron or hole tunneling.
Regarding claim 22, Ostermayr discloses wherein at least one of the channel layers is an N-type channel layer, and the oxide included therein is based on zinc (Zn), indium (In), gallium (Ga), tin (Sn), or combinations thereof ([0032]).
Regarding claim 23, Ostermayr discloses wherein at least one of the channel layers is a P- type channel layer, and the oxide included therein is based on nickel (Ni), copper (Cu), aluminum (Al), gallium (Ga), indium (In), strontium (Sr), tin (Sn), or combinations thereof ([0032]).
Regarding claim 24, Hashemi discloses further comprising a dielectric layer that separates the memory cell from another memory cell ([0068]).
Regarding claim 25, Ostermayr discloses wherein the oxide is a first oxide, and wherein each of the source feature and the drain feature includes a contact layer having a second oxide ([0037] & [0038]).
Regarding claim 26, Ostermayr discloses wherein the metal oxide is a first metal oxide (oxide semiconductor, [0032]), and Hashemi discloses wherein the word line structure 34R includes a conductive electrode (fig. 10 & [0064]) over a dielectric layer 32R having a second metal oxide (high-k dielectric, [0062]), the first metal oxide and the second metal oxide having different compositions.
3. Claims 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hashemi (US 2019/0326288) in view of Sato et al. (US 2022/0199628; hereinafter Sato).
Regarding claim 8, Hashemi, in fig. 10, discloses a memory device, comprising: a semiconductor substrate 10; and a memory cell over the semiconductor substrate, including: a stack of channel layers 14P’over the semiconductor substrate 10; a word line structure 34R wrapping around each channel layer 14P’; and a source metal electrode 36A/26/28 and a drain metal electrode 36B/26/28 on both sides of the stack of channel layers 14P’.
Hashemi discloses a memory device as above but fails to discloses each channel layer including a conductive oxide material.
However, Sato discloses channel layer including a conductive oxide material ([0018]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a conductive oxide channel as taught by Sato. A conductive oxide material has the advantage of a high mobility for greater switching performance and without concern for electron or hole tunneling.
Regarding claim 9, Hashemi discloses wherein the memory cell is a first memory cell, the memory device further comprising a second memory cell adjacent the first memory cell, and wherein the first memory cell and the second memory cell are separated by a dielectric layer ([0068]).
Regarding claim 10, Sato discloses wherein the memory cell is a first memory cell, the memory device further comprising a second memory cell adjacent the first memory cell, and wherein the drain metal electrode of the first memory cell is a common drain electrode shared between the first memory cell and the second memory cell (figs. 1-3).
Regarding claim 11, Sato discloses wherein the memory cell is a first memory cell and the word line structure is a first word line structure, and wherein the memory cell further includes a second word line structure disposed at a cell boundary (figs. 1-3).
Regarding claim 12, Sato discloses further comprising a bit line structure electrically connected to the drain metal electrode through a first via and a storage capacitor electrically connected to the source metal electrode through a second via (figs. 1-3).
Regarding claim 14, Sato discloses wherein the metal oxide is a first metal oxide (oxide semiconductor, [0018]), and wherein the word line structure WL includes a conductive electrode over a dielectric layer 145 having a second metal oxide (high-k dielectric, [0033]), the first metal oxide and the second metal oxide having different compositions (fig.1).
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818