Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17, 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12-15, 17 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yu et al. (U.S. Patent Publication No. 2017/0148765).
Referring to figures 1-36, Yu et al. teaches a semiconductor device, comprising:
a first semiconductor chip (100) having a first surface and a second surface opposite to each other;
a second semiconductor chip (130) disposed above the first semiconductor chip (100) and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip (see figures 12-22); and
the first semiconductor chip (100) has a first sidewall extending from the second surface to the first surface, a first angle between the first surface and the first sidewall and a second angle between the second surface and the first sidewall being less than 90 degrees, the second angle being different from the first angle (see figures 12-22), and
wherein the second semiconductor chip (130) has a second sidewall extending from the fourth surface to the third surface, a third angle between the third surface and the second sidewall being less than 90 degrees (see figures 12-22).
Regarding to claim 13, a dielectric filling material (160/300) with a plurality of portions, each of which extends along the first sidewall or the second sidewall (see figure 21).
Regarding to claim 14, the first semiconductor chip (100) has a first semiconductor substrate along the second surface, and the second semiconductor chip (130) has a second semiconductor substrate along the fourth surface (see figure 21).
Regarding to claim 15, one or more hybrid bonding layers (106/108) interposed between the second surface and the third surface (see paragraph# 29, figure 6).
Regarding to claim 17, a plurality of connector structures (108) formed along the first surface of the first semiconductor chip (100, see figure 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 16 is/are rejected under 35 U.S.C. 103 as being unpatentable Yu et al. (U.S. Patent Publication No. 2017/0148765) applied in claim(s) 12-15, 17 above in view of CHANG et al. (U.S. Patent Publication No. 2024/0387484 (provision application date).
Referring to figures 1-36, Yu et al. teaches a semiconductor device, comprising:
a first semiconductor chip (100) having a first surface and a second surface opposite to each other;
a second semiconductor chip (130) disposed above the first semiconductor chip (100) and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip (see figures 12-22); and
the first semiconductor chip (100) has a first sidewall extending from the second surface to the first surface, a first angle between the first surface and the first sidewall and a second angle between the second surface and the first sidewall being less than 90 degrees, the second angle being different from the first angle (see figures 12-22), and
wherein the second semiconductor chip (130) has a second sidewall extending from the fourth surface to the third surface, a third angle between the third surface and the second sidewall being less than 90 degrees (see figures 12-22).
However, the reference does not clearly teach the first semiconductor chip has a first metal seal ring around a perimeter of the first semiconductor chip, and the second semiconductor chip has a second metal seal ring around a perimeter of the second semiconductor chip (in claim 16).
CHANG teaches a semiconductor package having a the first semiconductor chip (100) has a first metal seal ring (130) around a perimeter of the first semiconductor chip, and the second semiconductor chip (200) has a second metal seal ring (23) around a perimeter of the second semiconductor chip (see figure 2a, meeting claim 16), and the first semiconductor chip has a first semiconductor substrate(102) along the second surface, and the second semiconductor chip has a second semiconductor substrate (202) along the fourth surface (see figures 2-8)
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would to forming metal seal ring and carrier wafer in as taught by CHANG in Kriman et al. because sealing ring would protect multiple semiconductors dies and forming the carrier/substrate to provide the support for the device.
Allowable Subject Matter
Claims 1-11, 21-23 are allowed. None of the prior art teaches or suggests that each of the first and second portions of the dielectric filling material has a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip, and
wherein a first angle between the first surface and the first sidewall is less than 90 degrees, in claim 11; a first portion disposed along a substrate portion of the first semiconductor chip, the first portion having a first taper angle; and a second portion disposed along an oxide portion formed over an active surface of the substrate portion, the second portion having a second taper angle different from the first taper angle, the first taper angle and the second taper angle being less than 90 degrees, in claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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