Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-17 in the reply filed on 10/29/25 is acknowledged. Claims 18-20 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Oath/Declaration
Oath/Declaration filed on 2/21/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by HAYAKAWA et al. (U.S. Patent Publication No. 2022/0315413).
Referring to figures 13-19, HAYAKAWA et al. teaches a semiconductor device, comprising:
a first semiconductor chip (30) having a first surface and a second surface opposite to each other;
a second semiconductor chip (20) disposed above the first semiconductor chip and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip; and
a dielectric filling material (40) having a plurality of portions, at least a first one of the plurality of portions being in contact with a first sidewall of the first semiconductor chip and at least a second one of the plurality of portions being in contact with a second sidewall of the second semiconductor chip;
wherein each of the first and second portions of the dielectric filling material has a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip (see figure 13b).
Regarding to claim 2, the first semiconductor chip (30) and the second semiconductor chip (20) are bonded to each other through one or more hybrid bonding layers (see figure 13a).
Regarding to claim 3, a plurality of connector structures (35/36/43/44) formed along the first surface of the first semiconductor chip (see figure 12).
Claim(s) 12-13, 15, 17, 21 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kriman et al. (U.S. Patent Publication No. 2010/0230795).
Referring to figures 7, 16, Kriman et al. teaches a semiconductor device, comprising:
a first semiconductor chip (101) having a first surface and a second surface opposite to each other;
a second semiconductor chip (102) disposed above the first semiconductor chip and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip; and
the first semiconductor chip (101) has a first sidewall extending from the second surface to the first surface, a first angle between the first surface and the first sidewall being less than 90 degrees, and wherein the second semiconductor chip (102)has a second sidewall extending from the fourth surface to the third surface, a second angle between the third surface and the second sidewall being less than 90 degrees (see figures 7, 16).
Regarding to claim 13, a dielectric filling material (623) with a plurality of portions, each of which extends along the first sidewall or the second sidewall (see figure 13).
Regarding to claim 15, one or more hybrid bonding layers (602) interposed between the second surface and the third surface (see figure 13a).
Regarding to claim 17, a plurality of connector structures (604) formed along the first surface of the first semiconductor chip (see figure 7, 16).
Regarding to claim 21, a semiconductor device, comprising:
a dielectric structure (623/602) laterally separating a first semiconductor chip (101) from a second semiconductor chip (101), the dielectric structure having opposing first and second tapered sidewalls, wherein the first tapered sidewall comprises:
a first portion, disposed along a substrate portion of the first semiconductor chip (101) having a first taper angle; and
a second portion, disposed along an oxide portions formed over an active surface of the substrate portion, having a second taper angle, different from the first taper angle (see paragraph# 108).
Claim(s) 21-22 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by HUANG et al. (U.S. Patent Publication No. 2023/0170258).
HUANG et al. teaches a semiconductor device, comprising:
a dielectric structure (125) laterally separating a first semiconductor chip (111) from a second semiconductor chip (111), the dielectric structure having opposing first and second tapered sidewalls, wherein the first tapered sidewall comprises:
a first portion, disposed along a substrate portion of the first semiconductor chip (111) having a first taper angle; and
a second portion, disposed along an oxide portions (135) formed over an active surface of the substrate portion, having a second taper angle, different from the first taper angle (see figures 1F, 14 paragraphs# 20+).
Regarding to claim 22, the second semiconductor chip (111) comprises a second substrate portion (104) and a second oxide portion symmetrical (135) to the substrate portion and oxide portion of the first semiconductor chip across a centerline of the dielectric structure; and the second tapered sidewall is conformal to the second substrate portion and the second oxide portion, and symmetric to the first tapered sidewall across the centerline of the dielectric structure (see figures 1F, 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5-7, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable HAYAKAWA et al. (U.S. Patent Publication No. 2022/0315413) applied in claim(s) 1-3 above in view of CHANG et al. (U.S. Patent Publication No. 2024/0387484 (provision application date).
Referring to figures 13-19, HAYAKAWA et al. teaches a semiconductor device, comprising:
a first semiconductor chip (30) having a first surface and a second surface opposite to each other;
a second semiconductor chip (20) disposed above the first semiconductor chip and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip; and
a dielectric filling material (40) having a plurality of portions, at least a first one of the plurality of portions being in contact with a first sidewall of the first semiconductor chip and at least a second one of the plurality of portions being in contact with a second sidewall of the second semiconductor chip;
wherein each of the first and second portions of the dielectric filling material has a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip (see figure 13b).
However, the reference does not clearly teach the first semiconductor chip has a first metal seal ring around a perimeter of the first semiconductor chip, and the second semiconductor chip has a second metal seal ring around a perimeter of the second semiconductor chip (in claim 4), the first metal seal ring surrounds the second metal seal ring (in claim 5), the first metal seal ring and the second metal seal ring have their respective portions aligned with each other (in claim 6), the second metal seal ring has a portion inside the first metal seal ring, and a remaining portion outside the first metal seal ring (in claim 7), a carry wafer bonded to the fourth surface of the second semiconductor chip ( in claim 10), and the first semiconductor chip has a first semiconductor substrate along the second surface, and the second semiconductor chip has a second semiconductor substrate along the fourth surface (in claim 11).
CHANG teaches a semiconductor package having a the first semiconductor chip (100) has a first metal seal ring (130) around a perimeter of the first semiconductor chip, and the second semiconductor chip (200) has a second metal seal ring (23) around a perimeter of the second semiconductor chip (see figure 2a, meeting claim 4), the first metal seal ring (130) surrounds the second metal seal ring (230, see figures 2a-8, meeting claim 5), the first metal seal ring and the second metal seal ring have their respective portions aligned with each other (see figures 2a-8 meeting claim 6), the second metal seal ring has a portion inside the first metal seal ring, and a remaining portion outside the first metal seal ring (see figures 2-8, meeting claim 7), a carry wafer (320) bonded to the fourth surface of the second semiconductor chip (see figures 2-8, meeting claim 10), and the first semiconductor chip has a first semiconductor substrate(102) along the second surface, and the second semiconductor chip has a second semiconductor substrate (202) along the fourth surface (see figures 2-8, meeting, claim 11).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would to forming metal seal ring and carrier wafer in as taught by CHANG in HAYAKAWA et al. because sealing ring would protect multiple semiconductors dies and forming the carrier/substrate to provide the support for the device.
Claim 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable HAYAKAWA et al. (U.S. Patent Publication No. 2022/0315413) applied in claim(s) 1-3 above in view of Kim et al. (U.S. Patent Publication No. 2021/0159213).
Referring to figures 13-19, HAYAKAWA et al. teaches a semiconductor device, comprising:
a first semiconductor chip (30) having a first surface and a second surface opposite to each other;
a second semiconductor chip (20) disposed above the first semiconductor chip and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip; and
a dielectric filling material (40) having a plurality of portions, at least a first one of the plurality of portions being in contact with a first sidewall of the first semiconductor chip and at least a second one of the plurality of portions being in contact with a second sidewall of the second semiconductor chip;
wherein each of the first and second portions of the dielectric filling material has a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip (see figure 13b).
However, the reference does not teach a dummy chip that essentially consists of silicon; wherein the dummy chip is also disposed above the first semiconductor chip and having a fifth surface and a sixth surface opposite to each other, and wherein the fifth surface of the dummy chip faces the second surface of the first semiconductor chip (in claim 8) and wherein at least a third one of the plurality of portions being in contact with both the second sidewall of the second semiconductor chip and a third sidewall of the dummy chip; wherein the third portion of the dielectric filling material has a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip (in claim 9).
Kim et al. teaches a semiconductor package having a dummy chip (230D/240D1) that essentially consists of silicon; wherein the dummy chip is also disposed above the first semiconductor chip (311) and having a fifth surface and a sixth surface opposite to each other, and wherein the fifth surface of the dummy chip (230D/240D) faces the second surface of the first semiconductor chip (311, meeting claim 8), wherein at least a third one of the plurality of portions being in contact with both the second sidewall of the second semiconductor chip (211) and a third sidewall of the dummy chip (230D/240D); wherein the third portion of the dielectric filling material (500) has a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip (311, see figures 5b, 9b, 14b, flip the drawing upside down, meeting claim 9).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form dummy chip in HAYAKAWA et al. as taught by Kim et al. because it is known in the art to fill height or act as spacer to protect active dies and wire bonds.
Claim 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable Kriman et al. (U.S. Patent Publication No. 2010/0230795) applied in claim(s) 12-13, 15, 17, 21 above in view
of CHANG et al. (U.S. Patent Publication No. 2024/0387484 (provision application date).
Referring to figures 7, 16, Kriman et al. teaches a semiconductor device, comprising:
a first semiconductor chip (101) having a first surface and a second surface opposite to each other;
a second semiconductor chip (102) disposed above the first semiconductor chip and having a third surface and a fourth surface opposite to each other, wherein the third surface of the second semiconductor chip faces the second surface of the first semiconductor chip; and
the first semiconductor chip (101) has a first sidewall extending from the second surface to the first surface, a first angle between the first surface and the first sidewall being less than 90 degrees, and wherein the second semiconductor chip (102) has a second sidewall extending from the fourth surface to the third surface, a second angle between the third surface and the second sidewall being less than 90 degrees (see figures 7, 16).
However, the reference does not clearly teach the first semiconductor chip has a first semiconductor substrate along the second surface, and the second semiconductor chip has a second semiconductor substrate along the fourth surface (in claim 14), the first semiconductor chip has a first metal seal ring around a perimeter of the first semiconductor chip, and the second semiconductor chip has a second metal seal ring around a perimeter of the second semiconductor chip (in claim 16).
CHANG teaches a semiconductor package having a the first semiconductor chip (100) has a first metal seal ring (130) around a perimeter of the first semiconductor chip, and the second semiconductor chip (200) has a second metal seal ring (23) around a perimeter of the second semiconductor chip (see figure 2a, meeting claim 16), and the first semiconductor chip has a first semiconductor substrate(102) along the second surface, and the second semiconductor chip has a second semiconductor substrate (202) along the fourth surface (see figures 2-8, meeting, claim 14).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would to forming metal seal ring and carrier wafer in as taught by CHANG in Kriman et al. because sealing ring would protect multiple semiconductors dies and forming the carrier/substrate to provide the support for the device.
Claims 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable Kriman et al. (U.S. Patent Publication No. 2010/0230795)/ HUANG et al. (U.S. Patent Publication No. 2023/0170258) applied in claim(s) 21-22 above in view of Kim et al. (U.S. Patent Publication No. 2021/0159213).
Kriman et al./ HUANG et al. teaches, a semiconductor device, comprising:
a dielectric structure (623/602) laterally separating a first semiconductor chip (101) from a second semiconductor chip (101), the dielectric structure having opposing first and second tapered sidewalls, wherein the first tapered sidewall comprises:
a first portion, disposed along a substrate portion of the first semiconductor chip (101) having a first taper angle; and
a second portion, disposed along an oxide portions formed over an active surface of the substrate portion, having a second taper angle, different from the first taper angle (see paragraph# 108).
However, the reference does not teach the second semiconductor chip is a dummy chip having a uniform taper angle along the second tapered sidewall of the dielectric structure (in claim 23).
Kim et al. teaches a semiconductor package having a dummy chip (230D/240D1, see figures 5b, 9b, 14b, meeting claim 22).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form dummy chip in Kriman et al./ HUANG et al. as taught by KIM et al. because it is known in the art to fill height or act as spacer to protect active dies and wire bonds.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893