DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of Invention I (claims 2-11, 17 and 19-27) in the reply filed on 08/15/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2, 5-7, 25-26 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Quinones et al (US 2005/0082670).
Regarding claim 2, Quinones (Figs. 3A-3B and 4) discloses a method connecting a substrate or integrated circuit (IC) chip 10 ([0020]) and a second substrate or IC chip 26 ([0032]), the method comprising: disposing electrically conductive balls 14 ([0020]) on electrical bonding pads 16 ([0020]) of a surface of the substrate or IC chip 10 to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, wherein the disposing includes: bonding the electrically conductive balls 14 to the electrical bonding pads 16 of the surface of the substrate or IC chip 10 (Fig. 3A); and disposing the underfill material 22/24 ([0030]) on the surface of the substrate or IC chip around bonds between the electrically conductive balls 14 and the electrical bonding pads 16 (Fig. 3B); and electrically and mechanically connecting the surface of the substrate or IC chip 10 to the second substrate or IC chip 26 using the BGA 14 disposed on the surface of the substrate or IC chip 10 (Fig. 4).
Regarding claim 5, Quinones (Figs. 3A-3B and 4) further discloses the underfill material 22/24 disposed around the bonds between the electrically conductive balls 14 and the electrical bonding pads 16. It is noted that because the protruding portion 22 of the underfill material 22/24 partially disposed around and encircling the conductive balls 14, the protruding portion 22 of the underfill material would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claims 6-7, Quinones (Figs. 3A-3B and 4) further discloses: the annuluses 22 of the underfill material do not completely cover the respective electrically conductive balls 14; and the annuluses 22 of the underfill material have heights in a range of 20% and 90% of a diameter ( or a height of ball) of the electrically conductive balls 14 ([0029]).
Regarding claim 25, Quinones (Figs. 3A-3B and 4) discloses a method of connecting a substrate or integrated circuit (IC) chip 10 ([0020]) and a second substrate or IC chip 26 ([0032]), the method comprising: bonding electrically conductive balls 14 to electrical bonding pads 16 of a surface of the substrate or IC chip 10 (Fig. 3A); disposing an underfill material 22/24 ([0030]) on the surface of the substrate or IC chip 10 around bonds between the electrically conductive balls 14 and the electrical bonding pads 16 (Fig. 3A); and after disposing the underfill material 22/24, electrically and mechanically connecting the surface of the substrate or IC chip 10 to the second substrate or IC chip 26 using the electrically conductive balls 14 bonded to the surface of the substrate or IC chip 10 (Fig. 4).
Regarding claim 26, Quinones (Figs. 3A-3B and 4) further discloses the underfill material 22/24 disposed around the bonds between the electrically conductive balls 14 and the electrical bonding pads 16. It is noted that because the protruding portion 22 of the underfill material 22/24 partially disposed around and encircling the conductive balls 14, the protruding portion 22 of the underfill material would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claim 27, Quinones (Figs. 3A-3B and 4) further discloses the annuluses 22 of the underfill material do not completely cover the respective electrically conductive balls 14, and the electrical and mechanical connecting of the surface of the substrate or IC chip 10 to the second substrate or IC chip 26 using the electrically conductive balls 14 bonded to the surface of the substrate or IC chip comprises bonding uncovered portions 30 of the electrically conductive balls 14 to the second substrate or IC chip 26.
Claims 2, 5-6, 25-26 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akram et al (US 5,956,605).
Regarding claim 2, Akram (Figs. 1-4) discloses a method connecting a substrate or integrated circuit (IC) chip 12 (column 6, lines 19-20) and a second substrate or IC chip 42 (column 7, line 5), the method comprising: disposing electrically conductive balls 16 (column 6, lines 28-30) on electrical bonding pads 14 (column 6, lines 21-22) of a surface of the substrate or IC chip 12 to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip 12, wherein the disposing includes: bonding the electrically conductive balls 16 to the electrical bonding pads 14 of the surface of the substrate or IC chip 12 (Fig. 1); and disposing the underfill material 22 on the surface of the substrate or IC chip 12 around bonds between the electrically conductive balls 16 and the electrical bonding pads 14 (Fig. 2); and electrically and mechanically connecting the surface of the substrate or IC chip 12 to the second substrate or IC chip 42 (Fig. 4) using the BGA 16 disposed on the surface of the substrate or IC chip 12.
Regarding claim 5, Akram (Figs. 1-4) further discloses the underfill material 22 disposed around the bonds between the electrically conductive balls 16 and the electrical bonding pads 14. It is noted that because the protruding portion of the underfill material 22 disposed around and encircling the conductive balls 16, the protruding portion of the underfill material 22 would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claim 6, Akram (Figs. 1-4) further discloses the annuluses of the underfill material 22 do not completely cover the respective electrically conductive balls 16 (i.e., top surfaces of 16 are uncovered or exposed).
Regarding claim 25, Akram (Figs. 1-4) discloses a method of connecting a substrate or integrated circuit (IC) chip 12 (column 6, lines 19-20) and a second substrate or IC chip 42 (column 7, line 5), the method comprising: bonding electrically conductive balls 16 (column 6, lines 28-30) to electrical bonding pads 14 (column 6, lines 21-22) of a surface of the substrate or IC chip 12; disposing an underfill material 22 on the surface of the substrate or IC chip 12 (Fig. 2) around bonds between the electrically conductive balls 16 and the electrical bonding pads 14; and after disposing the underfill material, electrically and mechanically connecting the surface of the substrate or IC chip 12 to the second substrate or IC chip 42 (Fig. 4) using the electrically conductive balls 16 bonded to the surface of the substrate or IC chip 12.
Regarding claim 26, Akram (Figs. 1-4) further discloses the underfill material 22 disposed around the bonds between the electrically conductive balls 16 and the electrical bonding pads 14. It is noted that because the protruding portion of the underfill material 22 disposed around and encircling the conductive balls 16, the protruding portion of the underfill material 22 would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claim 27, Akram (Figs. 1-4) further discloses the annuluses of the underfill material 22 do not completely cover the respective electrically conductive balls 16 (i.e., top surfaces of 16 are uncovered or exposed), and the electrical and mechanical connecting of the surface of the substrate or IC chip 12 to the second substrate or IC chip 42 (Fig. 4) using the electrically conductive balls 16 bonded to the surface of the substrate or IC chip 12 comprises bonding uncovered portions of the electrically conductive balls 16 to the second substrate or IC chip 42.
Claims 9, 19-21, 23 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al (US 2016/0240509).
Regarding claim 9, Kwon (Figs. 1-5) discloses a method of connecting a substrate or integrated circuit (IC) chip 10 ([0044]) and a second substrate or IC chip 120 ([0049]), the method comprising: disposing electrically conductive balls 12/14 ([0045]) on electrical bonding pads 18 ([0045]) of a surface of the substrate or IC chip 10 to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip 10, wherein the disposing includes: disposing the electrically conductive balls 12/14 of at least two different types ([0052]) on the electrical bonding pads 18 of the surface of the substrate or IC chip 10 to form the BGA comprising the electrically conductive balls 12 and 14 of the at least two different types disposed on the surface of the substrate or IC chip 10; and electrically and mechanically connecting the surface of the substrate or IC chip 10 to the second substrate or IC chip 120 using the BGA disposed on the surface of the substrate or IC chip 10 (Fig. 5 also see Fig. 13).
Regarding claims 19-21, 23 and 24, Kwon (Figs. 1-5) further discloses: the electrically conductive balls 12/14 of at least two different types include: a first type of electrically conductive ball 14 comprising a solder ball without a core of copper or copper alloy ([0052], “solder balls”), and a second type of electrically conductive ball 12 comprising a core of copper or copper alloy 7 (i.e., layer 7 is a portion of a core) coated with a coating 9 (see Fig. 4, a core layer 7 of copper coated with layer 9, [0051]); the electrically conductive balls 14 of the first type are disposed in a peripheral region of the surface of the substrate or IC chip 10 (see Fig. 1), and the electrically conductive balls 12 of the second type are disposed in a central region of the surface of the substrate or IC chip 10 (Fig. 1) that is surrounded by the peripheral region; the coating 9 comprises a nickel or gold film (i.e., “The fusion conductive layer 9 may include… a nickel (Ni) material, a gold (Au) material”, [0050]) coating the core of copper or copper alloy 7 (i.e., “layer 7, 8 may include… a copper (Cu) material”, [0051]); the coating 9 comprises a solder material (i.e., “the fusion conductive layer 9 may include a solder material”, [0050]) coating the core of copper or copper alloy 7; and the electrically conductive balls 14 of the first type are disposed in a peripheral region of the surface of the substrate or IC chip 10 (Fig. 1), and the electrically conductive balls 12 of the second type are disposed in a central region of the surface of the substrate or IC chip that is surrounded by the peripheral region (Fig. 1).
Claims 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakaguchi et al (US 2007/0234563).
Regarding claim 9, Sakaguchi (Figs. 3-4) discloses a method of connecting a substrate or integrated circuit (IC) chip 200 ([0071]) and a second substrate or IC chip 100 ([0040]), the method comprising: disposing electrically conductive balls 204/206 on electrical bonding pads 203/205 of a surface of the substrate or IC chip 200 to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, wherein the disposing includes: disposing the electrically conductive balls 204/206 of at least two different types (i.e., different types of sizes) on the electrical bonding pads 203/205 of the surface of the substrate or IC chip to form the BGA comprising the electrically conductive balls of the at least two different types disposed on the surface of the substrate or IC chip; and electrically and mechanically connecting the surface of the substrate or IC chip 200 to the second substrate or IC chip 100 (Fig. 4) using the BGA disposed on the surface of the substrate or IC chip.
Regarding claim 11, Sakuguchi (Figs. 3-4) further discloses the electrically conductive balls 204/206 of at least two different types include the electrically conductive balls 204 of a first type (i.e., smaller balls) and electrically conductive balls 206 of a second type (i.e., larger balls) that is different from the first type, and the disposing of the electrically conductive balls of at least two different types on the electrical bonding pads 203/205 of the surface of the substrate or IC chip 200 “are formed by the method illustrated in … (Figs. 2A-2K)” ([0073]), the method includes: disposing a stencil 140 (Fig. 2D, [0055]) on the surface of the substrate or IC chip, the surface having through-holes sized 140A/140B to receive the electrically conductive balls and aligned with the electrical bonding pads of the surface of the substrate or IC chip; disposing a stencil mask 150 (Fig. 2E, [0056]) on the stencil 140; with the stencil mask 150 disposed on the stencil, disposing electrically conductive balls 109A (or 204 in Fig. 3) of the first type (i.e., smaller balls) into through-holes of the stencil 140 that are not covered by the stencil mask 150 (Fig. 2E); after the disposing of the electrically conductive balls of the first type, removing the stencil mask 150 (Fig. 2F); and after removing the stencil mask, disposing electrically conductive balls 112A (or 206 in Fig. 3) of the second type (i.e., larger balls) into the through-holes of the stencil 140 (Fig. 2H) into which electrically conductive balls of the first type have not been disposed.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2, 5-6, 25-26 and 27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Swaminathan et al (US 2024/0030086).
Regarding claim 2, Swaminathan (Fig. 2) discloses a method connecting a substrate or integrated circuit (IC) chip 212 ([0053]) and a second substrate or IC chip 202 ([0053]), the method comprising: disposing electrically conductive balls 222 ([0053]) on electrical bonding pads 211 ([0059]) of a surface of the substrate or IC chip 212 to form a ball qrid array (BGA) ([0059]) disposed on the surface of the substrate or IC chip 212, wherein the disposing includes: bonding the electrically conductive balls 222 to the electrical bonding pads 211 of the surface of the substrate or IC chip 212; and disposing the underfill material 230 ([0054]) on the surface of the substrate or IC chip 212 around bonds between the electrically conductive balls 222 and the electrical bonding pads 211; and electrically and mechanically connecting the surface of the substrate or IC chip 212 to the second substrate or IC chip 202 using the BGA 222 disposed on the surface of the substrate or IC chip 212.
Regarding claim 5, Swaminathan (Fig. 2) further discloses the underfill material 230 disposed around the bonds between the electrically conductive balls 222 and the electrical bonding pads 211. It is noted that because the underfill material 230 partially disposed around and encircling the conductive balls 222, the underfill material 230 would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claim 6, Swaminathan (Fig. 2) further discloses the annuluses of the underfill material 230 do not completely cover the respective electrically conductive balls 222.
Regarding claim 25, Swaminathan (Fig. 2) discloses a method of connecting a substrate or integrated circuit (IC) chip 212 ([0053]) and a second substrate or IC chip 202 ([0053]), the method comprising: bonding electrically conductive balls 222 ([0053]) to electrical bonding pads 211 ([0059]) of a surface of the substrate or IC chip 212; disposing an underfill material 230 ([0054]) on the surface of the substrate or IC chip 212 around bonds between the electrically conductive balls 222 and the electrical bonding pads 211; and after disposing the underfill material, electrically and mechanically connecting the surface of the substrate or IC chip 212 to the second substrate or IC chip 202 using the electrically conductive balls 222 bonded to the surface of the substrate or IC chip 212.
Regarding claim 26, Swaminathan (Fig. 2) further discloses the underfill material 230 disposed around the bonds between the electrically conductive balls 222 and the electrical bonding pads 211. It is noted that because the underfill material 230 partially disposed around and encircling the conductive balls 222, the underfill material 230 would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claim 27, Swaminathan (Fig. 2) further discloses the annuluses of the underfill material 230 do not completely cover the respective electrically conductive balls 222, and the electrical and mechanical connecting of the surface of the substrate or IC chip to the second substrate or IC chip using the electrically conductive balls 222 bonded to the surface of the substrate or IC chip 212 comprises bonding uncovered portions of the electrically conductive balls 222 to the second substrate or IC chip 202.
Claims 9, 19, 21 and 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yim et al (US 2023/0042622).
Regarding claim 9, Yim (Fig. 1A and 3C-3E) discloses a method of connecting a substrate or integrated circuit (IC) chip 200 ([0037]) and a second substrate or IC chip 100 ([0039]), the method comprising: disposing electrically conductive balls 50/60 on electrical bonding pads 226L (Fig. 3C and [0037]) of a surface of the substrate or IC chip 200 to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, wherein the disposing includes: disposing the electrically conductive balls 50/60 of at least two different types ([0046] and [0047]) on the electrical bonding pads 226L of the surface of the substrate or IC chip to form the BGA comprising the electrically conductive balls of the at least two different types disposed on the surface of the substrate or IC chip; and electrically and mechanically connecting the surface of the substrate or IC chip 200 to the second substrate or IC chip 100 using the BGA disposed on the surface of the substrate or IC chip 200 (Fig. 3E).
Regarding claims 19, 21 and 23, Yim (Fig. 1A and 3C-3E) further discloses: the electrically conductive balls 50/60 of at least two different types include: a first type of electrically conductive ball 60 comprising a solder ball without a core of copper or copper alloy ([0047]), and a second type of electrically conductive ball 50 comprising a core of copper or copper alloy 52 coated with a coating 54/56 ([0046]); the coating 54 comprises a nickel or gold film coating the core 52 of copper or copper alloy ([0046]); and the coating 56 comprises a solder material coating the core of copper or copper alloy 52 ([0046]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Quinnones et al (US 2005/0082670) in view of JP 2005-268704A (with English translation attached).
Regarding claim 3, Quinnones (Figs. 3A-3B) further discloses the disposing of the underfill 24 includes: after the bonding, dispensing the underfill material 24 comprising a liquid epoxy or plastic molding compound ([0031]) on the surface of the substrate or IC chip 10, wherein the underfill material 24 collects around the bonds between the electrically conductive balls 14 and the electrical bonding pads 16; and after the dispensing, curing the liquid epoxy or plastic molding compound to solidify the liquid epoxy or plastic molding compound ([0030]).
Quinnones discloses the dispensing of the underfill material by capillary action.
However, JP ‘704 (Fig. 1) teaches a method of dispensing the underfill material 13 on the surface of the substrate or IC chip 11, wherein the underfill material 13 collects around the bonds between the electrically conductive balls and the electrical bonding pads by capillary action (“capillary phenomenon”, page 2, paragraph 6 of translation). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispensing the underfill material of Quinnones by capillary action because it is a simple equivalent process which is well known and commonly used for filling the underfill between the gaps of the solder balls.
Regarding claims 8 and 17, Quinones (Figs. 3A-3B) further discloses: the annuluses 22 of the underfill material do not completely cover the respective electrically conductive balls 14; and the annuluses 22 of the underfill material have heights in a range of 20% and 90% of a diameter ( or a height of ball) of the electrically conductive balls 14 ([0029]).
Quinones does not disclose the annuluses of the underfill material extend away from the respective bonds along the surface of the substrate or IC chip a distance that is in a range of 20% and 90% of a diameter of the electrically conductive ball.
However, it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the annuluses of the underfill material extend away with a distance within a range as claimed because such distance could be optimized during routine experimentation depending upon the desired material of the underfill. It appears that these changes produce no functional differences of preventing the conductive balls from cracking and preventing the conductive balls from peeling off and therefore would have been obvious.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 3,871,015) in view of Quinones et al (US 2005/0082670).
Regarding claim 9, Lin (Fig. 3) discloses a method of connecting a substrate or integrated circuit (IC) chip 10 (column 2, lines 60-62) and a second substrate or IC chip 16 (column 3, lines 3-4), the method comprising: disposing electrically conductive balls 30/28 on a surface of the substrate or IC chip to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip 10, wherein the disposing includes: disposing the electrically conductive balls of at least two different types (i.e., solder and copper, column 5, lines 30-38) on the electrical bonding pads of the surface of the substrate or IC chip to form the BGA comprising the electrically conductive balls 30/28 of the at least two different types disposed on the surface of the substrate or IC chip; and electrically and mechanically connecting the surface of the substrate or IC chip 10 to the second substrate or IC chip 16 using the BGA disposed on the surface of the substrate or IC chip 10.
Lin does not disclose the conductive balls 30/28 disposed on the electrical bonding pads of the surface of the substrate or IC chip 10.
However, Quinones (Fig. 3A) teaches a method comprising the conductive balls 14 disposed on the electrical bonding pads 16 of the surface of the substrate or IC chip 10. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose the conductive balls of Lin on the electrical bonding pads of the surface of the substrate or IC chip in order to provide the electrical connections between the conductive balls and the electronic components within the substrate or IC chip.
Regarding claim 10, Lin (Fig. 3) further discloses the electrically conductive balls of at least two different types include: a first type of electrically conductive ball 30 (corresponding conductive ball 100 in Fig. 5) comprising a solder ball (column 5, lines 30-38) without a core of copper or copper alloy; and a second type of electrically conductive ball 28 (corresponding conductive ball 106 in Fig. 5) consisting of a copper or copper alloy (column 5, lines 30-38).
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yim et al (US 2023/0042622) in view of Park et al (US 2016/0190054).
Yim (Fig. 1A) discloses does not disclose the coating 54 comprises a nickel or gold film coating the core of copper or copper alloy 52 ([0046]) , but Yim does not disclose the coating comprises an organic solderability preservative coating the core of copper or copper alloy.
However, Park teaches a method comprising the coating 114 comprises a nickel or gold film coating the core of copper or copper alloy 113 (Fig. 4, [0044] and [0047]) or the coating 302 comprises an organic solderability preservative coating the core of copper or copper alloy 113 (Fig. 3 and [0059]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the coating of Yim as a nickel or organic solderability preservative because they are equivalent anti-oxide materials that would prevent oxidation of the core body, as taught by Park ([0048]).
Claims 2-8, 17, 25-26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (US 2016/0240509) in view of Nakamura et al (US 6,372,547).
Regarding claim 2, Kwon (Figs. 1-5) discloses a method of connecting a substrate or integrated circuit (IC) chip 10 ([0033]) and a second substrate or IC chip 120 (or 40 in Fig. 13, [0061]), the method comprising: disposing electrically conductive balls 12/14 on electrical bonding pads 18 of a surface of the substrate or IC chip 10 to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip 10, wherein the disposing includes: bonding the electrically conductive balls 12/14 to the electrical bonding pads 18 of the surface of the substrate or IC chip 10 (Fig. 2); and electrically and mechanically connecting the surface of the substrate or IC chip 10 to the second substrate or IC chip 120 (Fig. 5 or 13) using the BGA disposed on the surface of the substrate or IC chip 10.
Kwon does not disclose disposing the underfill material on the surface of the substrate or IC chip around bonds between the electrically conductive balls and the electrical bonding pads.
However, Nakamura (Fig. 3) teaches a method comprising disposing the underfill material 7 (column 8, lines 12-15) on the surface of the substrate or IC chip 20 around bonds between the electrically conductive balls 2 and the electrical bonding pads 22. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kwon by disposing the underfill material on the surface of the substrate or IC chip around bonds between the electrically conductive balls and the electrical bonding pads in order to prevent the electrical conductive balls from cracking and prevent the electrical conductive balls from peeling off, as taught by Nakamura (column 2, lines 19-23).
Regarding claim 4, Kwon (Figs. 1-5) further discloses: the disposing of the electrically conductive balls 12/14 on the electrical bonding pads 18 of the surface of the substrate or IC chip 10 to form the BGA includes: disposing a first type of electrically conductive ball 14 comprising a solder ball without a core of copper or copper alloy ([0052], “solder balls”) in a peripheral region of the surface of the substrate or IC chip 10 (Fig. 1); and disposing a second type of electrically conductive ball 12 consisting of a copper or copper alloy or comprising a core of copper or copper alloy 7 (i.e., layer 7 is a portion of a core) coated with a coating 9 (see Fig. 4, a core layer 7 of copper coated with layer 9, [0051]) in a central region of the surface of the substrate or IC chip 10 that is surrounded by the peripheral region.
Regarding claim 3, Nakamura (Fig. 3) further teaches: the disposing of the underfill 7 includes: after the bonding, dispensing the underfill material 7 comprising a liquid epoxy or plastic molding compound (column 7, lines 48-59 and column 8, lines 12-15) on the surface of the substrate or IC chip 20, wherein the underfill material 7 collects around the bonds between the electrically conductive balls 2 and the electrical bonding pads 22 by capillary action (i.e., “a syringe is ejected between the solder balls”, column 7, lines 48-49); and after the dispensing, curing the liquid epoxy or plastic molding compound to solidify the liquid epoxy or plastic molding compound (column 2, lines 64-67).
Regarding claim 5, Nakamura (Fig. 3) further teaches the underfill material 7 disposed around the bonds between the electrically conductive balls 2 and the electrical bonding pads 22. It is noted that because the underfill material 7 partially disposed around and encircling the conductive balls 2, the underfill material 7 would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claims 6-7, Nakamura (Fig. 3) further teaches: the annuluses of the underfill material 7 do not completely cover the respective electrically conductive balls 2; and the annuluses of the underfill material 7 have heights in a range of 20% and 90% of a diameter of the electrically conductive balls 2 (column 7, lines 40-42 and 48-53, also see column 2, lines 46-48).
Regarding claims 8 and 17, Nakamura (Fig. 3) further teaches: the annuluses 7 of the underfill material do not completely cover the respective electrically conductive balls 2; and the annuluses 7 of the underfill material have heights in a range of 20% and 90% of a diameter of the electrically conductive balls 2 (column 7, lines 40-42 and 48-53, also see column 2, lines 46-48).
Nakamura does not disclose the annuluses of the underfill material extend away from the respective bonds along the surface of the substrate or IC chip a distance that is in a range of 20% and 90% of a diameter of the electrically conductive ball.
However, it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the annuluses of the underfill material extend away with a distance within a range as claimed because such distance could be optimized during routine experimentation depending upon the desired material of the underfill. It appears that these changes produce no functional differences of preventing the conductive balls from cracking and preventing the conductive balls from peeling off and therefore would have been obvious.
Regarding claim 25, Kwon (Figs. 1-5) discloses a method of connecting a substrate or integrated circuit (IC) chip 10 ([0033]) and a second substrate or IC chip 120 (or 40 in Fig. 13, [0061]), the method comprising: bonding electrically conductive balls 12/14 to electrical bonding pads 18 of a surface of the substrate or IC chip; and electrically and mechanically connecting the surface of the substrate or IC chip 10 to the second substrate or IC chip 120 (or 40 in Fig. 13) using the electrically conductive balls 12/14 bonded to the surface of the substrate or IC chip 10.
Kwon does not disclose disposing the underfill material on the surface of the substrate or IC chip around bonds between the electrically conductive balls and the electrical bonding pads.
However, Nakamura (Fig. 3) teaches a method comprising disposing the underfill material 7 (column 8, lines 12-15) on the surface of the substrate or IC chip 20 around bonds between the electrically conductive balls 2 and the electrical bonding pads 22. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kwon by disposing the underfill material on the surface of the substrate or IC chip around bonds between the electrically conductive balls and the electrical bonding pads in order to prevent the electrical conductive balls from cracking and prevent the electrical conductive balls from peeling off, as taught by Nakamura (column 2, lines 19-23).
Regarding claim 26, Nakamura (Fig. 3) further teaches the underfill material 7 disposed around the bonds between the electrically conductive balls 2 and the electrical bonding pads 22. It is noted that because the underfill material 7 partially disposed around and encircling the conductive balls 2, the underfill material 7 would inherently form annuluses encircling the conductive balls and respective bonds.
Regarding claim 27, Nakamura (Fig. 3) further teaches: the annuluses of the underfill material 7 do not completely cover the respective electrically conductive balls 2, and the electrical and mechanical connecting of the surface of the substrate or IC chip to the second substrate or IC chip using the electrically conductive balls 2 bonded to the surface of the substrate or IC chip 20 comprises bonding uncovered portions of the electrically conductive balls 2 to the second substrate or IC chip 8 (labeled in Fig. 2).
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/PHAT X CAO/ Primary Examiner, Art Unit 2817
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