Prosecution Insights
Last updated: July 17, 2026
Application No. 18/103,850

SCALED LINER LAYER FOR ISOLATION STRUCTURE

Non-Final OA §103
Filed
Jan 31, 2023
Priority
Nov 16, 2018 — provisional 62/768,569 +1 more
Examiner
FREY, KIMBERLY NEWMAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
17 granted / 22 resolved
+9.3% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
55 currently pending
Career history
91
Total Applications
across all art units

Statute-Specific Performance

§103
85.0%
+45.0% vs TC avg
§102
12.3%
-27.7% vs TC avg
§112
1.6%
-38.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 22 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/26 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 8 are rejected under U.S.C. 103 as being unpatentable over Lin et al.; US 2020/0020569; 07/2018 in view of Chang et al.; US 2020/0058784 A1; 08/2018 and further in view of Huang; US 10,573,725 B1; 09/2018 Claim 1: Lin discloses a method for semiconductor processing ( [0029] a dielectric gap-filling process for a semiconductor device ), the method comprising: forming fins ( Fig. 6A semiconductor strips #303 ) on a substrate ( Fig. 6A a substrate #201 ); forming a liner layer ( Fig. 6A the liner layer #401) conformally on and between the fins ( Fig. 6A #303 ), forming the liner layer comprising: and densifying, using a plasma treatment ( [ 0038] The formation of the liner layer #401 may include any suitable method, such as ALD, CVD, high density plasma chemical vapor deposition, PVD, a combination thereof, or the like ) , the pre-liner layer ( Fig. 6A #501) to form the liner layer ( Fig. 6A #401 ), wherein the liner layer comprises silicon nitride ( [ 0038] the liner layer #401 may comprise a semiconductor (e.g., silicon) nitride ); Lin does not appear to disclose conformally depositing a pre-liner layer directly on and between the fins, wherein the pre-liner layer comprises amorphous silicon; forming a dielectric material directly on the liner layer and between the fins. Huang discloses conformally depositing a pre-liner layer ( Fig. 4D #110 ) directly on and between the fins ( as shown in Fig. 4D ), wherein the pre-liner layer comprises amorphous silicon ( Col. 7 lines 23 – 24 the liner is selected from polysilicon (poly-Si) or amorphous silicon (a-Si)). Huang does not appear to disclose forming a dielectric material directly on the liner layer and between the fins. However, Chang teaches forming a dielectric material ( Fig. 4A #60 ) directly on the liner layer ( Fig. 4A #50 ) and between the fins ( Fig. 4A #40 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chang with Lin and Huang to implement forming a dielectric material directly on the liner layer and between the fins because this would provide electrical insulation between adjacent transistor components (shallow trench isolation) and help form the gate dielectric. Claim 2: Lin, Huang, and Chang disclose the method of claim 1 ( as discussed above). Lin teaches forming the liner layer ( Fig. 6A #401 ) is performed in a single processing system ( [ 0038] The formation of the liner layer #401 may include any suitable method, such as ALD, CVD, high density plasma chemical vapor deposition, PVD, a combination thereof, or the like ), conformally depositing the pre-liner layer ( [0039] The formation of the precursor soak layer #501 may include any suitable method, such as ALD, CVD, HDP-CVD, a combination thereof, or the like ) is performed in a first processing chamber of the single processing system ( In a Chemical Vapor Deposition (CVD) system the process chamber is where the deposition takes place), densifying the pre-liner layer is performed in a second processing chamber of the single processing system ( A pre-treatment chamber may be used in a CVD system for pre-treating substrates with plasma ), and the substrate ( Fig. 6A #201) is transferred from the first processing chamber to the second processing chamber through a transfer apparatus of the single processing system ( A transfer chamber often equipped with a robotic arm facilitates transfer of substrates between different processing chambers within the CVD system). Claim 3: Lin, Huang, and Chang disclose the method of claim 2 (as discussed above). Lin teaches the substrate ( Fig. 6A #201 ) is transferred from the first processing chamber ( CVD pre-treatment chamber ) to the second processing chamber ( CVD process chamber) without exposing the substrate to an atmospheric ambient environment ( CVD transfer chambers are typically designed to operate under a vacuum or controlled atmosphere to prevent contamination and maintain the process integrity of the interconnected chambers). Claim 4: Lin, Huang, and Chang disclose the method of claim 2 (as discussed above). Lin teaches the substrate ( Fig. 6A #201) is transferred from the first processing chamber ( CVD pre-treatment chamber ) to the second processing chamber ( CVD process chamber) in a transfer environment in the transfer apparatus with a pressure less than or equal to 300 Torr ( Plasma-Enhanced CVD systems often utilize a transfer chamber that operates under a pressure range around 0.1 to 10 Torr) without removing the transfer environment during the transferring of the substrate from the first processing chamber to the second processing chamber ( CVD transfer chambers are typically designed to operate under a vacuum or controlled atmosphere to prevent contamination and maintain the process integrity of the interconnected chambers). Claim 5: Lin, Huang, and Chang disclose the method of claim 1 (as discussed above). Lin teaches forming the liner layer (Fig. 6A #401) does not include using a chlorine-containing gas ( Physical Vapor Deposition (PVD) deposits material by physical means rather than chemical reactions with gaseous precursors). Claim 6: Lin, Huang, and Chang disclose the method of claim 1 (as discussed above). Lin teaches forming the dielectric material ( Fig. 6A #601 ) comprises: flowing a flowable material ( [0043] The dielectric layer #601 may comprise an oxide, such as silicon oxide, a nitride, such as silicon nitride, a combination thereof, or the like, and may be formed by ALD, CVD, HDP-CVD, flowable CVD (FCVD), a combination thereof, or the like ); and converting the flowable material to the dielectric material ( Fig. 6A #601 ), converting comprising exposing the flowable material to an environment having pressure in a range from 1 Bar to 80 Bar ( Supercritical Fluid (SCF) processing operates in the range of 1 Bar to 80 Bar and shares the common goal with Flowable CVD of depositing highly conformal films in advanced semiconductor manufacturing ). Claim 8: Lin, Huang, and Chang disclose the method of claim 1 ( as discussed above). Lin teaches recessing the dielectric material ( Fig. 13A #601) and the liner layer ( Fig. 13A #401), wherein after recessing, the fins protrude ( Fig. 13A #1303 ) above top surfaces of the dielectric material ( Fig. 13A #601) and the liner layer ( Fig. 13A #401). Response to Amendment/Arguments Applicant’s arguments, see RCE, filed 03/09/26, with respect to the rejection(s) of claims 1-8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Huang. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.N.F./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Show 6 earlier events
Dec 17, 2025
Final Rejection mailed — §103
Feb 25, 2026
Interview Requested
Mar 09, 2026
Request for Continued Examination
Mar 17, 2026
Response after Non-Final Action
Apr 08, 2026
Non-Final Rejection mailed — §103
Jun 26, 2026
Interview Requested
Jul 02, 2026
Examiner Interview Summary
Jul 02, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
86%
With Interview (+8.3%)
3y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 22 resolved cases by this examiner. Grant probability derived from career allowance rate.

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