DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 9-12, filed 2/4/2026, with respect to the rejection of claims 1-4, 6-11 and 13-20 under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0199238 to Tan et al. (Tan) and the rejection of claims 5 and 12 are under 35 U.S.C. 103 as being unpatentable over Tan have been fully considered and are persuasive only insofar as Tan is not understood to disclose “wherein the handler is operable to: to load and unload DUTs on the plurality of test sites” as recited in claim 1 and the similar functionality recited in amended claims 7, 14, 18. On this basis, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tan in view of US 6,323,669 to Kang (Kang).
Applicant's remaining arguments filed 2/4/2026 have been fully considered but they are not persuasive.
At the outset, the examiner provides a comparison between Fig. 1 of the present invention (a top view of exemplary automated test equipment 110 and an exemplary handler 130) and Fig. 3 of Tan.
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Tan’s handler (at least burn-in-board 104 that includes one or more the microcontroller units (MCUs) 422 of a corresponding one or more burn-in daughter boards 314, with each daughter board 314 containing an IC 106 to be accelerated stress tested) includes a real time tester interface (connection between the burn-in mother board 104 and the communication socket 110) and performs all of handler functionality of amended claim 1, with the exception of being operable to load and unload DUTs on the plurality of test sites. Newly-cited US 6,323,669 to Kang (Kang) discloses a handler that includes a tester interface (e.g., Fig. 2, burn-in board connector 28 installed on an edge of burn-in board 26) and that is configured to load and unload DUTs on the plurality of test sites (Kang, e.g., Fig. 1, an insertion tool 116 for inserting IC device 162 to a socket 30 of burn-in board 26 and a removal tool 118 for removing IC device 162 from socket 30). The combination of Tan and Kang (see rejection of claim 1 below) discloses all limitations of claim 1.
Applicant states at page 11:
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In response, the examiner first notes that the only apparent difference between Tan’s arrangement and “a handler that can load and unload DUTs on the plurality of test sites, control thermal management functions of the plurality of test sites; and provide a test site specific signal to the ATE via the real time tester interface to test a DUT coupled to a specific test site of the plurality of test sites” (as stated in applicant argument above) is that Tan does not disclose its arrangement is operable to load and unload DUTs on the plurality of test sites. Kang, taken in combination with Tan, cures this deficiency. Further, the examiner notes the claim 1 recites “provide a test site specific signal to the ATE via the real time tester interface to test a DUT”, which does not affirmatively exclude indirect communication with the ATE. Further, the examiner maintains Tan does implicitly disclose that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106 (see rejection of claim 4, for example). On this point, the examiner notes that Tan discloses that communication between computer 100 and the burn-in mother board 104 can be implemented using, for example I2C communication (Tan, e.g., paragraph 30), which one of ordinary skill in the art would understand utilizes identification information (i.e., addresses) in order implement communication.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended claim 1 has been amended to recite “wherein the handler is operable to: to load and unload DUTs on the plurality of test sites”. Analogous amendments have been made to claims 7, 14, 18, and claim 21 recites a similar limitation. Applicant has not pointed out where the new (or amended) claim is supported, nor does there appear to be a written description of the claim 1 limitation “wherein the handler is operable to: to load and unload DUTs on the plurality of test sites” and the similar limitations in claims 7, 14, 18 and 21, in the application as filed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0199238 to Tan et al. (Tan) in view of US 6,323,669 to Kang (Kang).
Regarding claim 1, Tan discloses a system for testing a device under test (DUT), the system comprising:
a handler comprising a real time tester interface (Tan, e.g., Figs. 1, 3-4B and paragraphs 25-31, handler in the form of at least burn-in-board 104 that includes one or more the microcontroller units (MCUs) 422 of a corresponding one or more burn-in daughter boards 314, with each daughter board 314 containing an IC 106 to be accelerated stress tested; note that each burn-in daughter board 314 includes a connector 428 that plugs into a connector 318 on a burn-in mother board 104, with the burn-in mother board 104 in turn being plugged into a communication socket 110, with the communication socket 110 being in communication with a computer (PC) 100 via a driver interface board 102, with the PC 100 controlling accelerated stress testing; the connection between the burn-in mother board 104 and the communication socket 110 (Fig. 1) defines a real time tester interface of the handler);
an automated test equipment (ATE) coupled to the real time tester interface (see Tan as discussed above, Tan’s PC 100 constitutes an ATE coupled to the real time tester interface); and
a plurality of test sites (see Tan as discussed above, each daughter board 314 containing an IC 106 to be accelerated stress tested, with the IC 106 being received in a heater socket 316 that defines a test site);
wherein the handler is operable to:
control thermal management functions of the plurality of test sites (see Tan as discussed above, each daughter board 314 containing an IC 106 to be accelerated stress tested, with the IC 106 being received in a heater socket 316 that defines a test site; also see paragraph 29, the microcontroller unit (MCU) 422 may be programmed to apply stress voltages to the packaged IC 106 and also may be programmed to control the stress temperature of the heater 420 in the heater socket 316); and
provide a test site specific signal to the ATE via the real time tester interface to test a DUT coupled to a specific test site of the plurality of test sites, wherein the test site specific signal corresponds to the specific test site (see Tan as discussed above, the connection between the burn-in mother board 104 and the communication socket 110 (Fig. 1) defines a real time tester interface; also see Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred, and also the type of failure that occurred; Tan’s PC 100 constitutes an ATE, and the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific signal to the ATE; note in Fig. 3 of Tan that the particular daughterboard 314 containing the failed IC 106 is one of a plurality of daughterboards 314; the failed IC 106 is therefore coupled to a specific test site (e.g., a specific test site in the corresponding daughterboard 314) of a plurality of test sites (e.g., the plurality of daughterboards 314, each containing a site for a DUT).
Tan discloses that burn-in board 104 may be populated with ICs 106 to be accelerated stress tested (e.g., Fig. 5 and paragraph 34), but Tan is not relied upon as explicitly disclosing wherein the handler is operable to load and unload DUTs on the plurality of test sites. Kang relates to an apparatus and a method for testing whether integrated circuit (IC) device pins securely contact IC socket terminals. Kang discloses that apparatus may include: a table; a burn-in board having a burn-in board connector; respective tools for loading the device from an IC tray to a positioning jig on the X-Y table, for inserting the device into a socket of the burn-in board, for removing the device from a socket of the burn-in board and for moving the device to a DC test position; a contact part for contacting the burn-in board connector; and a contact tester for testing the contact between device pins and socket terminals (Kang, e.g., Abstract; also see Figs. 1-2 and accompanying description). Kang therefore discloses a handler that includes a tester interface (e.g., Fig. 2, burn-in board connector 28 installed on an edge of burn-in board 26) and that is configured to load and unload DUTs on the plurality of test sites (Kang, e.g., Fig. 1, an insertion tool 116 for inserting IC device 162 to a socket 30 of burn-in board 26 and a removal tool 118 for removing IC device 162 from socket 30). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the handler is operable to load and unload DUTs on the plurality of test sites. In this way, in the manner disclosed by Kang, loading and unloading DUTs on the plurality of test sites can be automated.
Regarding claim 2, Tan in view of Kang discloses wherein the test site specific signal comprises a test site specific alarm (see Tan as applied to claim 1, e.g., Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific alarm), and wherein the handler is further operable to:
detect a temperature malfunction of the DUT (see Tan as applied to claim 1; note that Tan’s accelerated testing applies a stress voltage and stress temperature to the IC 106; Tan’s detection of a packaged IC 106 failure is therefore detection of a temperature malfunction of the IC because it occurs at least in part as a result of the application of a stress temperature);
perform test site specific alarm handling (see Tan as applied to claim 1, particularly paragraph 39, Tan’s MCU 422 sends notification of an IC 106 failure to the burn-in PC 100, which constitutes site specific handling of an alarm); and
execute a test site specific shutdown (see Tan as applied to claim 1, e.g., Fig. 5 and paragraphs 32-48, particularly paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; the examiner notes that termination of a test on the failed IC 106 by MCU 422 constitutes execution of a test site specific shutdown).
Regarding claim 3, Tan in view of Kang discloses wherein the handler is further operable to influence data handling of the DUT by the ATE using the test site specific signal via the real time tester interface (see Tan as applied to claim 1, Tan discloses that the MCU 422 is operable to influence data handling of a failed packaged IC 106 by the burn-in PC 100, see, e.g., paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508).
Regarding claim 4, Tan in view of Kang discloses wherein the test site specific signal comprises:
test site identification information (see Tan as applied to claim 1, e.g., Fig. 5 and paragraphs 32-48, particularly paragraphs 39-40, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; in this arrangement, it is at least implicit that that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106; also note that Tan discloses that communication between computer 100 and the burn-in mother board 104 can be implemented using, for example I2C communication (Tan, e.g., paragraph 30), which one of ordinary skill in the art would understand utilizes identification information (i.e., addresses) in order implement communication); and
regulation information, and
wherein the test site identification information associates the specific test site with the regulation information (see Tan as applied above, the data sent by the failing MCU 422 pertaining to the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes regulation information of the MCU 422 that is identified as failing).
Claim 5 recites wherein the test site identification information comprises a test site ID modulated onto the test site specific signal. As discussed above, in connection with claim 4, it is at least implicit that that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106. Although Tan is not relied upon as explicitly disclosing wherein the test site identification information comprises a test site ID, the examiner notes that each of Tan’s MCU 422 (see Figs. 3 and 4A) must necessarily be uniquely identifiable by the PC 100. If this were not the case, the PC 100 would not know from which MCU 422 of the plurality of MCUs 422 a signal/data indicating a failure of an IC 106 is received. The examiner takes Official notice of the fact that the use of device ID numbers, alpha-numeric addresses and the like for distinguishing from what processing devices a signal/data is received was well-known and conventional before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the test site identification information comprises a test site ID (e.g., a device identifier of the MCU 422 from which a signal/data indicating a failure of an IC 106 is received in order to uniquely identify the MCU 422 of interest from the other MCUs 422.
Tan as modified in this manner is not relied upon as explicitly disclosing that the test site ID is modulated onto the test site specific signal. Tan nonetheless discloses in certain embodiments that Bluetooth connections may be used to establish communication between a PC and the burn-in mother board 104 (Tan, e.g., paragraph 52). The examiner takes Official notice of the fact that the use modulation schemes such as GFSK, π/4-DQPSK (differential quadrature phase-shift keying) and 8-DPSK modulation for modulating data onto a signal for Bluetooth communication was known before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the test site ID is modulated onto the test site specific signal. In this way, in the manner disclosed by Tan, Bluetooth can used to exchange data between the burn-in mother board 104 and the PC 100.
Regarding claim 6, Tan in view of Kang discloses wherein the regulation information comprises at least one of:
timing information;
control amplitude information; and
control duration information (see Tan as applied to claim 4, Tan, e.g., paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred, and also the type of failure that occurred; the examiner notes that Tan’s stress conditions include voltage and thermal stress; accordingly, Tan’s data transmitted to the PC 100 regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes both timing information (e.g., stress conditions that existed at time of failure) as well as control amplitude information (the stress conditions)).
Claim 7 recites automated test equipment (ATE) for testing a device under test, the ATE comprising:
a processor; and
a real time handler interface coupled to a handler, wherein the handler is operable to:
load and unload DUTs on the plurality of test sites, and
control thermal management functions of the plurality of test sites, and wherein the real time handler interface is operable to receive a test site specific signal from the handler to test a DUT coupled to the handler using the processor, wherein the DUT is disposed in a specific test site of the plurality of test sites,
and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for the reasons discussed above in connection with claim 1, recognizing that Tan’s PC 100 constitutes an ATE and comprises a processor and a real time handler interface, e.g., interface of PC 100 connected to driver interface board 102 in Fig. 3. The examiner notes with respect to the recitation “a real time handler interface coupled to a handler, wherein the handler is operable to …” that the handler is regarded by the examiner as a required element of the claimed ATE.
Claim 8 recites wherein the test site specific signal comprises a test site specific alarm, and wherein the processor is operable to handle the test site specific alarm and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claims 2-3, e.g., Tan, Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific alarm; also see paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508).
Regarding claim 9, Tan in view of Kang discloses wherein the processor is further operable to perform a test site specific shutdown based on the test site specific alarm (see Tan as applied to claim 8, Tan, e.g., paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508).
Regarding claim 10, Tan in view of Kang discloses wherein the processor is operable to influence data handling of the device under test in response to a signal received from the handler (see Tan as applied to claim 7, Tan discloses that the PC 100 is operable to influence data handling of an IC 106 in response to a signal received from the MCU 422, Tan, e.g., Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific alarm; also see paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508).
Claim 11 recites wherein the test site specific signal comprises:
test site identification information; and
regulation information, and
wherein the test site identification information associates the specific test site with the regulation information,
and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claim 4, e.g. Tan, Fig. 5 and paragraphs 32-48, particularly paragraphs 39-40, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; in this arrangement, it is at least implicit that that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106; also note that Tan discloses that communication between computer 100 and the burn-in mother board 104 can be implemented using, for example I2C communication (Tan, e.g., paragraph 30), which one of ordinary skill in the art would understand utilizes identification information (i.e., addresses) in order implement communication; the data sent by the failing MCU 422 pertaining to the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes regulation information of the MCU 422 that is identified as failing).
Claim 12 recites wherein the test site identification information comprises a test site ID modulated onto the test site specific signal and is rejected under 35 U.S.C. 103 as unpatentable over Tan for reasons analogous to those discussed above in connection with claim 5.
Claim 13 recites wherein the regulation information comprises at least one of:
timing information;
control amplitude information; and
control duration information,
and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claim 6, e.g., Tan, paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred, and also the type of failure that occurred; the examiner notes that Tan’s stress conditions include voltage and thermal stress; accordingly, Tan’s data transmitted to the PC 100 regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes both timing information (e.g., stress conditions that existed at time of failure) as well as control amplitude information (the stress conditions).
Claim 14 recites a method of testing a device under test (DUT), the method comprising:
providing a test site specific signal to an automated test equipment (ATE) coupled to a handler via a real time tester interface; and
testing the DUT according to the test site specific signal, wherein the DUT is disposed in a test site of the plurality of test sites, wherein the handler is operable to:
load and unload DUTs on the plurality of test sites; and
control thermal management functions of the plurality of test sites,
and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claim 1.
Claim 15 recites wherein the test site specific signal comprises a test site specific alarm, and wherein the method further comprises performing a test site specific shutdown based on the test site specific alarm and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claim 2.
Claim 16 recites influencing data handling of the DUT in response to the test site specific signal and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claim 3.
Claim 17 recites wherein the test site specific signal comprises:
test site identification information; and
regulation information, and wherein the test site identification information associates the specific test site with the regulation information,
and is rejected under 35 U.S.C. 103 as unpatentable over Tan in view of Kang for reasons analogous to those discussed above in connection with claim 4.
Regarding claim 18, Tan discloses a method of testing a device under test (DUT), the method comprising:
receiving a test site specific signal from a handler via a real time tester interface (Tan, e.g., Fig. 5 and paragraphs 32-48, particularly paragraph 39, handler in the form of at least burn-in-board 104; if the MCU on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred); and
testing a DUT coupled to the handler according to the test site specific signa, wherein the DUT is disposed in a specific test side of a plurality of test sites (Tan, e.g., paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; note in Fig. 3 of Tan that the particular daughterboard 314 containing the failed IC 106 is one of a plurality of daughterboards 314; the failed IC 106 is therefore disposed in a specific test site (e.g., a specific test site in the corresponding daughterboard 314) of a plurality of test sites (e.g., the plurality of daughterboards 314, each containing a site for a DUT), wherein the handler is operable to:
control thermal management of the plurality of test sites (see Tan as discussed above, each daughter board 314 containing an IC 106 to be accelerated stress tested, with the IC 106 being received in a heater socket 316 (Figs. 4A-4B) that defines a test site; also see paragraph 29, the microcontroller unit (MCU) 422 may be programmed to apply stress voltages to the packaged IC 106 and also may be programmed to control the stress temperature of the heater 420 in the heater socket 316).
Tan discloses that burn-in board 104 may be populated with ICs 106 to be accelerated stress tested (e.g., Fig. 5 and paragraph 34), but Tan is not relied upon as explicitly disclosing wherein the handler is operable to load and unload DUTs on the plurality of test sites. Kang relates to an apparatus and a method for testing whether integrated circuit (IC) device pins securely contact IC socket terminals. Kang discloses that apparatus may include: a table; a burn-in board having a burn-in board connector; respective tools for loading the device from an IC tray to a positioning jig on the X-Y table, for inserting the device into a socket of the burn-in board, for removing the device from a socket of the burn-in board and for moving the device to a DC test position; a contact part for contacting the burn-in board connector; and a contact tester for testing the contact between device pins and socket terminals (Kang, e.g., Abstract; also see Figs. 1-2 and accompanying description). Kang therefore discloses a handler that includes a tester interface (e.g., Fig. 2, burn-in board connector 28 installed on an edge of burn-in board 26) and that is configured to load and unload DUTs on the plurality of test sites (Kang, e.g., Fig. 1, an insertion tool 116 for inserting IC device 162 to a socket 30 of burn-in board 26 and a removal tool 118 for removing IC device 162 from socket 30). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the handler is operable to load and unload DUTs on the plurality of test sites. In this way, in the manner disclosed by Kang, loading and unloading DUTs on the plurality of test sites can be automated.
Regarding claim 19, Tan in view of Kang discloses wherein the test site specific signal comprises a test site specific alarm, and wherein the method further comprises performing a test site specific shutdown based on the test site specific alarm (Tan, Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific alarm; also see paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508).
Regarding claim 20, Tan in view of Kang discloses wherein the test site specific signal comprises:
test site identification information (Tan, e.g., Fig. 5 and paragraphs 32-48, particularly paragraphs 39-40, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; in this arrangement, it is at least implicit that that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106; also note that Tan discloses that communication between computer 100 and the burn-in mother board 104 can be implemented using, for example I2C communication (Tan, e.g., paragraph 30), which one of ordinary skill in the art would understand utilizes identification information (i.e., addresses) in order implement communication); and
regulation information, and wherein the test site identification information associates the specific test site with the regulation information (see Tan as applied above, the data sent by the failing MCU 422 pertaining to the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes regulation information of the MCU 422 that is identified as failing).
Regarding claim 21, Tan discloses a handler for testing a device under test (DUT), the handler comprising:
a circuit (Tan, e.g., Figs. 1, 3-4B and paragraphs 25-31, circuit in the form of one or more the microcontroller units (MCUs) 422 of a corresponding one or more burn-in daughter boards 314, with each daughter board 314 containing an IC 106 to be accelerated stress tested; note that each burn-in daughter board 314 includes a connector 428 that plugs into a connector 318 on a burn-in mother board 104, with the burn-in mother board 104 in turn being plugged into a communication socket 110, with the communication socket 110 being in communication with a computer (PC) 100 via a driver interface board 102, with the PC 100 controlling accelerated stress testing); and
a real time tester interface operable to couple the circuit with an automated test equipment (ATE), wherein the ATE is coupled to a plurality of test sites (see Tan as discussed above, the connection between the burn-in mother board 104 and the communication socket 110 (Fig. 1), which in turn couples the burn-in mother board 104 to PC 100 via driver interface board 102, defines a real time tester interface; PC 100 constitutes an ATE that is coupled to a plurality of test sites of the circuit, e.g., test sites in the form of heater socket 316 on each daughter board 314), wherein the circuit is operable to:
control thermal management functions of the plurality of test sites (see Tan as discussed above, each daughter board 314 containing an IC 106 to be accelerated stress tested, with the IC 106 being received in a heater socket 316 (Figs. 4A-4B) that defines a test site; also see paragraph 29, the microcontroller unit (MCU) 422 may be programmed to apply stress voltages to the packaged IC 106 and also may be programmed to control the stress temperature of the heater 420 in the heater socket 316);
provide a test site specific signal to the ATE via the real time tester interface to test a DUT coupled to a specific test site of the plurality of test sites, wherein the test site specific signal corresponds to the specific test site (see Tan as discussed above, the connection between the burn-in mother board 104 and the communication socket 110 (Fig. 1) defines a real time tester interface; also see Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred, and also the type of failure that occurred; Tan’s PC 100 constitutes an ATE, and the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific signal to the ATE; note in Fig. 3 of Tan that the particular daughterboard 314 containing the failed IC 106 is one of a plurality of daughterboards 314; the failed IC 106 is therefore disposed in a specific test site (e.g., a specific test site in the corresponding daughterboard 314) of a plurality of test sites (e.g., the plurality of daughterboards 314, each containing a site for a DUT).
Tan discloses that burn-in board 104 may be populated with ICs 106 to be accelerated stress tested (e.g., Fig. 5 and paragraph 34), but Tan is not relied upon as explicitly disclosing wherein the handler is operable to control loading and unloading of DUTs on the plurality of test sites. Kang relates to an apparatus and a method for testing whether integrated circuit (IC) device pins securely contact IC socket terminals. Kang discloses that apparatus may include: a table; a burn-in board having a burn-in board connector; respective tools for loading the device from an IC tray to a positioning jig on the X-Y table, for inserting the device into a socket of the burn-in board, for removing the device from a socket of the burn-in board and for moving the device to a DC test position; a contact part for contacting the burn-in board connector; and a contact tester for testing the contact between device pins and socket terminals (Kang, e.g., Abstract; also see Figs. 1-2 and accompanying description). Kang therefore discloses a handler that includes a tester interface (e.g., Fig. 2, burn-in board connector 28 installed on an edge of burn-in board 26) and that is configured to load and unload DUTs on the plurality of test sites (Kang, e.g., Fig. 1, an insertion tool 116 for inserting IC device 162 to a socket 30 of burn-in board 26 and a removal tool 118 for removing IC device 162 from socket 30). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the handler is operable to control loading and unloading of DUTs on the plurality of test sites. In this way, in the manner disclosed by Kang, loading and unloading DUTs on the plurality of test sites can be automated.
Regarding claim 22, Tan in view of Kang discloses wherein the test site specific signal comprises a test site specific alarm (see Tan as applied to claim 21, e.g., Fig. 5 and paragraphs 32-48, particularly paragraph 39, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the signal from the MCU 422 of one of the burn-in daughter boards 314 that detects a packaged IC 106 failure communicating the failure and data pertaining to accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes a test site specific alarm), and wherein the circuit is further operable to:
detect a temperature malfunction of the DUT (see Tan as applied to claim 21; note that Tan’s accelerated testing applies a stress voltage and stress temperature to the IC 106; Tan’s detection of a packaged IC 106 failure is therefore detection of a temperature malfunction of the IC because it occurs at least in part as a result of the application of a stress temperature);
perform test site specific alarm handling (see Tan as applied to claim 21, particularly paragraph 39, Tan’s MCU 422 sends notification of an IC 106 failure to the burn-in PC 100, which constitutes site specific handling of an alarm); and
execute a test site specific shutdown (see Tan as applied to claim 21, e.g., Fig. 5 and paragraphs 32-48, particularly paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; the examiner notes that termination of a test on the failed IC 106 by MCU 422 constitutes execution of a test site specific shutdown).
Regarding claim 23, Tan in view of Kang discloses wherein the handler is further operable to influence data handling of the DUT by the ATE using the test site specific signal via the real time tester interface (see Tan as applied to claim 21, Tan discloses that the MCU 422 is operable to influence data handling of a failed packaged IC 106 by the burn-in PC 100, see, e.g., paragraph 40, the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508).
Regarding claim 24, Tan in view of Kang discloses wherein the test site specific signal comprises:
test site identification information (see Tan as applied to claim 1, e.g., Fig. 5 and paragraphs 32-48, particularly paragraphs 39-40, if the MCU 422 on one of the burn-in daughter boards 314 detects a packaged IC 106 failure, it sends a signal to the burn-in PC 100 that the packaged IC 106 has failed; it may also send data regarding the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred; the decision is made by the burn-in PC 100 or the MCU 422 to either terminate the test on the failing packaged IC 106 or to continue stress testing in step 508; in this arrangement, it is at least implicit that that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106; also note that Tan discloses that communication between computer 100 and the burn-in mother board 104 can be implemented using, for example I2C communication (Tan, e.g., paragraph 30), which one of ordinary skill in the art would understand utilizes identification information (i.e., addresses) in order implement communication); and
regulation information, and
wherein the test site identification information associates the specific test site with the regulation information (see Tan as applied above, the data sent by the failing MCU 422 pertaining to the accelerated stress conditions applied to the packaged IC 106 at the time the failure occurred constitutes regulation information of the MCU 422 that is identified as failing).
Claim 25 recites wherein the test site identification information comprises a test site ID modulated onto the test site specific signal. As discussed above, in connection with claim 24, it is at least implicit that that signal/data provided to the PC 100 includes information identifying the particular MCU 422 that has failed at least because the PC 100 may then terminate the test on the failing IC 106. Although Tan is not relied upon as explicitly disclosing wherein the test site identification information comprises a test site ID, the examiner notes that each of Tan’s MCU 422 (see Figs. 3 and 4A) must necessarily be uniquely identifiable by the PC 100. If this were not the case, the PC 100 would not know from which MCU 422 of the plurality of MCUs 422 a signal/data indicating a failure of an IC 106 is received. The examiner takes Official notice of the fact that the use of device ID numbers, alpha-numeric addresses and the like for distinguishing from what processing devices a signal/data is received was well-known and conventional before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the test site identification information comprises a test site ID (e.g., a device identifier of the MCU 422 from which a signal/data indicating a failure of an IC 106 is received in order to uniquely identify the MCU 422 of interest from the other MCUs 422.
Tan as modified in this manner is not relied upon as explicitly disclosing that the test site ID is modulated onto the test site specific signal. Tan nonetheless discloses in certain embodiments that Bluetooth connections may be used to establish communication between a PC and the burn-in mother board 104 (Tan, e.g., paragraph 52). The examiner takes Official notice of the fact that the use modulation schemes such as GFSK, π/4-DQPSK (differential quadrature phase-shift keying) and 8-DPSK modulation for modulating data onto a signal for Bluetooth communication was known before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tan such that the test site ID is modulated onto the test site specific signal. In this way, in the manner disclosed by Tan, Bluetooth can used to exchange data between the burn-in mother board 104 and the PC 100.
Conclusion
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/DANIEL R MILLER/Primary Examiner, Art Unit 2858