DETAILED ACTION
This office action is in response to the election filed 1/6/2026.
Currently, claims 1-20 are pending, of which claims 8 and 18 have been withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of the species represented by FIG. 1 is acknowledged.
Claim Objections
Claim 20 is objected to because of the following informalities: The word “comprises” should be “comprising” in line 1. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites “wherein the gate structure comprises a PFET”, implying that a PFET is a part of the gate. However, as is known in the art, it is the gate that is in fact a part of a transistor. Thus, it does not make sense to say that a part comprises a whole.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tipple et al. (US 2020/0152661).
Pertaining to claim 1, Tipple shows, with reference to FIG. 1, a structure comprising:
a floating well (120) of a first dopant type (n) within a semiconductor substrate (para. [0012]);
a second well (107) of a second dopant type within the floating well of the first dopant type;
a reverse bias diode (DIODETWX) at a junction between the floating well and the semiconductor substrate; and
a forward bias diode (DIODEPWTW) at a junction between the floating well and the second well.
Pertaining to claim 2, Tipple shows the floating well comprises a deep N-well and the second well comprises a P-well which is isolated from the semiconductor substrate (FIG. 1).
Pertaining to claim 3, Tipple shows the semiconductor substrate comprises a p-type substrate (para. [0012]).
Pertaining to claim 4, Tipple shows the reverse bias diode and the forward bias diode comprise back-to-back diodes (FIG. 1).
Pertaining to claims 5 and 6, Tipple shows a contact connecting to the second well, wherein the contact provides a fixed bias to the second well and forward biases the floating well to other than ground (para. [0014]).
Pertaining to claim 7, Tipple shows a PFET (102) above the second well (FIG. 1).
Pertaining to claim 10, Tipple shows the floating well is devoid of any contacts (FIG. 1).
Pertaining to claim 11, Tipple shows a structure comprising:
a semiconductor substrate comprising a floating well (120) of a first dopant type (n) and a well (107) of an opposite dopant type (p) to the first dopant type;
a buried insulator layer (113) above the semiconductor substrate;
a semiconductor on insulator material (comprising regions 111, 112, 114) above the insulator buried layer, the semiconductor on insulator material comprising diffusion regions (111, 112);
a gate structure (110) on the semiconductor on insulator material between the diffusion regions; and
a bias contact connecting to the well (para. [0014], lines 3-7).
Pertaining to claim 12, Tipple shows the floating well is devoid of any bias contacts (FIG. 1).
Pertaining to claim 13, Tipple shows the floating well (120) comprises a deep N-well, the well (107) comprises a P-well and the semiconductor substrate comprises a p-type substrate (para. [0012], lines 1-3).
Pertaining to claim 14, Tipple shows the P-well is isolated within the N-well (para. [0021], lines 12-14).
Pertaining to claim 15, Tipple shows back-to-back diodes (DIODETWX, DIODEPWTW) at a junction between the floating well and the semiconductor substrate and the floating well and the well. (FIG. 1).
Pertaining to claim 16, Tipple shows the back-to-back diodes comprise a reverse bias between the floating well and the semiconductor substrate and a forward bias diode between the floating well and the well (FIG. 1).
Pertaining to claim 17, Tipple shows deep trench isolation structures (unlabeled, adjacent diffusion regions 111, 112) within the well (FIG. 1).
Pertaining to claim 19, Tipple shows the gate structure comprises a PFET (102) (FIG. 1).
Pertaining to claim 20, Tipple shows a method comprising:
forming a floating well (120) of a first dopant type (n) within a semiconductor substrate; and
forming a second well (107) of a second dopant type (p) within the floating well of the first dopant type,
wherein a first diode (DIODETWX) is formed at a junction between the floating well and the semiconductor substrate, and a second diode (DIODEPWTW) is formed at a junction between the floating well and the second well.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including the structure having the limitations expressed in claims 1 and 5, and further comprising deep trench isolation structures that meet the limitations “within the body of the second well” and “between the floating well and the second well”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Inaba (US 7,259,428) discloses an invention similar to Applicant’s.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896