DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/10/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 13-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0054132 to Wang et al. (hereinafter Wang).
With respect to claim 1, Wang discloses an electrostatic discharge (ESD) protection structure (e.g., bipolar junction transistor (BJT) with increased breakdown voltage for electrostatic discharge protection circuits) (Wang, Figs. 1, 2A, ¶0002, ¶0006-¶0009, ¶0062-¶0072, ¶0093-¶0094), comprising:
a semiconductor substrate (10) (Wang, Figs. 1, 2A, ¶0064-¶0065);
a first n-type well region (20) (Wang, Figs. 1, 2A, ¶0062, ¶0066) disposed in the semiconductor substrate (10);
a p-type well region (30) (Wang, Figs. 1, 2A, ¶0062, ¶0070) disposed in the semiconductor substrate (10) and located adjacent to the first n- type well region (20);
a first p-type doped region (22) (Wang, Figs. 1, 2A, ¶0067) disposed in the semiconductor substrate (10) and located above the first n-type well region (20) in a vertical direction, wherein the first n-type well region (20) is directly connected with the first p-type doped region (22);
a second p-type doped region (32) (Wang, Figs. 1, 2A, ¶0071,) disposed in the semiconductor substrate (10) and located above the p- type well region (30) in the vertical direction, wherein the p-type well region (30) is directly connected with the second p-type doped region (32); and
an isolation structure (50/52) (Wang, Figs. 1, 2A, ¶0068, ¶0071) disposed in the semiconductor substrate (10), wherein a first portion (52) of the isolation structure (50/52) is located between the first p-type doped region (22) and the second p-type doped region (32) in a first horizontal direction, an edge of the first n-type well region (20) (Wang, Figs. 1, 2A, ¶0066, ¶0070) is located under the first portion (52) of the isolation structure (50/52) in the vertical direction, and a distance (Wang, Figs. 1, 2A, ¶0002, ¶0006, ¶0037) between the first p-type doped region (22) and the edge of the first n-type well region (20) in the first horizontal direction is less than a length of the first portion (52) of the isolation structure in the first horizontal direction,
wherein a length (e.g., a length of the p+ region 32 in a horizontal direction of Fig. 1) of the second p-type doped region (32) (Wang, Figs. 1, 2A, ¶0071) in the first horizontal direction is greater than a length (e.g., a length of the p+ region 22 in a horizontal direction of Fig. 1) of the first p-type doped region (22) (Wang, Figs. 1, 2A, ¶0067) in the first horizontal direction, and an edge of the p-type well region (30) is located under the first portion (52) of the isolation structure in the vertical direction and directly connected with the edge of the first n-type well region (20), wherein a bottom of the first p-type doped region (22) is higher than a bottom of the first portion (52) of the isolation structure in the vertical direction, and a bottom of the second p-type doped region (32) is higher than the bottom of the first portion (52) of the isolation structure in the vertical direction.
Regarding claim 2, Wang discloses the ESD protection structure according to claim 1. Further, Wang discloses the ESD protection structure, wherein the first p-type doped region (22) (Wang, Figs. 1, 2A, ¶0004, ¶0064) is an emitter of a bipolar junction transistor (PNP BJT), and the second p-type doped region (32) is at least a part of a collector of the bipolar junction transistor.
Regarding claim 3, Wang discloses the ESD protection structure according to claim 2. Further, Wang discloses the ESD protection structure, wherein the emitter (22) (Wang, Fig. 2A, ¶0004, ¶0064) and a base (20) of the bipolar junction transistor (PNP BJT) are electrically connected to a first terminal, and the collector (32) of the bipolar junction transistor is electrically connected to a second terminal.
Regarding claim 4, Wang discloses the ESD protection structure according to claim 3. Further, Wang discloses the ESD protection structure, wherein the first terminal is a power pad, and the second terminal is a ground pad (Wang, Fig. 2A, ¶0004, ¶0064).
Regarding claim 6, Wang discloses the ESD protection structure according to claim 1. Further, Wang discloses the ESD protection structure, wherein the distance between the first p- type doped region (22) (Wang, Fig. 2A, ¶0064, ¶0066) and the edge of the first n-type well region (20) in the first horizontal direction is a distance between a bottom of the first p-type doped region (22) and the edge of the first n-type well region (20) in the first horizontal direction.
Regarding claim 13, Wang discloses the ESD protection structure according to claim 1. Further, Wang discloses the ESD protection structure, wherein the first p-type doped region (22) is elongated in a second horizontal direction (e.g., a vertical direction in Fig. 1) (Wang, Figs. 1, 2A, ¶0064, ¶0066, ¶0071), and the second p-type doped region (32) is elongated in the second horizontal direction.
Regarding claim 14, Wang discloses the ESD protection structure according to claim 13. Further, Wang discloses the ESD protection structure, wherein the second horizontal direction (e.g., a vertical direction in Fig. 1) is orthogonal to the first horizontal direction (e.g., a horizontal direction in Fig. 1) (Wang, Figs. 1, 2A, ¶0064, ¶0066, ¶0071).
Regarding claim 15, Wang discloses the ESD protection structure according to claim 1. Further, Wang discloses the ESD protection structure, wherein the p-type well region (30) surrounds the first n-type well region (20) (Wang, Figs. 1, 2A, ¶0064, ¶0066, ¶0071) in a top view (Fig. 1) of the ESD protection structure.
Regarding claim 16, Wang discloses the ESD protection structure according to claim 1. Further, Wang discloses the ESD protection structure, wherein the isolation structure (50/52) surrounds the first p-type doped region (22) and the second p-type doped region (32) in a top view of the ESD protection structure (Wang, Figs. 1, 2A, ¶0064, ¶0068, ¶0071).
Regarding claim 20, Wang discloses the ESD protection structure according to claim 1. Further, Wang discloses the ESD protection structure, wherein the first portion (52) of the isolation structure (Wang, Figs. 1, 2A, ¶0071) is directly connected with the first p-type doped region (22), the second p-type doped region (32), the first n-type well region (20), and the p-type well region (30) (Wang, Figs. 1, 2A, ¶0062, ¶0064, ¶0070).
Claims 5, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0054132 to Wang in view of Kuo et al. (US 2013/0082353, hereinafter Kuo).
Regarding claim 5, Wang discloses the ESD protection structure according to claim 1. Further, Wang does not specifically disclose the ESD protection structure, wherein the distance between the first p- type doped region and the edge of the first n-type well region in the first horizontal direction is equal to or less than 45 nanometers.
However, Kuo teaches forming an ESD protection device (Kuo, Figs. 2-4, 12, ¶0013, ¶0018-¶0037, ¶0046-¶0051) including a BJT device with small chip area consumption and adjustable device characteristics, wherein the first p- type doped region (e.g., the emitter region 260) (Kuo, Figs. 2-4, 12, ¶0027-¶0028, ¶0031-¶0033) is formed above the N-type well (220) including the base of the BJT, the second p- type doped region (e.g., the collector region 270/271) is formed above the P-type well (230/231) and the p-type doped regions (250/251) constituting a collector of the BJT, and an interface (290/291) is formed at the pn-junction between the N-type well (220) and the P-type well (230/231). Further, in Kuo, the distance (301/300) is set between the first p- type doped region (260) and the interface (290/291) or the edge of the N-type well (220), and the distance (310/311) is set between the p- type doped region (250/251) of the collector and the interface (290/291). The distances (300/301) and (310/311) are in a range between 0 to about 7 microns, and adjusted to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT (Kuo, Figs. 2-4, 12, ¶0032-¶0033).
Thus, Kuo recognizes that the distance between the first p- type doped region and the edge of the N-type well impacts device characteristics (e.g., a turn-on voltage, a breakdown voltage, and a holding voltage) of the BJT device. Thus, the distance between the first p- type doped region and the edge of the N-type well is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the distance between the first p- type doped region and the edge of the N-type well as Kuo has identified the distance between the first p- type doped region and the edge of the N-type well as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific distance between the first p- type doped region and the edge of the N-type well that is equal to or less than 45 nanometers in the first horizontal direction, in order to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT as taught by Kuo (¶0032-¶0033) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Wang by optimizing a distance between p- type doped region and the edge of the N-type well of the BJT device as taught by Kuo to have the ESD protection structure, wherein the distance between the first p- type doped region and the edge of the first n-type well region in the first horizontal direction is equal to or less than 45 nanometers, in order to provide a BJT device with small chip area consumption and adjustable device characteristics (Kuo, ¶0013, ¶0032-¶0033, ¶0046-¶0048).
Regarding claim 10, Wang discloses the ESD protection structure according to claim 1. Further, Wang does not specifically disclose the ESD protection structure, wherein an area of the second p-type doped region in the vertical direction is greater than an area of the first p-type doped region in the vertical direction.
However, Kuo teaches forming the ESD protection structure, wherein an area of the second p-type doped region (e.g., collector region 270/250 has greater area in the vertical direction than that of the emitter region 260) (Kuo, Fig. 4, ¶0027, ¶0036) in the vertical direction is greater than an area of the first p-type doped region (260) in the vertical direction.
Further, Kuo teaches that the distance (301/300) is set between the first p- type doped region (260) and the interface (290/291) or the edge of the N-type well (220), and the distance (310/311) is set between the second p- type doped region (270/250) of the collector and the interface (290). The distances (300/301) and (310/311) are in a range between 0 to about 7 microns, and adjusted to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT (Kuo, Figs. 2-4, 12, ¶0032-¶0033). Thus, an area of the second p-type doped region (250/270) is adjusted to achieve the desired distance (310 and 311), and a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT.
Thus, Kuo recognizes that an area of the second p-type doped region impacts device characteristics (e.g., a turn-on voltage, a breakdown voltage, and a holding voltage) of the BJT device. Thus, an area of the second p-type doped region is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, an area of the second p-type doped region as Kuo has identified an area of the second p-type doped region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific area of the second p-type doped region in the vertical direction that is greater than an area of the first p-type doped region in the vertical direction, in order to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT as taught by Kuo (¶0032-¶0033) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Wang by optimizing an area of the second p-type doped region in the vertical direction as taught by Kuo to have the ESD protection structure, wherein an area of the second p-type doped region in the vertical direction is greater than an area of the first p-type doped region in the vertical direction, in order to provide a BJT device with small chip area consumption and adjustable device characteristics (Kuo, ¶0013, ¶0032-¶0033, ¶0046-¶0048).
Regarding claim 17, Wang discloses the ESD protection structure according to claim 1. Further, Wang does not specifically disclose the ESD protection structure, further comprising: a deep n-type well region disposed in the semiconductor substrate, wherein the first n-type well region and the p-type well region are located above the deep n-type well region in the vertical direction.
However, Kuo discloses the ESD protection structure, further comprising: a deep n-type well region (210) (Kuo, Fig. 4, ¶0019, ¶0036) disposed in the semiconductor substrate (200), wherein the first n-type well region (220) and the p-type well region (230) are located above the deep n-type well region (210) in the vertical direction, wherein the buried well (210) is formed to isolate the ESD protection structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Wang by forming the ESD protection device including a buried layer as taught by Kuo to have the ESD protection structure, further comprising: a deep n-type well region disposed in the semiconductor substrate, wherein the first n-type well region and the p-type well region are located above the deep n-type well region in the vertical direction, in order to isolate the ESD protection structure, and thus to obtain improved ESD protection device with adjustable device characteristics (Kuo, ¶0013, ¶0032-¶0033, ¶0046-¶0048).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0054132 to Wang in view of Kuo (US 2013/0082353) as applied to claim 17, and further in view of Han (US 2018/0082994).
Regarding claims 18 and 19, Wang in view of Kuo discloses the ESD protection structure according to claim 17. Further, Wang does not specifically disclose the ESD protection structure, further comprising: a second n-type well region disposed in the semiconductor substrate and located above the deep n-type well region in the vertical direction; and an n-type doped region disposed in the second n-type well region, wherein a second portion of the isolation structure is located between the second p-type doped region and the n-type doped region in the first horizontal direction (as clamed in claim 18); wherein the second n-type well region surrounds the first n-type well region and the p-type well region in a top view of the ESD protection structure (as clamed in claim 19).
However, Han teaches forming the ESD protection structure, further comprising: a second n-type well region (160) (Han, Fig. 3, ¶0055, ¶0061) disposed in the semiconductor substrate (105/110) and located above the deep n-type well region (115) in the vertical direction; and an n-type doped region (155) disposed in the second n-type well region (160), wherein a second portion of the isolation structure (120) is located between the second p-type doped region (140) and the n-type doped region (155) in the first horizontal direction, wherein the second n-type well region (160) has a ring shape to enlarge the area of the base (155) resulting in higher maintenance voltage for ESD protection device (Han, Fig. 3, ¶0055); wherein the second n-type well region (160) surrounds the first n-type well region (175) and the p-type well region (110) in a top view of the ESD protection structure (e.g., the collector region 140 has a ring shape surrounding the emitter region 130, and the base region 155 has a ring shape surrounding the collector region 140 and the emitter region 130, and therefore, in a top view, the second n-type well region including the base 155 surrounds the first n-type well region including the emitter 130 and the p-type well region including the collector region 140) (Han, Fig. 3, ¶0014, ¶0051, ¶0055, ¶0061-¶0062).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Wang/Kuo by forming the ESD protection device including a second n-type well region as taught by Han to have the ESD protection structure, further comprising: a second n-type well region disposed in the semiconductor substrate and located above the deep n-type well region in the vertical direction; and an n-type doped region disposed in the second n-type well region, wherein a second portion of the isolation structure is located between the second p-type doped region and the n-type doped region in the first horizontal direction (as clamed in claim 18); wherein the second n-type well region surrounds the first n-type well region and the p-type well region in a top view of the ESD protection structure (as clamed in claim 19), in order to enlarge the area of the base to have higher maintenance voltage for ESD protection device, and thus to obtain improved ESD protection device (Han, ¶0002, ¶0011, ¶0055, ¶0061-¶0062).
Response to Arguments
Applicant’s arguments with respect to claims 1-6, 10, and 13-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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