DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 11/18/2025.
Applicant’s amendments filed 11/18/2025 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claim 1; and cancellation of claim 9.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-8, 10-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0082353 to Kuo et al. (hereinafter Kuo).
With respect to claim 1, Kuo discloses an electrostatic discharge (ESD) protection structure (Kuo, Fig. 4, ¶0013, ¶0018-¶0037, ¶0046-¶0051), comprising:
a semiconductor substrate (200) (Kuo, Fig. 4, ¶0018, ¶0036);
a first n-type well region (220) (Kuo, Fig. 4, ¶0020, ¶0036) disposed in the semiconductor substrate (200);
a p-type well region (230) (Kuo, Fig. 4, ¶0021, ¶0036) disposed in the semiconductor substrate (200) and located adjacent to the first n- type well region (220);
a first p-type doped region (260) (Kuo, Fig. 4, ¶0025, ¶0027, ¶0036) disposed in the semiconductor substrate (200) and located above the first n-type well region (220) in a vertical direction;
a second p-type doped region (270) (Kuo, Fig. 4, ¶0025, ¶0027, ¶0036) disposed in the semiconductor substrate (200) and located above the p- type well region (230) in the vertical direction; and
an isolation structure (280-282) (Kuo, Fig. 4, ¶0029, ¶0036) disposed in the semiconductor substrate (200), wherein a first portion (281) of the isolation structure (280-282) is located between the first p-type doped region (260) and the second p-type doped region (270) in a first horizontal direction, an edge of the first n-type well region (220) (Kuo, Fig. 4, ¶0029, ¶0036) is located under the first portion of the isolation structure (281) in the vertical direction, and a distance (300) (Kuo, Fig. 4, ¶0031-¶0033, ¶0037) between the first p-type doped region (260) and the edge of the first n-type well region (220) in the first horizontal direction is less than a length of the first portion (281) of the isolation structure in the first horizontal direction,
wherein a length of the second p-type doped region (270/250) (Kuo, Fig. 4, ¶0027, ¶0036) in the first horizontal direction is greater than a length of the first p-type doped region (260) in the first horizontal direction.
Regarding claim 2, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein the first p-type doped region (260) (Han, Fig. 4, ¶0027, ¶0036) is an emitter of a bipolar junction transistor, and the second p-type doped region (270) is at least a part of a collector of the bipolar junction transistor.
Regarding claim 6, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein the distance (300/301) between the first p- type doped region (260) (Kuo, Fig. 4, ¶0031-¶0033, ¶0037) and the edge of the first n-type well region (220) in the first horizontal direction is a distance between a bottom of the first p-type doped region (260) and the edge of the first n-type well region (220) in the first horizontal direction.
Regarding claim 7, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein an edge of the p-type well region (230) (Kuo, Fig. 4, ¶0036) is located under the first portion (281) of the isolation structure (280-282) in the vertical direction.
Regarding claim 8, Kuo discloses the ESD protection structure according to claim 7. Further, Kuo discloses the ESD protection structure, wherein the edge of the first n-type well region (220) (Kuo, Fig. 4, ¶0036) is directly connected with the edge of the p-type well region (230).
Regarding claim 10, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein an area of the second p-type doped region (e.g., collector region 270/250 has greater area in the vertical direction than that of the emitter region 260) (Kuo, Fig. 4, ¶0027, ¶0036) in the vertical direction is greater than an area of the first p-type doped region (260) in the vertical direction.
Regarding claim 11, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein a bottom of the first p-type doped region (260) (Kuo, Fig. 4, ¶0027, ¶0036) is higher than a bottom of the first portion (281) of the isolation structure (280-282) in the vertical direction.
Regarding claim 12, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein a bottom of the second p-type doped region (270) (Kuo, Fig. 4, ¶0027, ¶0036) is higher than a bottom of the first portion (281) of the isolation structure (280-282) in the vertical direction.
Regarding claim 13, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein the first p-type doped region (260) is elongated in a second horizontal direction (e.g., a vertical direction in Fig. 12) (Kuo, Figs. 4, 12, ¶0027, ¶0036, ¶0046-¶0051), and the second p-type doped region (270) is elongated in the second horizontal direction.
Regarding claim 14, Kuo discloses the ESD protection structure according to claim 13. Further, Kuo discloses the ESD protection structure, wherein the second horizontal direction (e.g., a vertical direction in Fig. 12) is orthogonal to the first horizontal direction (e.g., a horizontal direction in Fig. 12) (Kuo, Figs. 4, 12, ¶0036, ¶0046-¶0051).
Regarding claim 15, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein the p-type well region (230) surrounds (e.g., the p-type well region 230 surrounds two sides) the first n-type well region (220) (Kuo, Figs. 4, 12, ¶0036, ¶0046-¶0051) in a top view of the ESD protection structure.
Regarding claim 16, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein the isolation structure (280-282) surrounds (e.g., two sides) the first p-type doped region (260) and the second p-type doped region (270) in a top view of the ESD protection structure (Kuo, Figs. 4, 12, ¶0036, ¶0046-¶0051).
Regarding claim 17, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, further comprising: a deep n-type well region (210) (Kuo, Fig. 4, ¶0019, ¶0036) disposed in the semiconductor substrate (200), wherein the first n-type well region (220) and the p-type well region (230) are located above the deep n-type well region (210) in the vertical direction.
Regarding claim 20, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo discloses the ESD protection structure, wherein the first portion (281) of the isolation structure (280-282) (Kuo, Fig. 4, ¶0029, ¶0036) is directly connected with the first p-type doped region (260), the second p-type doped region (270), the first n-type well region (220), and the p-type well region (230).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 10-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0082994 to Han et al. (hereinafter Han) in view Hwang et al. (US 2014/0367783, hereinafter Hwang).
With respect to claim 1, Han discloses an electrostatic discharge (ESD) protection structure (Han, Fig. 3, ¶0002, ¶0011-¶0026, ¶0037-¶0062), comprising:
a semiconductor substrate (105/110) (Han, Fig. 3, ¶0038-¶0040, ¶0061);
a first n-type well region (175) (Han, Fig. 3, ¶0062) disposed in the semiconductor substrate (105/110);
a p-type well region (110, p-type well region between deep n-type wells 175 and 160) (Han, Fig. 3, ¶0061-¶0062) disposed in the semiconductor substrate (105/110) and located adjacent to the first n- type well region (175);
a first p-type doped region (130) (Han, Fig. 3, ¶0046, ¶0061) disposed in the semiconductor substrate (105/110) and located above the first n-type well region (175) in a vertical direction;
a second p-type doped region (140) (Han, Fig. 3, ¶0048, ¶0061) disposed in the semiconductor substrate (105/110) and located above the p- type well region (110) in the vertical direction; and
an isolation structure (120) (Han, Fig. 3, ¶0043-¶0044, ¶0061) disposed in the semiconductor substrate (105/110), wherein a first portion of the isolation structure (120) is located between the first p-type doped region (130) and the second p-type doped region (140) in a first horizontal direction, an edge of the first n-type well region (175) (Han, Fig. 3, ¶0062) is located under the first portion of the isolation structure (120) in the vertical direction, and a distance between the first p-type doped region (130) (Han, Fig. 3, ¶0061-¶0062) and the edge of the first n-type well region (175) in the first horizontal direction is less than a length of the first portion of the isolation structure in the first horizontal direction.
Further, Han does not specifically disclose that a length of the second p-type doped region in the first horizontal direction is greater than a length of the first p-type doped region in the first horizontal direction.
However, Hwang teaches forming the ESD protection structure including a bipolar junction transistor, wherein the emitter region (307) (Hwang, Figs. 3A, 5, ¶0052, ¶0111) has an area of at least 10 mm2, and the collector region (302) has a length (a-1) of a shorter size of about 0. 5 mm or between 2-3 mm, to provide one or more contact lines (316a), and a length of the longer size of the collector region (302) is between 5 and 100 mm, to provide the ESD transistor with faster control of turn-on operation. Further, Hwang teaches that the area of the active region of the collector region (302) and a length of the shorter size of the collector region (302), which is indicated by "a-1" in Fig. 3B (Hwang, Figs. 3A, 5, ¶0111), should be sufficiently large such that current crowding is not generated. This is for preventing current crowding in a narrow region, when stress flows into the collector region 302 of the BJT (Hwang, Figs. 3A, 5, ¶0079).
Thus, a person of ordinary skill in the art would recognize that with a length of a shorter size of the emitter region of about 1 mm or 2 mm (e.g., for the area of the emitter region: 1 mm x 10 mm=10 mm2 or 2 mm x 5 mm=10 mm2), and a length (a-1) of a shorter size of the collector region of about 2-3 mm, a length (a-1=2 mm or 3 mm) of the second p-type doped region (e.g., the collector region 302) in the first horizontal direction would be greater than a length (e.g., 1 mm or 2 mm) of the first p-type doped region (e.g., the emitter region 307) in the first horizontal direction.
Further, Hwang teaches forming a length of the insulating layer (313) (Hwang, Figs. 3A, 5, ¶0070-¶0071) between the collector region and the emitter region that is sufficiently large, such that a lateral current path is not formed on the surface under the insulating layer and earlier breakdown voltage is stably generated. Thus, a person of ordinary skill in the art would recognize that by forming the insulating layer between the collector region and the emitter region and the collector region having a sufficiently large length, stable breakdown voltage characteristics could be achieved (Hwang, Figs. 3A, 5, ¶0070-¶0071). Also, a person of ordinary skill in the art would be motivated to form the collector region with increased length (e.g., a-1) of a shorter size of the collector region to prevent current crowding in a narrow region (Hwang, Figs. 3A, 5, ¶0079).
Thus, Hwang recognizes that a length of a shorter size of the collector region impacts current distribution and operation of the BJT device. Thus, a length of a shorter size of the collector region is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a length of a shorter size of the collector region as Hwang has identified a length of a shorter size of the collector region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific length of a shorter size of the collector region (e.g., a length of the second p-type doped region), such that a length of the second p-type doped region in the first horizontal direction is greater than a length of the first p-type doped region in the first horizontal direction, in order to prevent current crowding in a narrow region, as taught by Hwang (¶0079) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Han by optimizing a length of a shorter size of the collector region (e.g., a length of the second p-type doped region) and forming a collector region and the insulating layer between the collector region and the emitter region having a sufficiently large length as taught by Hwang to have the ESD protection structure, wherein a length of the second p-type doped region in the first horizontal direction is greater than a length of the first p-type doped region in the first horizontal direction, in order to prevent current crowding in a narrow region of the collector region, to provide one or more contact lines to the collector region, and to provide stable breakdown voltage characteristics, and thus to obtain improved ESD protection device (Hwang, ¶0047-¶0050, ¶0070-¶0071, ¶0079, ¶0111).
Regarding claim 2, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein the first p-type doped region (130) (Han, Fig. 3, ¶0046, ¶0061) is an emitter of a bipolar junction transistor, and the second p-type doped region (140) (Han, Fig. 3, ¶0048, ¶0061) is at least a part of a collector of the bipolar junction transistor.
Regarding claim 3, Han in view Hwang discloses the ESD protection structure according to claim 2. Further, Han discloses the ESD protection structure, wherein the emitter (130) (Han, Fig. 3, ¶0046, ¶0048) of the bipolar junction transistor is electrically connected to a first terminal, and the collector (140) of the bipolar junction transistor is electrically connected to a second terminal, but does not specifically disclose that the emitter and a base of the bipolar junction transistor are electrically connected to a first terminal.
However, Hwang teaches forming the ESD protection structure, wherein the emitter and a base of the bipolar junction transistor (Hwang, Figs. 3A, 5, ¶0046, ¶0048, ¶0085-¶0091) are electrically connected (e.g., through a resistor 420) to a first terminal (e.g., a ground electrode), and wherein the resistor (420) serves to adjust a potential between the base and the emitter to provide a rapid turn-on voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Han/Hwang by forming the ESD protection device including the emitter electrically connected to the base as taught by Hwang to have the ESD protection structure, wherein the emitter and a base of the bipolar junction transistor are electrically connected to a first terminal, in order to adjust a potential between the base and the emitter to provide a rapid turn-on voltage, and thus to obtain the ESD protection device having high efficiency and faster control of turn-on operation (Hwang, ¶0047-¶0050, ¶0085, ¶0091).
Regarding claim 4, Han in view of Hwang discloses the ESD protection structure according to claim 3. Further, Han does not specifically disclose the ESD protection structure, wherein the first terminal is a power pad, and the second terminal is an input/output pad or a ground pad.
However, Han teaches that conventionally, the emitter is connected to the positive terminal (Vdd) (Han, ¶0008) and the collector is connected to the ground terminal for protection of an internal device from an electrostatic discharge. Further, Han teaches forming n-type deep well (175) (Han, Fig. 3, ¶0062) below the emitter region to increase a width of a base region, and thus to reduce a path resistance of a base current.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Han/Hwang by forming the ESD protection device including the n-type deep well below the p-type emitter that is electrically connected to the power pad as taught by Han to have the ESD protection structure, wherein the first terminal is a power pad, and the second terminal is an input/output pad or a ground pad, in order to provide ESD protection device with path resistance of a base current (Han, ¶0002, ¶0011, ¶0061-¶0062).
Regarding claim 6, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein the distance between the first p- type doped region (130) (Han, Fig. 3, ¶0046, ¶0061) and the edge of the first n-type well region (175) in the first horizontal direction is a distance between a bottom of the first p-type doped region (130) and the edge of the first n-type well region (175) in the first horizontal direction.
Regarding claim 7, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein an edge of the p-type well region (110) (Han, Fig. 3, ¶0061) is located under the first portion of the isolation structure (120) in the vertical direction.
Regarding claim 8, Han in view Hwang discloses the ESD protection structure according to claim 7. Further, Han discloses the ESD protection structure, wherein the edge of the first n-type well region (175) (Han, Fig. 3, ¶0062) is directly connected with the edge of the p-type well region (110).
Regarding claim 10, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein an area of the second p-type doped region (e.g., collector region 140/135/145 has greater area in the vertical direction than that of the emitter region 130) (Han, Fig. 3, ¶0048-¶0050, ¶0061) in the vertical direction is greater than an area of the first p-type doped region in the vertical direction.
Regarding claim 11, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein a bottom of the first p-type doped region (130) (Han, Fig. 3, ¶0061) is higher than a bottom of the first portion of the isolation structure (120) in the vertical direction.
Regarding claim 12, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein a bottom of the second p-type doped region (140) (Han, Fig. 3, ¶0061) is higher than a bottom of the first portion of the isolation structure (120) in the vertical direction.
Regarding claim 13, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein the first p-type doped region (130) is elongated in a second horizontal direction (e.g., the collector region 140 has a stripe shape along both sides of the emitter region or a ring shape surrounding the emitter region 130, and therefore the collector region 140 and the emitter 130 are elongated in a second horizontal direction) (Han, Fig. 3, ¶0014, ¶0050-¶0051), and the second p-type doped region (140) is elongated in the second horizontal direction.
Regarding claim 15, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein the p-type well region (110) (e.g., the collector region 140 formed on the p-well 110 has a ring shape surrounding the emitter region 130, and therefore, in a top view, the collector region 140 formed on the p-well 110 surrounds the emitter 130 on the first n-type well 175) surrounds the first n-type well region (175) (Han, Fig. 3, ¶0014, ¶0051, ¶0062) in a top view of the ESD protection structure.
Regarding claim 16, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein the isolation structure (120) surrounds the first p-type doped region (130) and the second p-type doped region (140) in a top view of the ESD protection structure (e.g., the collector region 140 has a ring shape surrounding the emitter region 130, and the base region 155 has a ring shape surrounding the collector region 140 and the emitter region 130, and therefore, in a top view, the isolation structure 120 between the base 155 and the collector region 140 surrounds the emitter 130 and the collector region 140) (Han, Fig. 3, ¶0014, ¶0051, ¶0055, ¶0061-¶0062).
Regarding claim 17, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, further comprising: a deep n-type well region (115) (Han, Fig. 3, ¶0061) disposed in the semiconductor substrate (105/110), wherein the first n-type well region (175) and the p-type well region (110) are located above the deep n-type well region (115) in the vertical direction.
Regarding claim 18, Han in view Hwang discloses the ESD protection structure according to claim 17. Further, Han discloses the ESD protection structure, further comprising: a second n-type well region (160) (Han, Fig. 3, ¶0061) disposed in the semiconductor substrate (105/110) and located above the deep n-type well region (115) in the vertical direction; and an n-type doped region (155) disposed in the second n-type well region (160), wherein a second portion of the isolation structure (120) is located between the second p-type doped region (140) and the n-type doped region (155) in the first horizontal direction.
Regarding claim 19, Han in view Hwang discloses the ESD protection structure according to claim 18. Further, Han discloses the ESD protection structure, wherein the second n-type well region (160) surrounds the first n-type well region (175) and the p-type well region (110) in a top view of the ESD protection structure (e.g., the collector region 140 has a ring shape surrounding the emitter region 130, and the base region 155 has a ring shape surrounding the collector region 140 and the emitter region 130, and therefore, in a top view, the second n-type well region including the base 155 surrounds the first n-type well region including the emitter 130 and the p-type well region including the collector region 140) (Han, Fig. 3, ¶0014, ¶0051, ¶0055, ¶0061-¶0062).
Regarding claim 20, Han in view Hwang discloses the ESD protection structure according to claim 1. Further, Han discloses the ESD protection structure, wherein the first portion of the isolation structure (120) (Han, Fig. 3, ¶0042, ¶0061-¶0062) is directly connected with the first p-type doped region (130), the second p-type doped region (140), the first n-type well region (175), and the p-type well region (110).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0082353 to Kuo in view of Hwang (US 2014/0367783).
Regarding claim 3, Kuo discloses the ESD protection structure according to claim 2. Further, Kuo does not specifically disclose that the emitter and a base of the bipolar junction transistor are electrically connected to a first terminal, and the collector of the bipolar junction transistor is electrically connected to a second terminal.
However, Hwang teaches forming the ESD protection structure, wherein the emitter and a base of the bipolar junction transistor (Hwang, Figs. 3A, 5, ¶0046, ¶0048, ¶0085-¶0091) are electrically connected (e.g., through a resistor 420) to a first terminal (e.g., a ground electrode), and wherein the resistor (420) serves to adjust a potential between the base and the emitter to provide a rapid turn-on voltage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Kuo by forming the ESD protection device including the emitter electrically connected to the base as taught by Hwang to have the ESD protection structure, wherein the emitter and a base of the bipolar junction transistor are electrically connected to a first terminal, and the collector of the bipolar junction transistor is electrically connected to a second terminal, in order to adjust a potential between the base and the emitter to provide a rapid turn-on voltage, and thus to obtain the ESD protection device having high efficiency and faster control of turn-on operation (Hwang, ¶0047-¶0050, ¶0085, ¶0091).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0082353 to Kuo in view of Hwang (US 2014/0367783) as applied to claim 3, and further in view of Han (US 2018/0082994).
Regarding claim 4, Kuo in view of Hwang discloses the ESD protection structure according to claim 3. Further, Kuo does not specifically disclose the ESD protection structure, wherein the first terminal is a power pad, and the second terminal is an input/output pad or a ground pad.
However, Han teaches that conventionally, the emitter is connected to the positive terminal (Vdd) (Han, ¶0008) and the collector is connected to the ground terminal for protection of an internal device from an electrostatic discharge. Further, Han teaches forming n-type deep well (175) (Han, Fig. 3, ¶0062) below the emitter region to increase a width of a base region, and thus to reduce a path resistance of a base current.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Kuo/Hwang by forming the ESD protection device including the n-type deep well below the p-type emitter that is electrically connected to the power pad as taught by Han to have the ESD protection structure, wherein the first terminal is a power pad, and the second terminal is an input/output pad or a ground pad, in order to provide ESD protection device with path resistance of a base current (Han, ¶0002, ¶0011, ¶0061-¶0062).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0082353 to Kuo.
Regarding claim 5, Kuo discloses the ESD protection structure according to claim 1. Further, Kuo does not specifically disclose the ESD protection structure, wherein the distance between the first p- type doped region and the edge of the first n-type well region in the first horizontal direction is equal to or less than 45 nanometers.
However, Kuo teaches forming an ESD protection device (Kuo, Figs. 2-4, 12, ¶0013, ¶0018-¶0037, ¶0046-¶0051) including a BJT device with small chip area consumption and adjustable device characteristics, wherein the first p- type doped region (e.g., the emitter region 260) (Kuo, Figs. 2-4, 12, ¶0027-¶0028, ¶0031-¶0033) is formed above the N-type well (220) including the base of the BJT, the second p- type doped region (e.g., the collector region 270/271) is formed above the P-type well (230/231) and the p-type doped regions (250/251) constituting a collector of the BJT, and an interface (290/291) is formed at the pn-junction between the N-type well (220) and the P-type well (230/231), Further, in Kuo, the distance (301/300) is set between the first p- type doped region (260) and the interface (290/291) or the edge of the N-type well (220), and the distance (310/311) is set between the p- type doped region (250/251) of the collector and the interface (290/291). The distances (300/301) and (310/311) are in a range between 0 to about 7 microns, and adjusted to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT (Kuo, Figs. 2-4, 12, ¶0032-¶0033).
Thus, Kuo recognizes that the distance between the first p- type doped region and the edge of the N-type well impacts device characteristics (e.g., a turn-on voltage, a breakdown voltage, and a holding voltage) of the BJT device. Thus, the distance between the first p- type doped region and the edge of the N-type well is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the distance between the first p- type doped region and the edge of the N-type well as Kuo has identified the distance between the first p- type doped region and the edge of the N-type well as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific distance between the first p- type doped region and the edge of the N-type well that is equal to or less than 45 nanometers in the first horizontal direction, in order to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT as taught by Kuo (¶0032-¶0033) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Kuo by optimizing a distance between p- type doped region and the edge of the N-type well of the BJT device as taught by Kuo to have the ESD protection structure, wherein the distance between the first p- type doped region and the edge of the first n-type well region in the first horizontal direction is equal to or less than 45 nanometers, in order to provide a BJT device with small chip area consumption and adjustable device characteristics (Kuo, ¶0013, ¶0032-¶0033, ¶0046-¶0048).
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0082994 to Han in view of Hwang (US 2014/0367783) as applied to claim 1, and further in view of Kuo (US 2013/0082353).
Regarding claim 5, Han in view of Hwang discloses the ESD protection structure according to claim 1. Further, Han does not specifically disclose the ESD protection structure, wherein the distance between the first p- type doped region and the edge of the first n-type well region in the first horizontal direction is equal to or less than 45 nanometers.
However, Kuo teaches forming an ESD protection device (Kuo, Figs. 2-4, 12, ¶0013, ¶0018-¶0037, ¶0046-¶0051) including a BJT device with small chip area consumption and adjustable device characteristics, wherein the first p- type doped region (e.g., the emitter region 260) (Kuo, Figs. 2-4, 12, ¶0027-¶0028, ¶0031-¶0033) is formed above the N-type well (220) including the base of the BJT, the second p- type doped region (e.g., the collector region 270/271) is formed above the P-type well (230/231) and the p-type doped regions (250/251) constituting a collector of the BJT, and an interface (290/291) is formed at the pn-junction between the N-type well (220) and the P-type well (230/231), Further, in Kuo, the distance (301/300) is set between the first p- type doped region (260) and the interface (290/291) or the edge of the N-type well (220), and the distance (310/311) is set between the p- type doped region (250/251) of the collector and the interface (290/291). The distances (300/301) and (310/311) are in a range between 0 to about 7 microns, and adjusted to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT (Kuo, Figs. 2-4, 12, ¶0032-¶0033).
Thus, Kuo recognizes that the distance between the first p- type doped region and the edge of the N-type well impacts device characteristics (e.g., a turn-on voltage, a breakdown voltage, and a holding voltage) of the BJT device. Thus, the distance between the first p- type doped region and the edge of the N-type well is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the distance between the first p- type doped region and the edge of the N-type well as Kuo has identified the distance between the first p- type doped region and the edge of the N-type well as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific distance between the first p- type doped region and the edge of the N-type well that is equal to or less than 45 nanometers in the first horizontal direction, in order to achieve a desired value for a turn-on voltage, a breakdown voltage, and a holding voltage of the BJT as taught by Kuo (¶0032-¶0033) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Han/Hwang by optimizing a distance between p- type doped region and the edge of the N-type well of the BJT device as taught by Kuo to have the ESD protection structure, wherein the distance between the first p- type doped region and the edge of the first n-type well region in the first horizontal direction is equal to or less than 45 nanometers, in order to provide a BJT device with small chip area consumption and adjustable device characteristics (Kuo, ¶0013, ¶0032-¶0033, ¶0046-¶0048).
Regarding claim 14, Han in view of Hwang discloses the ESD protection structure according to claim 13. Further, Han does not specifically disclose the ESD protection structure, wherein the second horizontal direction is orthogonal to the first horizontal direction.
However, Han teaches that the collector region (140) has a stripe shape along both sides of the emitter region (130) or a ring shape surrounding the emitter region (130), and thus the collector region (140) and the emitter (130) are elongated in a second horizontal direction (Han, Fig. 3, ¶0014, ¶0050-¶0051).
Further, Kuo teaches forming an ESD protection device (Kuo, Figs. 2-3, 12, ¶0013, ¶0018-¶0035, ¶0046-¶0051) including a BJT device with small chip area consumption and adjustable device characteristics, wherein the collector region (270) is separated from the emitter region (260) by the isolation portion (281) in a first horizontal direction, and in a top view, the collector region (270) has a stripe shape along both sides of the emitter region (260) elongated in the second horizontal direction that is orthogonal to the first horizontal direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Han/Hwang by forming a BJT device including the collector region and the emitter region having a stripe shape or rectangular ring shape as taught by Kuo to have the ESD protection structure, wherein the second horizontal direction is orthogonal to the first horizontal direction, in order to provide a BJT device with small chip area consumption and adjustable device characteristics (Kuo, ¶0013, ¶0033, ¶0046-¶0048).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0082353 to Kuo in view of Han (US 2018/0082994).
Regarding claims 18 and 19, Kuo discloses the ESD protection structure according to claim 17. Further, Kuo does not specifically disclose the ESD protection structure, further comprising: a second n-type well region disposed in the semiconductor substrate and located above the deep n-type well region in the vertical direction; and an n-type doped region disposed in the second n-type well region, wherein a second portion of the isolation structure is located between the second p-type doped region and the n-type doped region in the first horizontal direction (as clamed in claim 18); wherein the second n-type well region surrounds the first n-type well region and the p-type well region in a top view of the ESD protection structure (as clamed in claim 19).
However, Han teaches forming the ESD protection structure, further comprising: a second n-type well region (160) (Han, Fig. 3, ¶0055, ¶0061) disposed in the semiconductor substrate (105/110) and located above the deep n-type well region (115) in the vertical direction; and an n-type doped region (155) disposed in the second n-type well region (160), wherein a second portion of the isolation structure (120) is located between the second p-type doped region (140) and the n-type doped region (155) in the first horizontal direction, wherein the second n-type well region (160) has a ring shape to enlarge the area of the base (155) resulting in higher maintenance voltage for ESD protection device (Han, Fig. 3, ¶0055); wherein the second n-type well region (160) surrounds the first n-type well region (175) and the p-type well region (110) in a top view of the ESD protection structure (e.g., the collector region 140 has a ring shape surrounding the emitter region 130, and the base region 155 has a ring shape surrounding the collector region 140 and the emitter region 130, and therefore, in a top view, the second n-type well region including the base 155 surrounds the first n-type well region including the emitter 130 and the p-type well region including the collector region 140) (Han, Fig. 3, ¶0014, ¶0051, ¶0055, ¶0061-¶0062).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the ESD protection device of Kuo by forming the ESD protection device including a second n-type well region as taught by Han to have the ESD protection structure, further comprising: a second n-type well region disposed in the semiconductor substrate and located above the deep n-type well region in the vertical direction; and an n-type doped region disposed in the second n-type well region, wherein a second portion of the isolation structure is located between the second p-type doped region and the n-type doped region in the first horizontal direction (as clamed in claim 18); wherein the second n-type well region surrounds the first n-type well region and the p-type well region in a top view of the ESD protection structure (as clamed in claim 19), in order to enlarge the area of the base to have higher maintenance voltage for ESD protection device, and thus to obtain improved ESD protection device (Han, ¶0002, ¶0011, ¶0055, ¶0061-¶0062).
Response to Arguments
Applicant's arguments filed 11/18/2025 have been fully considered but they are not persuasive.
In response to Applicant's arguments that “[H]wang does not disclose the area of the N+ emitter region 307 (alleged first p-type doped region). The area of the emitter region 308 is apparently not equal to the area of the N+ emitter region 307” and “[H]wang discloses that the area of the active region of the collector region 302 should be sufficiently large, but that does not mean that the area of the collector region 302 has to be greater than the area of the N+ emitter region 307”, the examiner submits that the reference character “307” of Hwang is used to designate “the emitter region” (see paragraphs [0052], [0054]-[0057], [0060]-[0061), [0071], [0078]). Thus, the reference character “308” for the area of the emitter region in paragraph [0111] of Hwang should be interpreted as “307” because the reference character “308” of Hwang is used to designate a contact for the emitter region (307), as shown in Figs. 3A and 4 of Hwang. Further, Hwang teaches that the area of the active region of the collector region (302) and a length of the shorter size of the collector region (302), which is indicated by "a-1" in Fig. 3B (Hwang, Figs. 3A-3B, 5, ¶0079, ¶0111), should be sufficiently large such that current crowding is not generated. This is for preventing current crowding in a narrow region, when stress flows into the collector region 302 of the BJT (Hwang, Figs. 3A, 5, ¶0079). Thus, a person of ordinary skill in the art would be motivated to form the collector region with increased length (e.g., a-1) of a shorter size of the collector region to prevent current crowding in a narrow region (Hwang, Figs. 3A, 5, ¶0079). Therefore, the above applicant’s arguments are not persuasive, and the rejection of claim 1 under 35 USC 103 over Han in view Hwang is maintained.
In response to Applicant's arguments that “[K]uo does not disclose the area relationship between the heavily doped region 260 (alleged first p-type doped region) and the heavily doped region 270/doped region 250 (alleged second p-type doped region) and/or the length relationship between the heavily doped region 260 and the heavily doped region 270/doped region 250, the examiner submits that Ku teaches that “the heavily doped region 260” and “the heavily doped region 270” are formed between the isolation regions (280/281) (Kuo, Fig. 3) having an inverse trapezoidal shape with a dimension of an upper portion greater than that of the bottom portion, such that the doped region (250) of the collector region (270/250, interpreted as the second p-type doped region) adjacent to the bottom portion of the isolation regions (280/281) would have a length greater than a length of the emitter region (260, interpreted as the first p-type doped region) adjacent to the top portion of the isolation regions (281/282).
Therefore, the above applicant’s arguments are not persuasive, and the rejection of claim 1 under 35 USC 102 to Kuo is maintained.
Regarding dependent claims 2-8 and 10-20 which depend on the independent claim 1, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891