DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Objections 3
III. Claim Rejections - 35 USC § 112 3
A. Claims 1-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 3
IV. Claim Rejections - 35 USC § 102 4
A. Claims 1-3, 5-7, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0197603 (“Chen”). 5
V. Claim Rejections - 35 USC § 103 11
A. Claims 1-3, 5-9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0098292 (“Nguyen”) in view of US 2010/0093168 (“Naik”). 11
B. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Naik, as applied to claims 1 and 3 above, and further in view of US 2024/0038528 (“Cheng”). 20
C. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Naik, as applied to claims 1 and 9 above, and further in view of US 2021/0305087 (“Parikh”). 21
VI. Response to Arguments 23
Conclusion 24
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Objections
Claims 1 and 5 are objected to because of the following informalities:
(1) In line 24 of claim 1, replace “thereat” with “thereover” for clarity.
(2) In line 24 of claim 1, after “second dielectric liner”, insert “portion” to provide proper antecedent basis in the claim.
(3) In line 3 of claim 5, after “second dielectric liner”, insert “portion” to provide proper antecedent basis in the claim.
Appropriate correction is required.
III. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 1-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites the limitations in lines 18-20 and 22-24, respectively:
wherein the first dielectric liner portion is disposed in the first opening and in contact between the first interconnect structure and the third interconnect structure
wherein the second dielectric liner portion is disposed in the second opening and in contact between the fourth interconnect structure and the second interconnect structure,
It is unclear what is meant by “in contact” in the context of the claim. It is unclear as to what the first and second dielectric liner portions are “in contact between …” the respective openings. In the alternative, the inventor or joint inventor may mean that the liner portions extend continuously between the respective first and third, and second and fourth interconnect structures.
Claims 2-11 are rejected for including the same indefinite feature by depending from claim 1.
For the purposes of examination, the latter interpretation, above, will be presumed in the claim, i.e. that the liner portions extend continuously between the respective first and third, and second and fourth interconnect structures, as this is consistent with the elected species shown in Fig. 1.
IV. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-3, 5-7, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0197603 (“Chen”).
With regard to claim 1, Chen discloses, in Fig. 1A-1D and 2,
1. (currently amended): A semiconductor device structure, comprising:
[1] a first dielectric layer 103 [¶ 13] disposed over a semiconductor substrate 101/106 [¶¶ 12, 13];
[2] a second dielectric layer 104 [¶ 14] disposed over the first dielectric layer 103;
[3] a first interconnect structure 115e and a second interconnect structure 115b disposed on a top surface of the second dielectric layer 104 [¶ 15; see annotated Fig. 2, below];
[4] a third interconnect structure 120a disposed on the top surface of the second dielectric layer 104 between the first interconnect structure 115e and the second interconnect structure 115b [see annotated Fig. 2, below];
[5] a fourth interconnect structure 115a disposed on the top surface of the second dielectric layer 104 between the third interconnect structure 120a and the second interconnect structure 115b [see annotated Fig. 2, below],
[6] wherein the third interconnect structure 102a and the fourth interconnect structure 115a are disposed between the first interconnect structure 115e and the second interconnect structure 115b [see annotated Fig. 2, below];
[7a] a first opening formed between the first interconnect structure 115e and the third interconnect structure 120a [first opening is not shown in Fig. 1A but is equivalent to the opening between, e.g., 115b and 120b in which liner material 125 and air gap 135 are formed],
[7b] wherein the top surface of the second dielectric layer 104 is exposed through the first opening;
[8a] a second opening formed between the fourth interconnect structure 115a and the second interconnect structure 115b [second opening is shown in Fig. 1A but not labeled and is between, e.g., 115a and 115b in which liner material 125 and air gaps 135 are formed],
[8b] wherein the top surface of the second dielectric layer 105 is exposed through the second opening;
[9a] a first dielectric liner portion [at least portion of “spacer material 125” (¶ 16) between and on sidewalls of 115e and 120a in Fig. 2, “125e”, hereafter] disposed adjacent to the first interconnect structure 115e,
[9b] wherein an air gap 135 [¶ 16] is enclosed in the first dielectric liner portion 125e,
[9c] wherein the first dielectric liner portion 125e is disposed in the first opening and in contact between the first interconnect structure 115e and the third interconnect structure 120a [as shown in Fig. 2 taken with Fig. 1A];
[10a] a second dielectric liner portion [at least portion of “spacer material 125” (¶ 16) on sidewalls of 115a and 115b in Fig. 2, which extends on the surface of the dielectric layer 104 between 115a and 115b as shown in Fig. 1A; see annotated Fig. 2 below] disposed adjacent to the second interconnect structure 115b,
[10b] wherein the second dielectric liner portion is disposed in the second opening and in contact between the fourth interconnect structure 115a and the second interconnect structure 115b [see annotated Fig. 2 below],
[10c] wherein the second dielectric liner [portion] 125b has a U-shaped cross section and forms a third opening thereat [third opening is as noted in annotated Fig. 2, below, and is equivalent to the rightmost portion of 125 in Fig. 1A in which “material section 130 of low-k material” (¶ 21) is formed; see explanation below]; and
[11] a filling portion 130 [¶ 21] disposed within the third opening, and surrounded by the second dielectric liner portion [again, at least portion of “spacer material 125” (¶ 16) on sidewalls of 115a and 115b in Fig. 2, which extends on the surface of the dielectric layer 104 between 115a and 115b as shown in Fig. 1A; see annotated Fig. 2 below];
[12] wherein a top surface of the first interconnect structure 115a, a top surface of the second interconnect structure 115b, a top surface of the first dielectric liner portion [portion of 125 to left of 115a], a top surface of the second dielectric liner portion [portion of 125 to the right of 115b], and a top surface of the filling portion 130 are coplanar with each other;
[13] wherein the air gap 135 is enclosed below the top surface of the first dielectric liner portion [portion of 125 to the left of 115a];
[14] wherein the air gap 135 is positioned below the top surface of the first interconnect structure 115a;
[15] wherein a width of the first opening [i.e. between 115e and 120a] is less than a width of the second opening [i.e. between 115a and 115b].
With regard to features [10c] and [11] of claim 1,
[10c] wherein the second dielectric liner 125b has a U-shaped cross section and forms a third opening thereat [third opening is as noted in annotated Fig. 2, below, and is equivalent to the rightmost portion of 125 in Fig. 1A in which “material section 130 of low-k material” (¶ 21) is formed; see explanation below]; and
[11] a filling portion 130 [¶ 21] disposed within the third opening, and surrounded by the second dielectric liner portion [again, at least portion of “spacer material 125” (¶ 16) on sidewalls of 115a and 115b in Fig. 2, which extends on the surface of the dielectric layer 104 between 115a and 115b as shown in Fig. 1A; see annotated Fig. 2 below];
As shown in annotated Fig. 2, taken with Fig. 1A, the liner material 125 extends continuously between the “second interconnect structure” 115a and the “fourth interconnect structure” 115b and would therefore form a complete U shape, like the portion of the U-shape shown at the rightmost side of Fig. 1A, in which the “material section 130 of low-k material” (¶ 21) is formed.
Note that instant claim 1 is only taken from the cross section shown in, e.g., the elected species 100a shown in instant Fig. 1 of the Instant Application, and there is no requirement that there be no other interconnect structure between the entirety of the claimed second and fourth interconnect structures.
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(Annotated Fig. 2 of Chen)
This is all of the features of claim 1.
With regard to claim 2, Chen further discloses,
2. (currently amended): The semiconductor device structure of claim 1, further comprising:
[1] a third dielectric liner portion [portion of 125] disposed on the second dielectric layer 104 and between the third interconnect structure 120a and the fourth interconnect structure 115a [as shown in Figs. 1A and annotated Fig. 2];
[2] wherein a bottom width of the second dielectric liner portion [i.e. portion of 125 extending between 115a and 115b at the cross-section denoted in annotated Fig. 2] is greater than a bottom width of the first dielectric liner portion 125e [i.e. the portion of 125 extending between 115e and 120a, which are directly adjacent as shown in annotated Fig. 2 (supra)];
[3] wherein the bottom width of the first dielectric liner portion 125e is equal to a width of the first opening [first opening is not shown in Fig. 1A but is equivalent to the opening between, e.g., 115b and 120b in which liner material 125 and air gap 135 are formed] while the bottom width of the second dielectric liner portion is equal to a width of the second opening [second opening is shown in Fig. 1A but not labeled and is between, e.g., 115a and 115b in which liner material 125 and air gaps 135 are formed; see annotated Fig. 2, above].
With regard to claim 3, Chen further discloses,
3. (previously presented): The semiconductor device structure of claim 1,
[1] wherein a material of the first dielectric liner portion is the same as a material of the second dielectric liner portion [because the “spacer material 125” forms all of the liner portions],
[2] wherein the first dielectric liner portion [at least portion of “spacer material 125” (¶ 16) between and on sidewalls of 115e and 120a in Fig. 2, “125e”, hereafter] and the second dielectric liner portion [at least portion of “spacer material 125” (¶ 16) on sidewalls of 115a and 115b in Fig. 2, which extends on the surface of the dielectric layer 104 between 115a and 115b as shown in Fig. 1A; see annotated Fig. 2 above] are two separated portions and are not connected with each other [at least in the cross-sectional view of the “second opening” denoted in annotated Fig. 2 and in Fig. 1A].
Note that the Instant Application only shows a cross-section; therefore, there is not requirement for a lack of connection between the claims first and second dielectric liner portions than in a cross section because there is no support for anything other than a cross section in the Instant Application.
With regard to claims 5, 6, 7, and 11, Chen further discloses,
5. (currently amended): The semiconductor device structure of claim 1,
[1] wherein the filling portion 130 is separated from the second dielectric layer 104 by the second dielectric liner portion [at least portion of “spacer material 125” (¶ 16) on sidewalls of 115a and 115b at the location of the “second opening” in annotated Fig. 2, above, which extends on the surface of the dielectric layer 104 between 115a and 115b as shown in Fig. 1A],
[2] wherein the second dielectric liner [portion] is in contact with two sidewalls and a bottom wall of the second opening [again at the cross section noted in annotated Fig. 2, above],
[3] wherein the two sidewalls of the second opening are defined at the fourth interconnect structure 115a and the second interconnect structure 115b respectively [as shown in Fig. 1A, taken with annotated Fig. 2]
[4] while the bottom wall of the second opening is defined on the top surface of the second dielectric layer 104 [as shown in Fig. 1A, taken with annotated Fig. 2].
6. (original): The semiconductor device structure of claim 5, wherein the filling portion 130 is separated from the second interconnect structure 115b by the second dielectric liner portion [at least portion of “spacer material 125” (¶ 16) on sidewalls of 115a and 115b at the location of the “second opening” in annotated Fig. 2, above, which extends on the surface of the dielectric layer 104 between 115a and 115b as shown in Fig. 1A].
7. (previously presented): The semiconductor device structure of claim 1, further comprising: a cover layer 140 [¶ 14] disposed over and in direct contact with the top surface of the first interconnect structure 115e, the top surface of the second interconnect structure 115b, the top surface of the first dielectric liner portion [i.e. all liner portions 125], the top surface of the second dielectric liner portion [i.e. all liner portions 125], and the top surface of the filling portion 130.
11. (original): The semiconductor device structure of claim 1, wherein the filling portion includes a low-k dielectric material 130 [¶ 21].
V. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 5-9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0098292 (“Nguyen”) in view of US 2010/0093168 (“Naik”).
Claim 1 reads,
1. (currently amended): A semiconductor device structure, comprising:
[1] a first dielectric layer disposed over a semiconductor substrate;
[2] a second dielectric layer disposed over the first dielectric layer;
[3] a first interconnect structure and a second interconnect structure disposed on a top surface of the second dielectric layer;
[4] a third interconnect structure disposed on the top surface of the second dielectric layer between the first interconnect structure and the second interconnect structure;
[5] a fourth interconnect structure disposed on the top surface of the second dielectric layer between the third interconnect structure and the second interconnect structure,
[6] wherein the third interconnect structure and the fourth interconnect structure are disposed between the first interconnect structure and the second interconnect structure;
[7a] a first opening formed between the first interconnect structure and the third interconnect structure,
[7b] wherein the top surface of the second dielectric layer is exposed through the first opening;
[8a] a second opening formed between the fourth interconnect structure and the second interconnect structure,
[8b] wherein the top surface of the second dielectric layer is exposed through the second opening;
[4] [9a] a first dielectric liner portion disposed adjacent to the first interconnect structure,
[9b] wherein an air gap is enclosed in the first dielectric liner portion,
[9c] wherein the first dielectric liner portion is disposed in the first opening and in contact between the first interconnect structure and the third interconnect structure;
[5] [10a] a second dielectric liner portion disposed adjacent to the second interconnect structure,
[10b] wherein the second dielectric liner portion is disposed in the second opening and in contact between the fourth interconnect structure and the second interconnect structure,
[10c] wherein the second dielectric liner [portion] has a U-shaped cross section and forms a third opening thereat; and
[6] [11] a filling portion disposed within the third opening, and surrounded by the second dielectric liner portion;
[7] [12] wherein a top surface of the first interconnect structure, a top surface of the second interconnect structure, a top surface of the first dielectric liner portion, a top surface of the second dielectric liner portion, and a top surface of the filling portion are coplanar with each other;
[8] [13] wherein the air gap is enclosed below the top surface of the first dielectric liner portion;
[9] [14] wherein the air gap is positioned below the top surface of the first interconnect structure;
[10] [15] wherein a width of the first opening is less than a width of the second opening.
With regard to claim 1, Nguyen discloses, generally in Fig. 10,
1. (currently amended) A semiconductor device structure, comprising:
[1] a first dielectric layer [pre-metal dielectric (PMD) of FEOL/MOL layer 104 (¶ 21)] disposed over a semiconductor substrate 102 [¶ 19];
[2] a second dielectric layer 106 [¶ 22] disposed over the first dielectric layer [PMD of 104];
[3] a first interconnect structure 114A [¶ 26] and a second interconnect structure 114E disposed on a top surface of the second dielectric layer 106;
[4] a third interconnect structure 114B disposed on the top surface of the second dielectric layer 106 between the first interconnect structure 114A and the second interconnect structure 114E;
[5] a fourth interconnect structure 114D disposed on the top surface of the second dielectric layer 106 between the third interconnect structure 114B and the second interconnect structure 114E,
[6] wherein the third interconnect structure 114B and the fourth interconnect structure 114D are disposed between the first interconnect structure 114A and the second interconnect structure 114E;
[7a] a first opening [not labeled] formed between the first interconnect structure 114A and the third interconnect structure 114B,
[7b] wherein the top surface of the second dielectric layer 106 is exposed through the first opening;
[8a] a second opening [not labeled] formed between the fourth interconnect structure 114D and the second interconnect structure 114E,
[8b] wherein the top surface of the second dielectric layer 106 is exposed through the second opening;
[9a] a first dielectric liner portion [¶ 28; portion of 116' including pinch off 124 (¶ 37) between 114A and 114B] disposed adjacent to the first interconnect structure 114A,
[9b] wherein an air gap 126 [¶ 37] is enclosed in the first dielectric liner portion 116',
[9c] wherein the first dielectric liner portion is disposed in the first opening and in contact between the first interconnect structure 114A and the third interconnect structure 114B;
[10a] a second dielectric liner portion [¶ 28; portion of 116' between 114D and 114E] disposed adjacent to the second interconnect structure 114E,
[10b] wherein the second dielectric liner portion is disposed in the second opening and in contact between the fourth interconnect structure 114D and the second interconnect structure 114E,
[10c] wherein the second dielectric liner [portion] has a U-shaped cross section and forms a third opening thereat; and
[11] a filling portion 118 [¶ 33] disposed within the third opening, and surrounded by the second dielectric liner portion [i.e. portion of 116' between 114D and 114E],
[12] … [not taught] …
[13] wherein the air gap 126 is enclosed below the top surface of the first dielectric liner portion [portion of 116' including pinch off 124 (¶ 37) between 114A and 114B];
[14] wherein the air gap 126 is positioned below the top surface of the first interconnect structure [e.g. 114A];
[15] wherein a width of the first opening [i.e. between 114A and 114B] is less than a width of the second opening [i.e. between 114D and 114E] [see explanation below].
With regard to feature [9] of claim 1, there is no claim language requiring that the entirety of the air gap be “positioned below the top surface of the first interconnect structure”. Fig. 10 of Nguyen shows the virtually the entirety of the air gap 126 is positioned below the top surface of the first interconnect structure, e.g. 114A. And even if claim 1 were amended to require that the entirety of the air gap be positioned below the top surface of the first interconnect structure, Nguyen modified according to Naik teaches this (infra).
With regard to feature [15] of claim 1, although not apparent from Fig. 10, “a width of the first opening [i.e. between 114A and 114B] is less than a width of the second opening [i.e. between 114D and 114E]”. In this regard, Nguyen states the following:
It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations that are not drawn to scale.
(Nguyen: ¶ 16; emphasis added)
[0037] In another illustrative embodiment, an air-gap integration process can be implemented to form air gaps between closely spaced metal lines 114A-114E. For example, with reference to FIG. 10, the semiconductor structure 300 includes a barrier 116′ having additional layers formed in accordance with the process outlined in FIGS. 1-7 to provide a thicker barrier 116′. In one methodology, the ILD layer 118 may be deposited over the semiconductor structure 300 shown in FIG. 10 using a non-conformal deposition process (e.g., chemical vapor deposition (CVD) or Plasma-enhanced chemical vapor deposition (PECVD), which results in the formation of “pinch-off” regions 124 in the layer of dielectric material [i.e. barrier 116'] above the small spaces between closely spaced metal lines 114A-114E. The wider spaces between the metal lines 114A-114E will be filled. The pinch-off regions 124 substantially prevent inflow of the subsequently applied dielectric liner [i.e. barrier 116'] thereby providing air gaps 126 between the adjacent metal lines 114A-114E as separated by the barrier layers 116′.
(Nguyen: ¶ 37; emphasis added)
Thus, although not apparent in Fig. 10 that the first opening between 114A and 114B is less than the width between the second opening between 114D and 114E, Nguyen states that the drawings are not to scale. Therefore, recourse is to the disclosure in Nguyen. Because the first opening between 114A and 114B is pinched off with an air gap 126 while the second opening between 114D and 114E is filled with dielectric fill 118 it is necessarily inherently the case that the “a width of the first opening [i.e. between 114A and 114B] is less than a width of the second opening [i.e. between 114D and 114E]”, as explained in Nguyen (¶ 37, supra). As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to feature [12] of claim 1, and claims 7 and 8,
[12] wherein a top surface of the first interconnect structure, a top surface of the second interconnect structure, a top surface of the first dielectric liner portion, a top surface of the second dielectric liner portion, and a top surface of the filling portion are coplanar with each other;
7. (previously presented): The semiconductor device structure of claim 1, further comprising: a cover layer disposed over and in direct contact with the top surface of the first interconnect structure, the top surface of the second interconnect structure, the top surface of the first dielectric liner portion, the top surface of the second dielectric liner portion, and the top surface of the filling portion.
8. (original): The semiconductor device structure of claim 7, wherein the cover layer includes silicon nitride (Si3N4), silicon oxynitride (SiON), silicon dioxide (SiO2), or carbonitride.
Nguyen does not disclose the configuration required by feature [12] of claim 1 and claims 7 and 8.
Naik, like Nguyen, teaches a metallization structure (Naik: Figs. 4G, 6A) including spaced metal lines 405, which may be Cu, Al, W (¶ 43) in a dielectric layer 415(417) in which the air gaps 408 are enclosed by pinching of the dielectric 415(417) (Naik: Figs. 4E-4G; ¶¶ 67-69). Fig. 6A of Naik further shows the structure of Fig. 4G after planarizing to expose the metal lines 405 (Naik: ¶ 76). After the planarization step, the top surfaces of each of the metal lines 405 and the dielectric portions 415(417) between each of the metal lines 405 are coplanar—as required by feature [12] of claim 1—thereby making a planar surface on which a capping layer 616 is deposited, which is a “second metal barrier liner 216” (Naik: ¶ 77; Fig. 6C), which may be made of silicon nitride or silicon dioxide—as required by claim 8 (Naik: ¶ 71). The “second metal barrier liner 216” directly contacts each of the underlying dielectric portions 417 having the air gaps as well as the top surfaces of the metal lines 405, as shown in Fig. 6C of Naik. After depositing the “second metal barrier liner 216”, Naik forms an overlying “second level interconnect” including ILD layers 641 through 645 (Naik: ¶ 79; Fig. 6E) connected to the underlying metal lines 405, which is shown in Figs. 8A-8I (Naik: ¶ 85).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, (1) to planarize the metallization structure shown in Fig. 10 of Nguyen, thereby planarizing each of the barrier 116' and ILD layer 118 of to expose the top surfaces of the metal lines 114A-114E, as taught in Fig. 6B of Naik, and then (2) to form a capping layer 616 (of Naik), i.e. the second metal barrier liner of silicon oxide or silicon nitride of Naik, covering the planarized surface, thereby directly contacting the top surfaces of each of the barrier 116', the ILD layer 118, and the metal lines 114A-114E, in order to (1) form a barrier surrounding each of the metal lines 114A-114E, and (2) prepare the metal level shown in Fig. 10 of Nguyen for forming a second, overlying level of interconnect, as taught by Naik (supra).
In order to preserve the air gaps 126 within the barrier 116' after the planarization step of Naik, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, in addition, to form the pinch-off region 124 such that the bottom surface of the barrier 116' over the air gap 126 is sufficiently below the top surface of the metal lines 405, as taught in Naik at Figs. 6A and 8A.
So modified, Nguyen in view of Naik teaches,
[12] wherein a top surface of the first interconnect structure [e.g. 114A of Nguyen],
a top surface of the second interconnect structure [e.g. 114C of Nguyen],
a top surface of the first dielectric liner portion [e.g. portion of 116' including pinch off 124 (¶ 37) between 114A and 114B of Nguyen],
a top surface of the second dielectric liner portion [e.g. portion of 116' between 114B and 114C of Nguyen], and
a top surface of the filling portion [118 of Nguyen]
are coplanar with each other [by the planarization taught in Naik, as shown in Fig. 6B of Naik]
7. (previously presented) The semiconductor device structure of claim 1, further comprising: a cover layer [616 of Naik] disposed over and in direct contact with
the top surface of the first interconnect structure [114A of Nguyen],
the top surface of the second interconnect structure [114C of Nguyen],
the top surface of the first dielectric liner portion [i.e. portion of 116' including pinch off 124 (¶ 37) between 114A and 114B of Nguyen],
the top surface of the second dielectric liner portion [i.e. portion of 116' between 114B and 114C of Nguyen], and
the top surface of the filling portion [118 of Nguyen].
8. (original): The semiconductor device structure of claim 7, wherein the cover layer [616 of Naik used in Nguyen] includes silicon nitride (Si3N4), silicon oxynitride (SiON), silicon dioxide (SiO2), or carbonitride [Naik: ¶ 71].
This is all of the limitations of claims 1, 7, and 8.
With regard to claim 2, Nguyen further discloses,
2. (currently amended): The semiconductor device structure of claim 1, further comprising:
[1] a third dielectric liner portion [portion of 116' between 114B and 114D] disposed on the second dielectric layer 106 and between the third interconnect structure 114B and the fourth interconnect structure 114D;
[2] wherein a bottom width of the second dielectric liner portion [i.e. the portion of 116' between 114D and 114E] is greater than a bottom width of the first dielectric liner portion [i.e. the portion of 116' between 114A and 114B] [as explained above];
[3] wherein the bottom width of the first dielectric liner portion [i.e. the portion of 116' between 114A and 114B] is equal to a width of the first opening while the bottom width of the second dielectric liner portion [i.e. the portion of 116' between 114D and 114E] is equal to a width of the second opening [as shown in Fig. 10].
With regard to feature [2] of claim 2, for the same reason as explained under feature [15] of claim 1, it is held, absent evidence to the contrary, that “the bottom width of the first dielectric liner portion [i.e. the portion of 116' between 114A and 114B] is equal to a width of the first opening while the bottom width of the second dielectric liner portion [i.e. the portion of 116' between 114D and 114E] is equal to a width of the second opening”. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
This is all of the limitations of claim 2.
With regard to claim 3, Nguyen modified according to Naik as explained under claim 1 further teaches,
Claim 3 (previously presented): The semiconductor device structure of claim 1,
[1] wherein a material of the first dielectric liner portion [e.g. portion of 116' between 114A and 114B] is the same as a material of the second dielectric liner portion [e.g. portion of 116' between 114D and 114E],
[2] wherein the first dielectric liner portion [e.g. portion of 116' between 114A and 114B] and the second dielectric liner portion [e.g. portion of 116' between 114D and 114E] are two separated portions and are not connected with each other [because the planarization process of Naik which isolates the liner 116' portions between the interconnect structures 114A-E of Nguyen].
With regard to claims 5, 6, 9, and 11, Nguyen further discloses,
5. (currently amended): The semiconductor device structure of claim 1,
[1] wherein the filling portion 118 is separated from the second dielectric layer 106 by the second dielectric liner portion [i.e. portion of 116' between 114D and 114E],
[2] wherein the second dielectric liner [portion] is in contact with two sidewalls and a bottom wall of the second opening [between 114D and 114E],
[3] wherein the two sidewalls of the second opening are defined at the fourth interconnect structure 114D and the second interconnect structure 114E respectively
[4] while the bottom wall of the second opening is defined on the top surface of the second dielectric layer 106 [as shown in Fig. 10].
6. (original) The semiconductor device structure of claim 5, wherein the filling portion 118 is separated from the second interconnect structure 114B or 114C by the second dielectric liner portion [i.e. portion of 116' between 114B and 114C].
9. (previously presented): The semiconductor device structure of claim 1, wherein each of the first interconnect structure 114A, the second interconnect structure 114E, the third interconnect structure 114B, and the fourth interconnect structure 114D comprises
[1] a first conductive layer [i.e. “metallic liners and/or adhesion layers” e.g. Ta, TaN, TiN (Nguyen: ¶ 26)] disposed on the second dielectric layer 106 and
[2] a second conductive layer [i.e. metal fill, e.g. Cu, Co, Al, W, Ru (¶ 26)] disposed on the first conductive layer [because “[t]hese liners and or adhesives may be deposited or grown in the openings 110-1 to 110-5 prior to the metallization process.” (Nguyen: ¶ 26, last sentence)]
[3] wherein the first opening [between 114A and 114B] and the second opening [between 114D and 114E] are penetrated through the first conductive layer and the second conductive layer to expose the top surface of the second dielectric layer 106 [as shown in Fig. 10].
11. (original) The semiconductor device structure of claim 1, wherein the filling portion 118 includes a low-k dielectric material [Nguyen: ¶ 33].
B. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Naik, as applied to claims 1 and 3 above, and further in view of US 2024/0038528 (“Cheng”).
Claim 4 reads,
4. (original) The semiconductor device structure of claim 3, wherein the material of the first dielectric liner portion and the material of the second dielectric liner portion include boron carbonitride (BCN).
The prior art of Nguyen in view of Naik, as explained above, teaches each of the features of claims 1 and 3.
Nguyen further teaches that the material of the first dielectric liner 116' can be SiCN but does not teach BCN.
Cheng, like Nguyen, teaches a metallization structure (Cheng: Fig. 12) including metallic liner 40', e.g. Ta, TaN (Cheng: ¶ 34) and a metal fill 50', e.g. , Cu, Co, Ru, W, Al (Cheng: ¶ 37) having air gaps 80 between the metallization structures (Cheng: ¶ 48). Also like Nguyen (at ¶ 28), Cheng teaches that the dielectric layer 20 in which the air gaps 80 are formed can be made of SiCN (Cheng: ¶ 30). Cheng further teaches that the dielectric layer 20 can be BCN (Cheng: ¶ 30).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the dielectric layer 116' of Nguyen from BCN because Cheng teaches that each of SiCN and BCN are suitable for a dielectric material formed between metallization structures in which air gaps are to formed, such that the substitution of SiCN for BCN would be the substitution of one known dielectric material for another, known to be suitable for the same purpose of enclosing air gaps in the dielectric formed between metallization structures. As such, the selection of BCN amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claim 4.
C. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Naik, as applied to claims 1 and 9 above, and further in view of US 2021/0305087 (“Parikh”).
Claim 10 reads,
10. (previously presented): The semiconductor device structure of claim 9, wherein
[1] the first liner portion is in direct contact with the first conductive layer and the second conductive layer of the first interconnect structure, and
[2] the second liner portion is in direct contact with the first conductive layer and the second conductive layer of the second interconnect structure,
[3] wherein the first conductive layer and the second conductive layer are made of different materials.
The prior art of Nguyen in view of Naik, as explained above, teaches each of the features of claims 1 and 9.
Nguyen does not provide the details of the configuration of the “metallic liners and/or adhesion layers” e.g. Ta, TaN, TiN, and subsequently deposited metallization, e.g. Cu, Co, Al, W, Ru (Nguyen: ¶ 26) and does not therefore teach a stacked configuration such that the first and second liner portions 116' contact each of the liner/adhesion and the metallization.
Parikh, like Nguyen, teaches a metallization structure including metal lines 203 having air gaps 231 in a dielectric 230 between sufficiently closely spaced metal lines 203 (Parikh: Figs. 6A-6D. Also like Nguyen, the metal lines 203 of Parikh include an adhesion layer 245 and a “stack metal” 250 of e.g. Cu, Co, Al, W, Ru (Parikh: ¶ 48). Parikh further teaches that the adhesion layer and the stack metal 250 are vertically stacked, such that the sidewalls of each contact the adjacent liner 240 (Parikh: ¶¶ 48-49; Figs. 6A-6D).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the metal lines 114A-114E of Nguyen to have a vertically stacked configuration taught in Parikh (Figs. 6A-6D) including the adhesion layer 245 and an overlying stack metal 250, because Nguyen is silent as to the configuration of the layers of the metal lines 114A-114E, such that one having ordinary skill in the art would use known configurations, such as those taught in Parikh. (See MPEP 2143.)
So done, the first and second liner portions 116' of Nguyen would contact the sidewalls of each of the first (adhesion 245) and second (stack metal 250) conductive portions of each of the metal lines 114A-114E, as shown in Fig. 6B-6D of Parikh.
This is all of the limitations of claim 10.
Returning to claim 9, particularly feature [3] of claim 9,
[3] wherein the first opening and the second opening are penetrated through the first conductive layer and the second conductive layer to expose the top surface of the second dielectric layer.
While Examiner respectfully maintains that Nguyen discloses all of the features of claim 9, to the extent that the limitation, “penetrated through”, may be interpreted as requiring a stacked structure of the first and second conductive layers making up the interconnect structures—a point with which Examiner disagrees—then this may be a difference between Nguyen and claim 9. However, making the interconnect structures 114A-114E of Nguyen as taught in Parikh, as explained under claim 10, then the limitation, “penetrated through”, is met.
This is all of the limitations of claim 9.
VI. Response to Arguments
Applicant’s arguments filed 01/06/2026 have been fully considered but they are not persuasive.
Applicant’s arguments directed to Chen (Remarks filed 01/06/2026: pp. 8-9), while noted, are premised on a different set of interconnect patterns 115 and 120 in Chen that make up the first through fourth claimed interconnect structures than those relied on in the Non-Final Rejection mailed 12/09/2025. Examiner respectfully maintains that Chen anticipates each of the features of claim 1 for the reasons explained in the rejection (supra).
Applicant’s arguments directed to Nguyen in view of Naik (Remarks filed 01/06/2026: pp. 9-14), while noted, are premised on a different set of interconnect patterns 114A-114E in Nguyen that make up the first through fourth claimed interconnect structures than those relied on in the Non-Final Rejection mailed 12/09/2025. Examiner respectfully maintains that Nguyen in view of Naik anticipates each of the features of claim 1, as well as claims 2, 3, 5-9, and 11 for the reasons explained in the rejection (supra).
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814