DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Claims 1-3 and 5-8 in the reply filed on 12/04/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statements filed on 04/21/2023 and 02/03/2023 have been considered.
Drawings
The drawings filed on 02/03/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 02/03/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Radulescu (US 2023/0075505).
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Regarding claim 1, Radulescu discloses:
A transistor device, comprising:
a substrate (322, ¶0068);
a plurality of transistor unit cells arranged in parallel on the substrate, wherein each of the transistor unit cells comprises a source contact (315, ¶0072), a drain contact (305, ¶0072), and a gate finger (310, ¶0072) between the source contact (315) and the drain contact (305), wherein the gate finger (310) extends in a first direction and has a first end and a second end;
wherein the source contacts (315), the drain contacts (305) and the gate fingers (310) of the plurality of unit cells define an active region of the transistor device in a portion of the substrate where the source contacts, the drain contacts and the gate fingers overlap in the first direction (x-direction, figure 1); and
a first solder bump (solder bump 367, ¶0082) on the transistor device, wherein the first solder bump is within a periphery of the active region and is electrically connected to the gate finger (310) of a first one of the unit cells at a feed point that is between the first end and the second end of the gate finger (solder bump 367, see figure 2A, is electrically connected to gate finger 310 at least through conductive pillar 366 and metal contact 365, ¶0082 at multiple points between the first and second end of the gate finger 310, figure 1).
Regarding claim 2, Radulescu further discloses:
a source contact pad (321s, ¶0092) on the substrate adjacent a first side of the active region;
a drain contact pad (321d) on the substrate adjacent a second side of the active region opposite the first side of the active region;
a second solder bump (366) on the source contact pad; and
a third solder bump (366) on the drain contact pad.
Regarding claim 3, Radulescu further discloses:
wherein the first solder bump (366) is connected to the gate finger (310) via a first metal interconnect layer (365, ¶0079) between the gate finger (310) and the first solder bump (366).
Regarding claim 5, Radulescu further discloses:
a first plurality of solder bumps (366) on the transistor device, wherein the first plurality of solder bumps are within the periphery of the active region and are electrically connected to gate fingers (310) of respective ones of the plurality of transistor unit cells (figure 7a).
Regarding claim 6, Radulescu further discloses:
wherein the first solder bump (366) is directly above the gate finger (310).
Regarding claim 7, Radulescu further discloses:
wherein the transistor device is configured to be flip-chip mounted to a submount having a contact bond pad region that contacts the first solder bump (¶0122) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radulescu.
Regarding claim 8, Radulescu does not disclose “wherein an input signal is propagated along the contact bond pad region to the first solder bump (365) in a second direction that is perpendicular to the first direction”. However, Applicant is advised that the claimed limitation is an intended use limitation rather than a required structural limitation further limiting the scope of the device claim. The applied prior art can be so modified or used and therefore renders unpatentable such claim limitations. See, for example, M.P.E.P. § 2111.04, and precedents cited therein.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899