DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US9865504B2).
Regarding claim 1, Fig.14 of Lee teaches a semiconductor device, comprising:
a fin structure 20 (col.3, line 19) disposed on a substrate 10 (col.2, line 18), wherein the fin structure 20 protrudes from the substrate 10 in a first direction (Z-direction, col.3, line 19); and
an epitaxial semiconductor layer 60 (col.5, line 45) disposed over an upper part of the fin structure 20 and having an undercut (see annotated Fig.14), wherein the undercut has a first surface (see annotated Fig.14) parallel to a third direction perpendicular to the first direction, wherein the undercut further includes a second surface (see annotated Fig.14) connected to the first surface and lower than the first surface, and wherein an interior angle between the first surface and the second surface is greater than 180 degrees (see annotated Fig.14), a third surface (see annotated Fig.14) connected to the second surface and lower than the second surface, and an interior angle between the third surface and the second surface is less than 180 degrees (see annotated Fig.14).
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Regarding claim 3, Lee further teaches the semiconductor device of claim 1, wherein the undercut (see annotated Fig.14) comprises a curved surface.
Regarding claim 4, Lee further teaches the semiconductor device of claim 1, wherein the substrate 10 (col.2, lines 33-34) comprises silicon.
Regarding claim 5, Lee further teaches the semiconductor device of claim 1, wherein the fin structure 20 (col.3, line 11) comprises silicon.
Regarding claim 10, Lee further teaches the semiconductor device of claim 1, wherein the epitaxial semiconductor layer 60 (col.5, line 45, see annotated Fig.14) has a right-left symmetric, concave polygonal cross-section.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US9865504B2) in view of Wu et al. (US10032910B2).
Regarding claim 6, Lee does not teach wherein the semiconductor device is a PMOS transistor and the epitaxial semiconductor layer comprises compressively stressed silicon germanium.
Fig.6 of Wu teaches a FinFET device that includes epitaxially-grown source and drain regions that include silicon germanium (SiGe) to provide compressive strain within the channel [col.1, lines 56-58].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the epitaxially-grown source and drain regions that include silicon germanium (SiGe) to provide compressive strain within the channel, as taught by Wu, in the teachings of Lee in order to enhance hole mobility Wu, [col.1, lines 56-59]).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US9865504B2) in view of BERGENDAHL et al. (US20170229350A1).
Regarding claim 7, Lee further teaches the semiconductor device of claim 1 further comprising: an isolation structure 30 (col.4, lines 11-12) around the fin structure 20 (col.3, line 19),
However, Lee does not disclose wherein an oxide liner layer conformally covering the undercut; and wherein the oxide liner layer is in direct contact with the isolation structure.
Fig.9A and 9B of BERGENDAHL teaches formation of the first epitaxial semiconductor material 50 in the first device region 15, an oxide liner 55 is formed on the epitaxial semiconductor material 50. The oxide liner 55 is formed on the entirety of the exposed surfaces of the first epitaxial semiconductor material 50. (para.0091).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the oxide liner of BERGENDAHL in the teachings of Lee in order to provide electrical isolation and insulation.
Regarding claim 8, the combination of Lee and BERGENDAHL teaches the semiconductor device of claim 7, BERGENDAHL does not teach wherein the oxide liner layer comprises silicon dioxide.
However, it is noted that BERGENDAHL teaches that the oxide liner 55 is formed as a result of oxidation on of the epitaxial semiconductor 50. Thus, if the Source/Drain epitaxial layer 60 of Lee (col.5, lines 50-52, wherein the source/drain epitaxial layer 60 may be grown at a temperature of about 600 to 800° C. under a pressure of about 80 to 150 Torr, by using a Si containing gas) is oxidized to form a liner, a person having ordinary skills in the art would understand that the oxidation of Si would result in the formation of either silicon dioxide liner.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the oxide liner of BERGENDAHL in the teachings of Lee based on the rationale of relying on teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
Regarding claim 9, BERGENDAHL further teaches the semiconductor device of claim 7, wherein the oxide liner layer has a thickness of 1-30 angstroms. In paragraph 0091, BERGENDAHL teaches wherein the oxide liner 55 has a thickness ranging from 2 nm to 5 nm, which is an overlapping range. It should be noted that it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (MPEP 2144.05.I).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights