Prosecution Insights
Last updated: October 25, 2026
Application No. 18/106,072

DISPLAY DEVICE

Non-Final OA §103§DOUBLEPATENT
Filed
Feb 06, 2023
Priority
Sep 19, 2008 — JP 2008-241335 +5 more
Examiner
LIN, JOHN
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
5 (Non-Final)
60%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
257 granted / 428 resolved
-8.0% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
29 currently pending
Career history
453
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
56.4%
+16.4% vs TC avg
§102
21.5%
-18.5% vs TC avg
§112
19.4%
-20.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 428 resolved cases

Office Action

§103 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Response to Amendment This Office Action is in response to Applicant’s reply filed on 25 July 2026. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 2-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 10,559,599, hereinafter referred to as Yamazaki, in view of U.S. Pub. 2002/0113934, hereinafter referred to as Aoki, in view of U.S. Pub. 2005/0247939, hereinafter referred to as Iketsu et al., in view of U.S. Patent 6,255,130, hereinafter referred to as Kim. Regarding claim 2, claim 4 of Yamazaki recites most of the limitations of claim 2. Yamazaki appears not to explicitly recite a second insulating layer interposed between the transparent conductive film and the first insulating layer, wherein the first insulating layer comprises a first opening and the second insulating layer comprises a second opening, wherein the transparent conductive film overlaps the first opening and the second opening, wherein the second opening does not overlap the first opening, wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the second opening. Aoki, however, in Fig. 7(b) and in paragraphs 47 and 51, discloses a second insulating layer (9) interposed between the transparent conductive film (7) and the first insulating layer (3), wherein the first insulating layer (3) comprises a first opening (middle 8) and the second insulating layer (9) comprises a second opening (right 8), wherein the transparent conductive film (7) overlaps the first opening (middle 8) and the second opening (right 8), wherein the second opening (right 8) does not overlap the first opening (middle 8), wherein in the second direction (horizontal direction), the transparent conductive film (7) comprises a region extending beyond a second side edge (right vertical edge of 2) of the first conductive layer (2), and wherein the first opening (middle 8) is larger than the second opening (right 8). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Aoki, to have made a second insulating layer interposed between the transparent conductive film and the first insulating layer, wherein the first insulating layer comprises a first opening and the second insulating layer comprises a second opening, wherein the transparent conductive film overlaps the first opening and the second opening, wherein the second opening does not overlap the first opening, wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the second opening in order to electrically connect the first conductive layer, the second conductive layer and the transparent conductive film while protecting the surrounding elements. Claim 4 of Yamazaki also appears not to explicitly disclose wherein a first side edge of the second insulating layer facing the second opening is tapered. Iketsu et al., however, in Fig. 9B and in paragraph 66, discloses a first side edge (side edge of 9b facing 6) of the second insulating layer (9b) facing the second opening (6) is tapered in order to prevent cracks in the second conductive layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Iketsu et al., to have made a first side edge of the second insulating layer facing the second opening is tapered in order to prevent cracks in the second conductive layer (paragraph 66 of Iketsu et al.). Claim 4 of Yamazaki also appears not to explicitly disclose wherein the transparent conductive film overlaps with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer. Kim, however, in Fig. 1, discloses the transparent conductive film (84; column 13, lines 6-9) overlaps with a third side edge (left vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24; column 7, lines 7-25) opposite the second side edge (right vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Kim, to have made the transparent conductive film overlap with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer in order to protect the first conductive layer from corrosion and to supplement adhesiveness between an external circuit and the first conductive layer (column 8, lines 50-56 of Kim). Regarding claim 3, claim 4 of Yamazaki discloses the connection portion is located in a position which does not overlap a sealant. Regarding claim 4, Yamazaki recites in claim 4 most of the limitations of claim 4. Yamazaki appears not to explicitly recite a second insulating layer interposed between the transparent conductive film and the first insulating layer, wherein the first insulating layer comprises a first opening and the second insulating layer comprises a second opening and a third opening, wherein the transparent conductive film overlaps the first opening and the second opening, wherein the second opening does not overlap the first opening, wherein the third opening does not overlap with the first opening, wherein the first opening is larger than the second opening, wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the third opening. Aoki, however, in Figs. 7(a) and 7(b) and in paragraphs 47 and 51, discloses a second insulating layer (9) interposed between the transparent conductive film (7) and the first insulating layer (3), wherein the first insulating layer (3) comprises a first opening and the second insulating layer (9) comprises a second opening and a third opening, wherein the transparent conductive film (7) overlaps the first opening (rightmost 8) and the second opening, wherein the second opening does not overlap the first opening, wherein the third opening does not overlap with the first opening, wherein the first opening is larger than the second opening, wherein in the second direction (horizontal direction), the transparent conductive film (7) comprises a region extending beyond a second side edge (right vertical edge of 2) of the first conductive layer (2), and wherein the first opening is larger than the third opening. PNG media_image1.png 444 611 media_image1.png Greyscale It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Aoki, to have made a second insulating layer interposed between the transparent conductive film and the first insulating layer, wherein the first insulating layer comprises a first opening and the second insulating layer comprises a second opening and a third opening, wherein the transparent conductive film overlaps the first opening and the second opening, wherein the second opening does not overlap the first opening, and wherein the third opening does not overlap with the first opening, wherein the first opening is larger than the second opening, wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the third opening in order to electrically connect the first conductive layer, the second conductive layer and the transparent conductive film while protecting the surrounding elements. Yamazaki also appears not to explicitly disclose wherein a first side edge of the second insulating layer facing the second opening is tapered. Iketsu et al., however, in Fig. 9B and in paragraph 66, discloses a first side edge (side edge of 9b facing 6) of the second insulating layer (9b) facing the second opening (6) is tapered in order to prevent cracks in the second conductive layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Iketsu et al., to have made a first side edge of the second insulating layer facing the second opening is tapered in order to prevent cracks in the second conductive layer (paragraph 66 of Iketsu et al.). Claim 4 of Yamazaki also appears not to explicitly disclose wherein the transparent conductive film overlaps with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer. Kim, however, in Fig. 1, discloses the transparent conductive film (84; column 13, lines 6-9) overlaps with a third side edge (left vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24; column 7, lines 7-25) opposite the second side edge (right vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Kim, to have made the transparent conductive film overlap with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer in order to protect the first conductive layer from corrosion and to supplement adhesiveness between an external circuit and the first conductive layer (column 8, lines 50-56 of Kim). Regarding claim 5, claim 4 of Yamazaki discloses the connection portion is located in a position which does not overlap a sealant. Regarding claim 6, claim 4 of Yamazaki recites most of the limitations of claim 6. Yamazaki appears not to explicitly recite a second insulating layer interposed between the transparent conductive film and the first insulating layer, wherein the first insulating layer comprises a first opening and the second insulating layer comprises a second opening, wherein the transparent conductive film overlaps the first opening and the second opening, wherein the second opening does not overlap the first opening, wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the second opening. Aoki, however, in Fig. 7(b) and in paragraphs 47 and 51, discloses a second insulating layer (9) interposed between the transparent conductive film (7) and the first insulating layer (3), wherein the first insulating layer (3) comprises a first opening (middle 8) and the second insulating layer (9) comprises a second opening (right 8), wherein the transparent conductive film (7) overlaps the first opening (middle 8) and the second opening (right 8), wherein the second opening (right 8) does not overlap the first opening (middle 8), wherein in the second direction (horizontal direction), the transparent conductive film (7) comprises a region extending beyond a second side edge (right vertical edge of 2) of the first conductive layer (2), and wherein the first opening (middle 8) is larger than the second opening (right 8). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Aoki, to have made a second insulating layer interposed between the transparent conductive film and the first insulating layer, wherein the first insulating layer comprises a first opening and the second insulating layer comprises a second opening, wherein the transparent conductive film overlaps the first opening and the second opening, wherein the second opening does not overlap the first opening, wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the second opening in order to electrically connect the first conductive layer, the second conductive layer and the transparent conductive film while protecting the surrounding elements. Yamazaki also appears not to explicitly disclose wherein a first side edge of the second insulating layer facing the second opening is tapered. Iketsu et al., however, in Fig. 9B and in paragraph 66, discloses a first side edge (side edge of 9b facing 6) of the second insulating layer (9b) facing the second opening (6) is tapered in order to prevent cracks in the second conductive layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Iketsu et al., to have made a first side edge of the second insulating layer facing the second opening is tapered in order to prevent cracks in the second conductive layer (paragraph 66 of Iketsu et al.). Claim 4 of Yamazaki also appears not to explicitly disclose wherein the transparent conductive film overlaps with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer. Kim, however, in Fig. 1, discloses the transparent conductive film (84; column 13, lines 6-9) overlaps with a third side edge (left vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24; column 7, lines 7-25) opposite the second side edge (right vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 4 of Yamazaki, as disclosed by Kim, to have made the transparent conductive film overlap with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer in order to protect the first conductive layer from corrosion and to supplement adhesiveness between an external circuit and the first conductive layer (column 8, lines 50-56 of Kim). Regarding claim 7, claim 4 of Yamazaki discloses the connection portion is located in a position which does not overlap a sealant. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2, 4 and 6 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Aoki (U.S. Pub. 2002/0113934) in view of Iketsu et al. (U.S. Pub. 2005/0247939) in view of Kim (U.S. Patent 6,255,130). Claim 2: Aoki discloses a semiconductor device, in Figs. 10(a) and 10(b) and in paragraphs 4-8, comprising: a pixel portion (right portion in Fig. 10(a) having pixel electrodes 5); and a connection portion (left portion in Fig. 10(a) connecting patterns 7) outside the pixel portion, wherein the connection portion comprises: a first conductive layer (11) separated from a gate wiring (2) of the pixel portion, wherein the first conductive layer (11) and the gate wiring (2) comprise aluminum; a second conductive layer (13 and 15) separated from a source wiring (4) of the pixel portion, the second conductive layer (13 and 15) and the source wiring (4) comprise aluminum; and a transparent conductive film (7) over the second conductive layer (13 and 15), wherein the second conductive layer (13 and 15) is electrically connected to the first conductive layer (11) and the transparent conductive film (7), wherein the second conductive layer (13 and 15) is located over the first conductive layer (11) with a first insulating layer (3) interposed therebetween, wherein the transparent conductive film (7) is located over the first conductive layer (11) with the first insulating layer (3) and a second insulating layer (9) interposed therebetween, wherein the first insulating layer (3) comprises a first opening (rightmost 8) and the second insulating layer (9) comprises a second opening (fourth 8 from the right), wherein the transparent conductive film (7) overlaps with the first opening (rightmost 8) and the second opening (fourth 8 from the right), wherein the second opening (fourth 8 from the right) does not overlap with the first opening (rightmost 8), wherein the second conductive layer (13 and 15) overlaps with the first conductive layer (11), wherein the second conductive layer (13 and 15) comprises a first region (13) having a first width (width of 13 in the horizontal direction in Fig. 10(a)) and a second region (15) having a second width (width of 15 in the horizontal direction in Fig. 10(a)) smaller than the first width, the second region (15) extending from the first region (13), wherein in a first direction (vertical direction in Fig. 10(a)), the second region (15) of the second conductive layer (13 and 15) extends beyond a first side edge (lower edge of 11 in Fig. 10(a)) of the first conductive layer (11) and a first side edge (lower edge of 7 in Fig. 10(a)) of the transparent conductive film (7), and wherein in a second direction (horizontal direction in Fig. 10(a)) intersecting with the first direction (vertical direction in Fig. 10(a)), the first width (width of 13 in the horizontal direction in Fig. 10(a)) of the first region (13) of the second conductive layer (13 and 15) is smaller than a width (width of 11 in the horizontal direction in Fig. 10(a)) of the first conductive layer (11) and smaller than a width (width of 7 in the horizontal direction in Fig. 10(a)) of the transparent conductive film (7). The recitation “the semiconductor device has a function of driving in FFS mode” has been considered and determined to be intended use, making the claim scope not distinguish over a semiconductor device capable of having voltage applied to the device to be driven in FFS mode as the intended use recitation. See M.P.E.P. § 2114, and precedents cited therein. PNG media_image2.png 291 519 media_image2.png Greyscale Aoki, in the embodiment of Figs. 10(a) and 10(b) appears not to explicitly disclose wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the second opening. Aoki, however, in Figs. 7(a) and 7(b) and in paragraphs 48 and 51, discloses wherein in the second direction (horizontal direction in Fig. 7(a)), the transparent conductive film (7) comprises a region extending beyond a second side edge (right vertical edge of 2) of the first conductive layer (2), and the first opening (right 8) is larger than the second opening (middle 8). Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Aoki in the embodiment of Figs. 7(a) and 7(b) that is in the same field of endeavor with Aoki in the embodiment of Figs. 10(a) and 10(b), before the effective filing date of the claimed invention in order to substitute, in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and the first opening being larger than the second opening as disclosed by Aoki in the embodiment of Figs. 7(a) and 7(b) for the transparent conductive film and the first and second openings disclosed by Aoki in the embodiment of Figs. 10(a) and 10(b). The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of, in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and the first opening being larger than the second opening disclosed by Aoki in the embodiment of Fig. 7(b) for transparent conductive film and the first and second openings disclosed by Aoki in the embodiment of Figs. 10(a) and 10(b) would have yielded predictable results, namely providing a suitable electrical connection between the metal layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Aoki also appears not to explicitly disclose wherein a first side edge of the second insulating layer facing the second opening is tapered. Iketsu et al., however, in Fig. 9B and in paragraph 66, discloses a first side edge (side edge of 9b facing 6) of the second insulating layer (9b) facing the second opening (6) is tapered in order to prevent cracks in the second conductive layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Aoki with the disclosure of Iketsu et al. to have made a first side edge of the second insulating layer facing the second opening is tapered in order to prevent cracks in the second conductive layer (paragraph 66 of Iketsu et al.). Aoki also appears not to explicitly disclose wherein the transparent conductive film overlaps with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer. Kim, however, in Fig. 1, discloses the transparent conductive film (84; column 13, lines 6-9) overlaps with a third side edge (left vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24; column 7, lines 7-25) opposite the second side edge (right vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Aoki with the disclosure of Kim to have made the transparent conductive film overlap with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer in order to protect the first conductive layer from corrosion and to supplement adhesiveness between an external circuit and the first conductive layer (column 8, lines 50-56 of Kim). Claim 4: Aoki discloses a semiconductor device, in Figs. 10(a) and 10(b) and in paragraphs 4-8, comprising: a pixel portion (right portion in Fig. 10(a) having pixel electrodes 5); and a connection portion (left portion in Fig. 10(a) connecting patterns 7) outside the pixel portion, wherein the connection portion comprises: a first conductive layer (11) separated from a gate wiring (2) of the pixel portion, wherein the first conductive layer (11) and the gate wiring (2) comprise aluminum; a second conductive layer (13 and 15) separated from a source wiring (4) of the pixel portion, the second conductive layer (13 and 15) and the source wiring (4) comprise aluminum; and a transparent conductive film (7) over the second conductive layer (13 and 15), wherein the second conductive layer (13 and 15) is electrically connected to the first conductive layer (11) and the transparent conductive film (7), wherein the second conductive layer (13 and 15) is located over the first conductive layer (11) with a first insulating layer (3) interposed therebetween, wherein the transparent conductive film (7) is located over the first conductive layer (11) with the first insulating layer (3) and a second insulating layer (9) interposed therebetween, wherein the first insulating layer (3) comprises a first opening (rightmost 8) and the second insulating layer (9) comprises a second opening (fourth 8 from the right) and a third opening (fifth 8 from the right), wherein the transparent conductive film (7) overlaps with the first opening (rightmost 8) and the second opening (fourth 8 from the right), wherein the second opening (fourth 8 from the right) does not overlap with the first opening (rightmost 8), wherein the third opening (fifth 8 from the right) does not overlap with the first opening (rightmost 8), wherein the second conductive layer (13 and 15) overlaps with the first conductive layer (11), wherein the second conductive layer (13 and 15) comprises a first region (13) having a first width (width of 13 in the horizontal direction in Fig. 10(a)) and a second region (15) having a second width (width of 15 in the horizontal direction in Fig. 10(a)) smaller than the first width, the second region (15) extending from the first region (13), wherein in a first direction (vertical direction in Fig. 10(a)), the second region (15) of the second conductive layer (13 and 15) extends beyond a first side edge (lower edge of 11 in Fig. 10(a)) of the first conductive layer (11) and a first side edge (lower edge of 7 in Fig. 10(a)) of the transparent conductive film (7), and wherein in a second direction (horizontal direction in Fig. 10(a)) intersecting with the first direction (vertical direction in Fig. 10(a)), the first width (width of 13 in the horizontal direction in Fig. 10(a)) of the first region (13) of the second conductive layer (13 and 15) is smaller than a width (width of 11 in the horizontal direction in Fig. 10(a)) of the first conductive layer (11) and smaller than a width (width of 7 in the horizontal direction in Fig. 10(a)) of the transparent conductive film (7). The recitation “the semiconductor device has a function of driving in FFS mode” has been considered and determined to be intended use, making the claim scope not distinguish over a semiconductor device capable of having voltage applied to the device to be driven in FFS mode as the intended use recitation. See M.P.E.P. § 2114, and precedents cited therein. PNG media_image2.png 291 519 media_image2.png Greyscale Aoki, in the embodiment of Figs. 10(a) and 10(b) appears not to explicitly disclose wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, wherein the first opening is larger than the second opening, and wherein the first opening is larger than the third opening. Aoki, however, in Fig. 7(a) and in paragraphs 48 and 51, discloses wherein in the second direction (horizontal direction), the transparent conductive film (7) comprises a region extending beyond a second side edge (right vertical edge of 2) of the first conductive layer (2), the first opening is larger than the second opening, and the first opening is larger than the third opening. PNG media_image1.png 444 611 media_image1.png Greyscale Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Aoki in the embodiment of Fig. 7(a) that is in the same field of endeavor with Aoki in the embodiment of Figs. 10(a) and 10(b), before the effective filing date of the claimed invention in order to substitute, in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, the first opening being larger than the second opening, and the first opening is larger than the third opening as disclosed by Aoki in the embodiment of Fig. 7(a) for the transparent conductive film and the first and second openings disclosed by Aoki in the embodiment of Figs. 10(a) and 10(b). The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of, in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer the first opening being larger than the second opening, and the first opening is larger than the third opening disclosed by Aoki in the embodiment of Fig. 7(a) for the transparent conductive film and the first and second openings disclosed by Aoki in the embodiment of Figs. 10(a) and 10(b) would have yielded predictable results, namely providing a suitable electrical connection between the metal layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Aoki also appears not to explicitly disclose wherein a first side edge of the second insulating layer facing the second opening is tapered. Iketsu et al., however, in Fig. 9B and in paragraph 66, discloses a first side edge (side edge of 9b facing 6) of the second insulating layer (9b) facing the second opening (6) is tapered in order to prevent cracks in the second conductive layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Aoki with the disclosure of Iketsu et al. to have made a first side edge of the second insulating layer facing the second opening is tapered in order to prevent cracks in the second conductive layer (paragraph 66 of Iketsu et al.). Aoki also appears not to explicitly disclose wherein the transparent conductive film overlaps with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer. Kim, however, in Fig. 1, discloses the transparent conductive film (84; column 13, lines 6-9) overlaps with a third side edge (left vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24; column 7, lines 7-25) opposite the second side edge (right vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Aoki with the disclosure of Kim to have made the transparent conductive film overlap with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer in order to protect the first conductive layer from corrosion and to supplement adhesiveness between an external circuit and the first conductive layer (column 8, lines 50-56 of Kim). Claim 6: Aoki discloses a semiconductor device, in Figs. 10(a) and 10(b) and in paragraphs 4-8, comprising: a pixel portion (right portion in Fig. 10(a) having pixel electrodes 5); and a connection portion (left portion in Fig. 10(a) connecting patterns 7) outside the pixel portion, wherein the connection portion comprises: a first conductive layer (11) separated from a gate wiring (2) of the pixel portion, wherein the first conductive layer (11) and the gate wiring (2) comprise aluminum; a second conductive layer (13 and 15) separated from a source wiring (4) of the pixel portion, the second conductive layer (13 and 15) and the source wiring (4) comprise aluminum; and a transparent conductive film (7) over the second conductive layer (13 and 15), wherein the second conductive layer (13 and 15) is electrically connected to the first conductive layer (11) and the transparent conductive film (7), wherein the second conductive layer (13 and 15) is located over the first conductive layer (11) with a first insulating layer (3) interposed therebetween, wherein the transparent conductive film (7) is located over the first conductive layer (11) with the first insulating layer (3) and a second insulating layer (9) interposed therebetween, wherein the first insulating layer (3) comprises a first opening (rightmost 8) and the second insulating layer (9) comprises a second opening (fourth 8 from the right), wherein the transparent conductive film (7) overlaps with the first opening (rightmost 8) and the second opening (fourth 8 from the right), wherein the second opening (fourth 8 from the right) does not overlap with the first opening (rightmost 8), wherein the second conductive layer (13 and 15) overlaps with the first conductive layer (11), wherein the second conductive layer (13 and 15) comprises a first region (13) having a first width (width of 13 in the horizontal direction in Fig. 10(a)) and a second region (15) having a second width (width of 15 in the horizontal direction in Fig. 10(a)) smaller than the first width, the second region (15) extending from the first region (13), wherein in a first direction (vertical direction in Fig. 10(a)), the second region (15) of the second conductive layer (13 and 15) extends beyond a first side edge (lower edge of 11 in Fig. 10(a)) of the first conductive layer (11) and a first side edge (lower edge of 7 in Fig. 10(a)) of the transparent conductive film (7), and wherein in a second direction (horizontal direction in Fig. 10(a)) intersecting with the first direction (vertical direction in Fig. 10(a)), the first width (width of 13 in the horizontal direction in Fig. 10(a)) of the first region (13) of the second conductive layer (13 and 15) is smaller than a width (width of 11 in the horizontal direction in Fig. 10(a)) of the first conductive layer (11) and smaller than a width (width of 7 in the horizontal direction in Fig. 10(a)) of the transparent conductive film (7). PNG media_image2.png 291 519 media_image2.png Greyscale Aoki, in the embodiment of Figs. 10(a) and 10(b) appears not to explicitly disclose wherein in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and wherein the first opening is larger than the second opening. Aoki, however, in Figs. 7(a) and 7(b) and in paragraphs 48 and 51, discloses wherein in the second direction (horizontal direction), the transparent conductive film (7) comprises a region extending beyond a side edge (right vertical edge of 2) of the first conductive layer (2), and the first opening (right 8) is larger than the second opening (middle 8). Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Aoki in the embodiment of Figs. 7(a) and 7(b) that is in the same field of endeavor with Aoki in the embodiment of Figs. 10(a) and 10(b), before the effective filing date of the claimed invention in order to substitute, in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and the first opening being larger than the second opening as disclosed by Aoki in the embodiment of Figs. 7(a) and 7(b) for transparent conductive film and the first and second openings disclosed by Aoki in the embodiment of Figs. 10(a) and 10(b). The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of, in the second direction, the transparent conductive film comprises a region extending beyond a second side edge of the first conductive layer, and the first opening being larger than the second opening disclosed by Aoki in the embodiment of Figs. 7(a) and 7(b) for the transparent conductive film and the first and second openings disclosed by Aoki in the embodiment of Figs. 10(a) and 10(b) would have yielded predictable results, namely providing a suitable electrical connection between the metal layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Aoki appears not to explicitly disclose wherein a first side edge of the second insulating layer facing the second opening is tapered. Iketsu et al., however, in Fig. 9B and in paragraph 66, discloses a first side edge (side edge of 9b facing 6) of the second insulating layer (9b) facing the second opening (6) is tapered in order to prevent cracks in the second conductive layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Aoki with the disclosure of Iketsu et al. to have made a first side edge of the second insulating layer facing the second opening is tapered in order to prevent cracks in the second conductive layer (paragraph 66 of Iketsu et al.). Aoki also appears not to explicitly disclose wherein the transparent conductive film overlaps with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer. Kim, however, in Fig. 1, discloses the transparent conductive film (84; column 13, lines 6-9) overlaps with a third side edge (left vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24; column 7, lines 7-25) opposite the second side edge (right vertical edge of 24; column 7, lines 7-25) of the first conductive layer (24). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Aoki with the disclosure of Kim to have made the transparent conductive film overlap with a third side edge of the first conductive layer opposite the second side edge of the first conductive layer in order to protect the first conductive layer from corrosion and to supplement adhesiveness between an external circuit and the first conductive layer (column 8, lines 50-56 of Kim). Claims 3, 5 and 7 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Aoki in view of Iketsu et al. in view of Kim as applied to claim 2, 4 and 6 above, and further in view of Akimoto (U.S. Pub. 2007/0108446). Claim 3: Aoki in view of Iketsu et al. in view of Kim discloses the semiconductor device according to claim 2. Aoki in view of Iketsu et al. in view of Kim appears not to explicitly disclose the connection portion is located in a position which does not overlap a sealant. Akimoto, however, in Fig. 9B and in paragraph 143, discloses a connection portion (portion where 71 is connected to 69) is located in a position which does not overlap a sealant (75). It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Aoki in view of Iketsu et al. in view of Kim with the disclosure of Akimoto to have made the connection portion is located in a position which does not overlap a sealant in order to provide a region to fill with liquid crystal composition while allowing electrical connections within the device. Claim 5: Aoki in view of Iketsu et al. in view of Kim discloses the semiconductor device according to claim 4. Aoki in view of Iketsu et al. in view of Kim appears not to explicitly disclose the connection portion is located in a position which does not overlap a sealant. Akimoto, however, in Fig. 9B and in paragraph 143, discloses a connection portion (portion where 71 is connected to 69) is located in a position which does not overlap a sealant (75). It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Aoki in view of Iketsu et al. in view of Kim with the disclosure of Akimoto to have made the connection portion is located in a position which does not overlap a sealant in order to provide a region to fill with liquid crystal composition while allowing electrical connections within the device. Claim 7: Aoki in view of Iketsu et al. in view of Kim discloses the semiconductor device according to claim 6. Aoki in view of Iketsu et al. in view of Kim appears not to explicitly disclose the connection portion is located in a position which does not overlap a sealant. Akimoto, however, in Fig. 9B and in paragraph 143, discloses a connection portion (portion where 71 is connected to 69) is located in a position which does not overlap a sealant (75). It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Aoki in view of Iketsu et al. in view of Kim with the disclosure of Akimoto to have made the connection portion is located in a position which does not overlap a sealant in order to provide a region to fill with liquid crystal composition while allowing electrical connections within the device. Response to Arguments Applicant’s arguments with respect to claim(s) 2-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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Prosecution Timeline

Show 4 earlier events
Sep 18, 2025
Request for Continued Examination
Oct 01, 2025
Response after Non-Final Action
Dec 16, 2025
Non-Final Rejection mailed — §103, §DOUBLEPATENT
Mar 09, 2026
Response Filed
Jun 02, 2026
Final Rejection mailed — §103, §DOUBLEPATENT
Jul 25, 2026
Request for Continued Examination
Jul 28, 2026
Response after Non-Final Action
Oct 08, 2026
Non-Final Rejection mailed — §103, §DOUBLEPATENT (current)

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5-6
Expected OA Rounds
60%
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68%
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3y 9m (~0m remaining)
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