Attorney’s Docket Number: NAUP4160USA
Filing Date: 2/9/2023
Claimed Priority Date: 12/28/2022 (TW 111150397)
Inventors: Chang et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the request for reconsideration filed on 7/10/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Request for Reconsideration Status
The request for reconsideration filed on 7/10/2025 in reply to the Office action in paper no. 7, mailed on 6/25/2025, has been entered. The present Office action is made with all the suggested arguments being fully considered. Accordingly, pending in this Office action are claims 1-27.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6,11, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2022/0336502) in view of Lee (US 2020/0194267).
Regarding claim 1, Oh (see, e.g., fig. 3) shows most aspects of the instant invention including a high-voltage transistor comprising:
A well region in a semiconductor substrate 200
A gate structure 225 above the well
A gate oxide layer 224 between the gate and the well and including first and second portions
First and second drift regions in the well
wherein:
The first and second drift regions are located at opposite sides of the gate 225
The first drift region is adjacent to the first portion of the gate oxide 224
The second drift region is adjacent to the second portion of the gate oxide 224
The first and second drift regions have the same conductivity type
Regarding claim 11, Oh (see, e.g., fig. 3) shows most aspects of the instant invention including a level-up shifting circuit comprising a first high-voltage transistor, wherein the transistor comprises:
A first well region in a semiconductor substrate 200
A first gate structure 225 above the well
A first gate oxide layer 224 between the first gate and the first well and including first and second portions, and
First and second drift regions in the first well
wherein:
The first and second drift regions are located at opposite sides of the first gate 225
The first drift region is adjacent to the first portion of the gate oxide 224
The second drift region is adjacent to the second portion of the gate oxide 224
The first and second drift regions have the same conductivity type
Regarding claims 1 and 11, Oh fails to disclose that the first portion of the gate oxide is thicker than the second portion. Lee (see, e.g., par. 0055) teaches that such a configuration reduces or prevents the hot carrier effect in a transistor.
Accordingly, it would have been obvious to a person of ordinary skill in the art, at the time of filing the invention, to modify the transistor of Oh to include the thicker first portion of the gate oxide of Lee to mitigate the hot carrier effect.
Regarding claims 1, 5 and 11, although Lee (see, e.g., par. 0055) teaches that having the first portion of the gate oxide thicker than the second helps prevent the hot carrier effect in a transistor, he does not disclose that the thickness of the second portion is greater than one-quarter the thickness of the first portion. However, differences in thickness alone do not support patentability over the prior art unless there is evidence that such differences are critical.
As the courts noted in In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955), “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In the present case, selecting the claimed thickness for the second portion would not yield any meaningful change in the performance of Lee’s gate oxide. That is, so long as the first portion is thicker, as Lee already teaches, the hot carrier effect will be mitigated.
Accordingly, in the absence of evidence establishing the criticality of the claimed thickness ratios (see paragraph below), it would have been obvious to a person of ordinary skill in the art to use these values in the device of Lee.
CRITICALITY
The specification does not disclose the critical nature of the claimed thickness ratios or any unexpected results arising from them. Where patentability is said to be based upon chosen dimensions or a recited variable, the applicant must demonstrate that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 2, Oh (see, e.g., fig. 3) shows the transistor further comprising a deep well region 220 in the substrate and under the well PW. Oh also shows that the conductivity type of the deep well 220 is the same as the drift regions ND and complementary to the well PW.
Regarding claim 3, Oh (see, e.g., fig. 3) shows the transistor further comprising a deep well region 220 in the substrate and under the well NW. Oh also shows that the conductivity type of the deep well 220 is the same as the well NW and complementary to the drift regions PD.
Regarding claim 4, Oh (see, e.g., fig. 3) shows the transistor further comprising:
A first doped region 222 in the first drift region ND
A second doped region in the second drift region ND
wherein:
The first and second doped regions 222 are located on opposite sides of the gate
The doped 222 and drift ND regions have the same conductivity type
Regarding claims 6 and 17, Lee (see, e.g., par. 0054/ll.6-9) shows that the length of the first portion is less than the length of the second portion of the gate oxide.
Regarding claim 16, Oh (see, e.g., fig. 3) shows that the conductivity type of the first well PW is complementary to the first and second drift regions ND.
Claims 1, 7, 9, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hatakenaka (US 2021/0305425) in view of Lee.
Regarding claim 1, Hatakenaka (see, e.g., fig. 11) shows most aspects of the instant invention including a high-voltage transistor 50 comprising:
A well region 101 in a semiconductor substrate 100
A gate structure 105 above the well
A gate oxide layer 104 between the gate and the well and including first and second portions
First and second drift regions in the well
wherein:
The first and second drift regions are located at opposite sides of the gate 105
The first drift region is adjacent to the first portion of the gate oxide 104
The second drift region is adjacent to the second portion of the gate oxide 104
The first and second drift regions have the same conductivity type
Regarding claim 11, Hatakenaka (see, e.g., fig. 11) shows most aspects of the instant invention including a level-up shifting circuit comprising a first high-voltage transistor 50, wherein the transistor comprises:
A first well region 101 in a semiconductor substrate
A first gate structure 105 above the well
A first gate oxide layer 104 between the first gate and the first well and including first and second portions, and
First and second drift regions in the first well 101
wherein:
The first and second drift regions are located at opposite sides of the first gate 105
The first drift region is adjacent to the first portion of the gate oxide 104
The second drift region is adjacent to the second portion of the gate oxide 104
The first and second drift regions have the same conductivity type
Regarding claims 1 and 11, Hatakenaka fails to disclose that the first portion of the gate oxide is thicker than the second portion. Lee (see, e.g., par. 0055) teaches that such a configuration reduces or prevents the hot carrier effect in a transistor.
Accordingly, it would have been obvious to a person of ordinary skill in the art, at the time of filing the invention, to modify the transistor of Hatakenaka to include the thicker first portion of the gate oxide of Lee to mitigate the hot carrier effect.
Regarding claims 1 and 11, see also the comments stated above in paragraphs 9-12, which are considered repeated here.
Regarding claims 7 and 18, Hatakenaka (see, e.g., fig. 11) shows that a part of the first drift region 102B is under the first gate 105, and that the second drift region 103A is not under the first gate.
Regarding claim 9, Hatakenaka (see, e.g., fig. 11) shows the transistor further comprising a third drift region 102B in the well and under the first drift region 103B, wherein a bottom of the third region is lower that a bottom of the second drift region 103A.
Allowable Subject Matter
Claims 12-15 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Response to Arguments
The applicant argues:
Lee focus on the thicker first portion of the gate oxide on the drain side of the transistor. There is no motivation for one of ordinary skill in the art to adjust the thickness of the second portion to be greater than one eight the thickness of the first portion in Lee.
The examiner responds:
This argument is not persuasive. Lee teaches that varying gate oxide thickness reduces electric field intensity and mitigates hot carrier effects (see, e.g., par. 0055). Thus, Lee establishes that gate oxide thickness is a result-effective variable for controlling device reliability and performance. Once a parameter is recognized as result-effective, optimization of that parameter, including selection of thickness ratios between portions of the gate oxide, would have been within the level of ordinary skill in the art.
The claims do not require a specific mechanism or processing technique for achieving the claimed thickness ratio, nor do they recite any unexpected result associated with the claimed one-eighth limitation. Applicant has not provided evidence that a thickness ratio of at least one-eighth yields results different in kind from those achieved by other thickness ratios taught or suggested by Lee.
Accordingly, selecting a thickness for the second portion that is greater than or equal to one-eighth the thickness of the first portion represents a matter of routine optimization of a known device parameter and would have been obvious to one of ordinary skill in the art.
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
January 8, 2026