Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's arguments filed 12/8/2025 have been fully considered.
Applicant’s arguments in respect to claims 1-2, 4, 6, 8-9, 11, 67-70 are persuasive and accordingly a second non-final is being mailed replacing the previous office action.
Applicant’s arguments with respect to amended claims 15, 20, 22-23, 71-72, 75 and 29-30, 33, 37-38, 73-74 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
DETAILED ACTION
This action is responsive to application No. 18107537 filed on 02/09/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Allowable subject matter
Claim 70 is objected to as being dependent upon a rejected base claim (independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Wada et al. (CN 103718298 A).
With respect to dependent claim 70, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the gate pad comprises a first gate pad, the MOSFET further comprising a second gate pad that is positioned adjacent a second location where third and fourth of the sides of the hexagon shaped semiconductor die meet”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, 15, 20, 75 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada et al. (CN 103718298 A).
Regarding independent claim 1, Wada et al. teach a teach semiconductor device, comprising:
a semiconductor die (Figs. 1 & 2, paragraph 0053 discloses MOSFET) that comprises a substrate (Figs. 1 & 2, element 1, that has a hexagonal crystal structure (Fig. 1, paragraph 0012, 0053-0054 discloses hexagonal crystal),
wherein first and second sides of the semiconductor die (Figs. 1 & 2, paragraph 0053-0054 disclose MOSFET layers 2, 3, 4, 5 epitaxially grown on the substrate with hexagonal crystal structure, accordingly the axes would be aligned between the die and substrate) extend along respective first and second crystallographic axes of the hexagonal crystal structure of the substrate.
Regarding claim 2, Wada et al. teach wherein the first side and the second side meet to define an interior angle that is an obtuse angle (Fig. 1).
Regarding claim 4, Wada et al. teach wherein the semiconductor die comprises a power semiconductor die that has a hexagon shape when viewed in plan view (Fig. 1, paragraph 0053-0054 discloses silicon carbide which is the same structure as the instant application).
Regarding claim 6, Wada et al. teach wherein the semiconductor die has a hexagon shape with beveled corners when viewed in plan view (Fig. 1).
Regarding independent claim 15, Wada et al. teach a semiconductor device, comprising:
a semiconductor die (Figs. 1 & 2, paragraph 0053 discloses MOSFET),
wherein the semiconductor die comprises at least five sides when viewed in plan view (Fig. 1), and
wherein the semiconductor device is a silicon carbide power semiconductor device that has a silicon carbide semiconductor layer (Figs. 1 & 2, paragraph 0053-0054 disclose MOSFET having silicon carbide layers 2, 3, 4, 5 epitaxially grown on the substrate 1).
Regarding claim 20, Wada et al. teach wherein at least three of the sides of the semiconductor die extend along crystallographic axes of the crystal structure of the silicon carbide semiconductor layer (Fig. 1).
Regarding claim 75, Wada et al. teach wherein the semiconductor die has a hexagon shape with rounded or beveled corners when viewed in plan view (Fig. 1)
Claims 8-9, 11, 22-23, 29, 30-33, 37-38, 67-69, 71-74 are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (CN 103718298 A) in view of Kumada (US 2023/0062475).
Regarding claim 8, Wada et al. teach all of the limitations as discussed above.
Wada et al. teach a MOSFET that comprises an active region (Figs. 1 & 2, paragraph 0053-0054).
Wada et al. do not explicitly disclose a plurality of unit cell transistors, and wherein a gate runner of the MOSFET comprises at least a first straight segment, a second straight segment, a third straight segment, a fourth straight segment and a fifth straight segment, and the first straight segment connects to the second straight segment at an obtuse angle.
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Kumada teaches a semiconductor device comprising a MOSFET that comprises an active region (Fig. 1, element 1) that comprises a plurality of unit cell transistors (paragraph 0050), and wherein a gate runner (Fig. 1, element 63, paragraph 0050) of the MOSFET comprises at least a first straight segment, a second straight segment, a third straight segment, a fourth straight segment and a fifth straight segment, and the first straight segment connects to the second straight segment at an obtuse angle (see annotated figure).
It would be obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wada et al. according to the teachings of Kumada with the motivation provide interconnection to the gate electrode (paragraph 0050).
Regarding claim 9, Wada et al. modified by Kumada teach wherein the first through fifth straight and second segments of the gate runner each extend along a periphery of the active region (see annotated figure above), and wherein a gate pad of the MOSFET is located in a center of the active region so that the unit cell transistors are formed on all sides of the gate pad when the gate pad is viewed in plan view, and wherein the gate runner comprises a plurality of additional segments that extend outwardly from the gate pad (the addition of gate runner segments from the gate pad would be an obvious design choice).
Regarding claim 11, Wada et al. teach all of the limitations as discussed above.
Wada et al. teach a MOSFET that comprises an active region (Figs. 1 & 2, paragraph 0053-0054).
Wada et al. do not explicitly disclose a plurality of unit cell transistors, and wherein a gate runner of the MOSFET comprises first and second segments that connect at an angle of between 115° and 125°.
Kumada teaches wherein the semiconductor die comprises a MOSFET that comprises an active region (Fig. 1, element 1) that comprises a plurality of unit cell transistors (paragraph 0050), and wherein a gate runner (Fig. 1, element 63, paragraph 0050) of the MOSFET comprises first and second segments that connect at an angle of between 115° and 125° (Kumada teaches an obtuse angle. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the angle as the angle is a result-effective variable. The applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
It would be obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wada et al. according to the teachings of Kumada with the motivation provide interconnection to the gate electrode (paragraph 0050).
Regarding claim 67, Wada et al. modified by Kumada teach wherein the gate runner further comprises at least one additional segment that extends outwardly from the gate pad (the addition of gate runner segments from the gate pad would be an obvious design choice).
Regarding claim 68, Wada et al. modified by Kumada teach wherein the gate runner further comprises a plurality of additional segments that extend radially outwardly from the gate pad (the addition of gate runner segments from the gate pad would be an obvious design choice).
Regarding claim 69, Wada et al. teach all of the limitations as discussed above.
Wada et al. teach wherein the semiconductor die has a hexagon shape when viewed in plan view (Fig. 1) and comprises a MOSFET that comprises a semiconductor layer structure (Figs. 1-2, elements 2, 3, 4, 5, paragraph 0053-0054).
Wada et al. do not explicitly disclose a plurality of unit cell transistors and a gate pad on the semiconductor layer structure, wherein the gate pad is positioned adjacent a first location where first and second of the sides of the hexagon shaped semiconductor die meet.
Kumada teaches a semiconductor device comprising a MOSFET that comprises an active region (Fig. 1, element 1) that comprises a plurality of unit cell transistors (paragraph 0050), and wherein a gate pad (Fig. 1, element 64, paragraph 0049) is located.
It would be obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wada et al. according to the teachings of Kumada (the gate pad is positioned in the middle as disclosed by Kumada and therefore would be positioned between the two sides of the hexagon of Wada when modified) with the motivation provide interconnection to the gate electrode (paragraph 0050).
Regarding claim 22, Wada et al. teach all of the limitations as discussed above.
Wada et al. teach a MOSFET that comprises a semiconductor layer structure (Figs. 1-2, elements 2, 3, 4, 5, paragraph 0053-0054).
Wada et al. do not explicitly disclose wherein a gate runner of the MOSFET comprises first and second segments that connect at an obtuse angle.
Kumada teaches a semiconductor device comprising a MOSFET that comprises an active region (Fig. 1, element 1) that comprises a plurality of unit cell transistors (paragraph 0050), and wherein a gate runner (Fig. 1, element 63, paragraph 0050) of the MOSFET comprises first and second segments that connect at an obtuse angle (Fig. 1).
It would be obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wada et al. according to the teachings of Kumada (the gate pad is positioned in the middle as disclosed by Kumada and therefore would be positioned between the two sides of the hexagon of Wada when modified) with the motivation provide interconnection to the gate electrode (paragraph 0050).
Regarding claim 23, Wada et al. modified by Kumada teach wherein the obtuse angle is an angle of 120° (Kumada teaches an obtuse angle. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the angle as the angle is a result-effective variable. The applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 71, Wada et al. teach all of the limitations as discussed above.
Wada et al. teach a MOSFET that comprises a semiconductor layer structure (Figs. 1-2, elements 2, 3, 4, 5, paragraph 0053-0054).
Wada et al. do not explicitly disclose wherein a gate runner of the MOSFET comprises first and second segments that connect at an obtuse angle.
Kumada teaches a semiconductor device comprising a MOSFET that comprises an active region (Fig. 1, element 1) that comprises a plurality of unit cell transistors (paragraph 0050), and wherein a gate runner (Fig. 1, element 63, paragraph 0050) of the MOSFET comprises first and second segments that connect at an obtuse angle (Fig. 1).
It would be obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wada et al. according to the teachings of Kumada with the motivation provide interconnection to the gate electrode (paragraph 0050).
Regarding claim 72, Wada et al. modified by Kumada teach wherein the gate runner further comprises a plurality of additional segments that extend radially outwardly from the gate pad (the addition of gate runner segments from the gate pad would be an obvious design choice).
Regarding independent claim 29, Wada et al. teach semiconductor device, comprising:
a semiconductor die (Figs. 1 & 2, paragraph 0053 discloses MOSFET), wherein, when viewed in plan view, the semiconductor die has a hexagon shape (Fig. 1, paragraph 0053-0054),
wherein the semiconductor die comprises a MOSFET that comprises a silicon carbide semiconductor layer structure (Figs. 1 & 2, paragraph 0053-0054 disclose MOSFET having silicon carbide layers 2, 3, 4, 5 epitaxially grown on the substrate 1).
Wada et al. do not explicitly disclose having a plurality of unit cell transistors formed therein, and wherein a gate runner of the MOSFET comprises a first straight segment and a second straight segment that is adjacent the first straight segment, where the first segment and the second segment extend along respective first and second axes that intersect to define an angle of 120°.
Kumada teaches a semiconductor device comprising a MOSFET that comprises an active region (Fig. 1, element 1) that comprises a plurality of unit cell transistors (paragraph 0050), and wherein a gate runner (Fig. 1, element 63, paragraph 0050) of the MOSFET comprises a first straight segment and a second straight segment that is adjacent the first straight segment, where the first segment and the second segment extend along respective first and second axes that intersect to define an angle of 120° (Kumada teaches an obtuse angle in Fig. 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the angle as the angle is a result-effective variable. The applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
It would be obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wada et al. according to the teachings of Kumada with the motivation provide interconnection to the gate electrode (paragraph 0050).
Regarding claim 30, Wada et al. teach wherein the semiconductor die comprises a semiconductor layer that has a hexagonal crystal structure (Fig. 1).
Regarding claim 33, Wada et al. teach wherein at least two sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the semiconductor layer (Figs. 1-2, paragraph 0053-0054).
Regarding claim 37, Wada et al. modified by Kumada teach wherein the first and second straight segments of the gate runner each extend along a periphery of the active region (Fig. 1 of Kumada).
Regarding claim 38, Wada et al. modified by Kumada teach wherein a gate pad (Fig. 1, element 64, paragraph 0069 of Kumada) of the MOSFET is located in a center of the active region, and wherein the gate runner comprises a plurality of additional segments that extend radially outwardly from the gate pad (Fig. 1 of Kumada).
Regarding claim 73, Wada et al. modified by Kumada teach wherein the MOSFET further comprises a gate pad (Fig. 1, element 64, paragraph 0069 of Kumada) on the semiconductor layer structure, wherein the gate pad is positioned adjacent a location where the first and second axes intersect (the gate pad is positioned in the middle as disclosed by Kumada and therefore would be positioned between the two sides of the hexagon of Wada when modified).
Regarding claim 74, Wada et al. modified by Kumada teach wherein the MOSFET further comprises a gate pad (Fig. 1, element 64, paragraph 0069 of Kumada) on the semiconductor layer structure, and the gate runner further comprises a plurality of segments that extend radially outwardly from the gate pad (Fig. 1 of Kumada).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813