DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/04/2026 has been entered.
Response to Arguments
6. Applicant’s arguments, see Claim Rejections, filed 5/04/2026, with respect to the rejection(s) of claim(s) 1 and 15 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, Da Hye et al. (Pub No. US 20230420519 A1) (hereinafter, Kim) in view of Lin, Sankuei et al. (Pub No. US 20220359208 A1) (hereinafter, Lin).
7. Applicant’s arguments, see Claim Rejections, filed 5/04/2026, with respect to the rejection(s) of claim(s) 9 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, Da Hye et al. (Pub No. US US 20230420519 A1) (hereinafter, Kim) in view of Ye, Hung-Yu et al. (Pub No. US 20220310787 A1) (hereinafter, Ye) in view of Lin, Sankuei et al. (Pub No. US 20220359208 A1) (hereinafter, Lin).
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 6-8, 15-16 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Da Hye et al. (Pub No. US 20230420519 A1) (hereinafter, Kim), and further in view of Lin, Sankuei et al. (Pub No. US 20220359208 A1) (hereinafter, Lin).
Re Claim 1, (Currently Amended) Kim teaches a semiconductor device, comprising:
an epitaxial source/drain region (Semiconductor liner film/insertion film; 151/152; Fig 11; ¶[0103]), wherein the epitaxial source/drain region has an inner profile (Inner sidewalls of 151/152; Fig 11), and the inner profile includes two or more valley sections (Valleys of inner profile of 151/152; See Fig 11 annotation) alternatively connected between two or more mountain sections (Mountains of inner profile of 151/152; See Fig 11 annotation);
Kim, Fig 11: Embodiment of semiconductor device annotated with mountains and valleys
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two or more channel layers (Sheet patterns; NS1; Fig 11; ¶[0032]) in contact with the epitaxial source/drain region, wherein the two or more channel layers are vertically stacked, and the two or more channel layers correspond (Form the mountain portion on other side of source/drain regions; Fig 11) to the two or more mountain sections in the inner profile;
and a source/drain contact feature (Source/drain contact/filling film/interlayer insulating film; 180/153/190; Fig 11; ¶[0234]) disposed in and on the epitaxial source/drain region, wherein the source/drain contact feature has an outer profile matching (Matches portion of inner profile of epitaxial source/drain region 153; Fig 11) the inner profile of the epitaxial source/drain region.
However, Kim does not teach a silicide layer disposed between the outer profile of the source/drain contact feature and the inner profile of epitaxial source/drain region,
and wherein the silicide layer includes one or more kinks corresponding to the two or more valley sections and the two or more mountain sections of the inner profile of the epitaxial source/drain region.
In the same field of endeavor, Lin teaches a silicide layer (Silicide layer; 322; Fig 3; ¶[0024]) disposed between the outer profile (Outer profile of metal fill 310 shaped by silicide layer 322; Fig 3) of the source/drain contact feature (Metal fill; 310; Fig 3; ¶[0025]) and the inner profile (Inner profile of epitaxial material 306 shaped by silicide layer 322; Fig 3) of epitaxial source/drain region (Epitaxial material; 306; Fig 3; ¶[0025]),
and wherein the silicide layer includes one or more kinks (Valley or mountain portion of silicide layer 322; Fig 3) corresponding to the two or more valley sections (Valley sections corresponding to where silicide layer 322 interfaces inner spacers 226; Fig 3) and the two or more mountain sections (Mountain sections corresponding to convex regions of silicide layer 322 surrounding valley therebetween; Fig 3) of the inner profile of the epitaxial source/drain region. (See Fig 3 of Lin below)
Lin, Fig 3: Nanosheet FET device with silicide layers along inner/outer profiles of the source/drain contact and source/drain regions
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a silicide layer disposed between the outer profile of the source/drain contact feature and the inner profile of epitaxial source/drain region, and wherein the silicide layer includes one or more kinks corresponding to the two or more valley sections and the two or more mountain sections of the inner profile of the epitaxial source/drain region, as taught by Lin, with the semiconductor device as taught by Kim. One would have been motivated to do this with a reasonable expectation of success because the silicide layer with kinks along the profiles of the source/drain contact and epitaxial source/drain regions allows for the length of the nanosheet channel layers between the source/drain regions to be controlled. Further, the silicide layer functions as a contact with lowered contact resistance for the source/drain regions (Lin; ¶[0024]).
Re Claim 6, (Original) Kim teaches the semiconductor device of claim 1, wherein the source/drain contact feature (Source/drain contact/filling film/interlayer insulating film; 180/153/190; Fig 11; ¶[0234]) comprises an ILD portion (Interlayer insulating film; 190; Fig 11; ¶[0028]) and a core portion (Source/drain contact and filling film; 180/153; Fig 11; ¶[0234]), the core portion is deposed in a central cavity (First source/drain recess and inner profile of filling film 153; 150R; Fig 11; ¶[0093]) of the epitaxial source/drain region defined by the inner profile (Inner sidewalls of 153; Fig 11) and including alternatively narrow sections and wide sections (Defined by mountains and valley of filling film 153; Fig 11).
Re Claim 7, (Original) Kim teaches the semiconductor device of claim 6, wherein the epitaxial source/drain region (Semiconductor liner film/insertion film; 151/152; Fig 11; ¶[0103]) wraps around (Liner and insertion film wrap around filling film 153 and contact 180; Fig 11) the core portion (Source/drain contact and filling film; 180/153; Fig 11; ¶[0234]) of the source/drain contact feature (Source/drain contact and filling film; 180/153; Fig 11; ¶[0234]).
Re Claim 8, (Original) Kim teaches the semiconductor device of claim 1, further comprising a sacrificial source/drain feature (Upper portion of semiconductor filling film 153; Fig 32) disposed between the source/drain contact feature (Lower portion of source/drain contact 180; Fig 11; ¶[0234]) and a contact etch stop layer (Source/drain etch stop film; 185; Fig 11; ¶[0028]).
Re Claim 15, (Currently Amended) Kim teaches a method (Figs 26 to 32 are intermediate steps, Fig 11 comprises of final steps according to an embodiment; ¶[0219]), comprising:
forming a first fin structure (Upper pattern structure; U_AP; Fig 26; ¶[0220]) along a first direction (D3; Fig 26);
forming a sacrificial gate structure (Dummy gate electrode; 120p; Fig 26; ¶[0223]) along a second direction (D1; Fig 26) and across the first fin structure;
Kim, Fig 26: Forming fin structure and sacrificial gate structure
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etching back the first fin structure to form source/drain openings (First source/drain recess; 150R; Fig 27; ¶[0227]) on opposing sides of the sacrificial gate structure;
Kim, Fig 27: Etching back fin structure to form source/drain openings
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forming epitaxial source/drain regions (Semiconductor liner film; 151; Fig 29; ¶[0229]) in the source/drain openings, wherein each of the epitaxial source/drain regions includes a central cavity (Liner recess; 151R; Fig 29; ¶[0231]);
Kim, Fig 29: Forming epitaxial source/drain regions
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forming an etch stop layer (Semiconductor insertion film, i.e. may act as an etch-stop layer; 152; Fig 11; ¶[0103]) on the epitaxial source/drain regions;
forming a sacrificial source/drain region (Upper portion of semiconductor filling film 153; Figs 11/32; Note: 153 may be considered a sacrificial material, such that a portion of 153 is etched back to form the source/drain contact) on the etch stop layer to fill the central cavity
Kim, Fig 32: Forming sacrificial source/drain region in cavity
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depositing a CESL (contact etch stop layer) (Etch stop film; 185; Fig 11; ¶[0028]) over the sacrificial source/drain region;
depositing an ILD (interlayer dielectric) layer (Interlayer insulating film; 190; Fig 31; ¶[0236]) over the CESL layer;
Kim, Fig 31: Depositing ILD layer over CESL layer
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forming a source/drain contact opening (Opening (not labelled) between ILD layer 190 and silicide layer 155; Fig 11) through the ILD layer and CESL layer to expose the sacrificial source/drain region;
removing the sacrificial source/drain region to form a source/drain cavity (Cavity (step not shown) where silicide film 155 is located; Fig 11),
filling the source/drain cavity to form a source/drain contact feature (Source/drain contact; 180; Fig 11; ¶[0234]).
However, Kim does not teach wherein the source/drain cavity is defined by an inner profile, and the inner profile includes a plurality of valley sections alternatively connected between a plurality of mountain sections; and
forming a silicide layer in the source/drain cavity, wherein the silicide layer includes one or more kinks corresponding to the two or more valley sections and the two or more mountain sections of the inner profile of the source/drain cavity.
In the same field of endeavor, Lin teaches wherein the source/drain cavity (Cavity formed by epitaxial material 306; Fig 3) is defined by an inner profile (Inner profile of epitaxial material 306 shaped by silicide layer 322; Fig 3),
and the inner profile includes a plurality of valley sections (Valley sections corresponding to where silicide layer 322 interfaces inner spacers 226; Fig 3) alternatively connected between a plurality of mountain sections (Mountain sections corresponding to convex regions of silicide layer 322 surrounding valley therebetween; Fig 3); and
forming a silicide layer (Silicide layer; 322; Fig 3; ¶[0024]) in the source/drain cavity, wherein the silicide layer includes one or more kinks (Valley or mountain portion of silicide layer 322; Fig 3) corresponding to the two or more valley sections and the two or more mountain sections of the inner profile of the source/drain cavity.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the source/drain cavity defined by an inner profile, and the inner profile includes a plurality of valley sections alternatively connected between a plurality of mountain sections and forming a silicide layer in the source/drain cavity, wherein the silicide layer includes one or more kinks corresponding to the two or more valley sections and the two or more mountain sections of the inner profile of the source/drain cavity, as taught by Lin, with the semiconductor device as taught by Kim. One would have been motivated to do this with a reasonable expectation of success because the silicide layer with kinks along the profiles of the source/drain contact and epitaxial source/drain regions allows for the length of the nanosheet channel layers between the source/drain regions to be controlled. Further, the silicide layer functions as a contact with lowered contact resistance for the source/drain regions (Lin; ¶[0024]).
Re Claim 16, (Original) Kim teaches the method of claim 15, wherein the first fin structure (Upper pattern structure; U_AP; Fig 26; ¶[0220]) comprises a plurality of vertically stacked semiconductor layers (Sacrificial/active patterns; SC_L/ACT_L; Fig 26; ¶[0222]), and forming the epitaxial source/drain regions comprises:
conformally growing (Continuously formed along source/drain recess 150R; Fig 29) a semiconductor layer (Semiconductor liner film; 151; Fig 29; ¶[0104]) from end surfaces of the plurality of vertically stacked semiconductor layers in the source/drain openings (Source/drain recess; 150R; Fig 28; ¶[0104]); and
terminating growth of the semiconductor layer while a bottom surface (Bottom surface of liner film 151; Fig 29) of the central cavity (Liner recess; 151R; Fig 29; ¶[0231]) is below a lower most semiconductor layer (Lower most sacrificial layer SC_L; Fig 29).
Re Claim 20, (Currently Amended) Kim teaches the method of claim 16, wherein the plurality of mountain sections (Mountains of inner profile of 151/152; See Fig 11 annotation) correspond to the plurality of vertically stacked semiconductor layers (Sheet patterns; NS1; Fig 11; ¶[0032]).
Re Claim 21, (Currently Amended) The method of claim 16, wherein the etch stop layer (Semiconductor insertion film, i.e. may act as an etch-stop layer/Etch stop film; 152/185; Fig 11; ¶[0103]; Note: 185 may extend along profile of source/drain pattern 150, therefore inner profile of 153) is formed on the inner profile (Inner profile of source/drain regions 152 or 153; Fig 11).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Da Hye et al. (Pub No. US US 20230420519 A1) (hereinafter, Kim) in view of Lin, Sankuei et al. (Pub No. US 20220359208 A1) (hereinafter, Lin) as applied to claim 1 above, and further in view of More, Shahaji et al. (Pub No. US 20220392894 A1) (hereinafter, More).
Re Claim 2, (Original) Kim teaches the semiconductor device of claim 1, wherein the epitaxial source/drain region (Semiconductor liner film/insertion film; 151/152; Fig 11; ¶[0103]) comprises two wing portions (Mountain/Valley portions of Semiconductor liner film and insertion film 151/152; Fig 11; ¶[0103]) extending from the fin portion, the inner profile is defined by the two wing portions.
However, Kim in view of Lin does not teach wherein the epitaxial source/drain region comprises a fin portion, the inner profile is defined by the fin portion.
In the same field of endeavor, More teaches wherein the epitaxial source/drain region (Epitaxial layers; 152/154A/156A; Fig 2H; ¶[0030]) comprises a fin portion (Epitaxial layers; 152; Fig 2H; ¶[0030]), the inner profile (Inner sidewalls of Epitaxial layers 152/154A/156A) is defined by the fin portion.
More, Fig 2H: Multigate device with fin portion beneath source drain regions
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the wing portions of the epitaxial source/drain regions as taught by Kim with the fin portion as taught by More. One would have been motivated to do this with a reasonable expectation of success because the fin portion provides a buffer between doped epitaxial layers and the semiconductor substrate, which can reduce short channel effects in multigate device. In some embodiments, the fin portion may be tuned based on active region size to mitigate short channel effects while optimizing performance (e.g., drive current), as suggested by More (¶[0030]).
Re Claim 3, (Original) Kim teaches the semiconductor device of claim 2, wherein the two or more channel layers (Sheet patterns; NS1; Fig 11; ¶[0032]) extend between a first vertical level (First vertical level; L1; See annotated Fig 11 below) and a second vertical level (Second vertical level; L2; See annotated Fig 11 below), and the first vertical level is above the second vertical level.
Kim, Fig 11: Annotation of 1st - 4th vertical levels and channel layers
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Re Claim 4, (Previously Presented) Kim teaches the semiconductor device of claim 3, wherein the source/drain contact feature (Source/drain contact/filling film/interlayer insulating film; 180/153/190; Fig 11; ¶[0234]) extends between a third vertical level (Third vertical level; L3; See annotated Fig 11 above) and a fourth vertical level (Fourth vertical level; L4; See annotated Fig 11 above), the third vertical level is above the fourth vertical level, and the second vertical level (Second vertical level; L2; See annotated Fig 11 above) is above the four vertical level.
Re Claim 5, (Original) Kim teaches the semiconductor device of claim 4, wherein the third vertical level (Third vertical level; L3; See annotated Fig 11 above) is above the first vertical level (First vertical level; L1; See annotated Fig 11 above).
12. Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Da Hye et al. (Pub No. US US 20230420519 A1) (hereinafter, Kim) in view of Ye, Hung-Yu et al. (Pub No. US 20220310787 A1) (hereinafter, Ye), and further in view of Lin, Sankuei et al. (Pub No. US 20220359208 A1) (hereinafter, Lin).
Re Claim 9, (Currently Amended) Kim teaches a semiconductor device, comprising:
a first source/drain region (Left hand side semiconductor liner film/insertion film; 151/152; Fig 11; ¶[0103]), wherein the first source/drain region has a first inner profile (Inner sidewalls of left side liner/insertion films 151/152; Fig 11);
a second source/drain region (Right hand side semiconductor liner film/insertion film; 151/152; Fig 11; ¶[0103]) disposed adjacent the first source/drain region, wherein the second source/drain region has a second inner profile (Inner sidewalls of right side liner/insertion films 151/152; Fig 11);
a first source/drain contact feature (Left side source/drain contact/filling film/interlayer insulating film; 180/153/190; Fig 11; ¶[0234]) disposed over the first inner profile of the first source/drain region, wherein the first source/drain contact feature extends from a first vertical level (First vertical level; See annotated Fig 11 below) above a topmost of the plurality of first channels (Sheet patterns; NS1; Fig 11; ¶[0032]) to a second vertical level (Second vertical level; See annotated Fig 11 below) below a lower most of the plurality of first channels; and
a second source/drain contact feature (Right side source/drain contact/filling film/interlayer insulating film; 180/153/190; Fig 11; ¶[0234]) disposed in the second inner profile of the second source/drain region.
However, Kim does not teach a forksheet structure comprising:
a plurality of first channels in contact with the first source/drain region;
a plurality of second channels in contact with the second source/drain region;
a dielectric wall disposed between the plurality of first channel and the plurality of second channels;
a first silicide layer disposed on the first inner profile of the first epitaxial source/drain region,
wherein the first silicide layer source/drain contact feature extends from a first vertical level above a topmost of the plurality of first channels to a second vertical level below a lower most of the plurality of first channels.
In the same field of endeavor, Ye teaches a forksheet structure (See Figs 36A/36B/37B below) comprising:
a plurality of first channels (Nanostructure layers; 505A/505B/505C; Fig 37B; ¶[0112]) in contact with the first source/drain region (Source/drain structures; 516S/516D; Figs 36A/36B; ¶[0112]);
a plurality of second channels (Nanostructure layers; 507A/507B/507C; Fig 37B; ¶[0112]) in contact with the second source/drain region (Source/drain structures; 518S/518D; Figs 36A/36B; ¶[0112]);
a dielectric wall (Dielectric wall; 511; Fig 37B; ¶[0112]) disposed between the plurality of first channel and the plurality of second channels;
Ye, Figs 36A/36B: Semiconductor device with source/drain regions
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Ye, Fig 37B: Channels connected to dielectric wall
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used first and second channel layers to contact a source/drain region with a dielectric wall disposed between said channel layers, as taught by Ye, for the semiconductor device of Kim. One would have been motivated to do this with a reasonable expectation of success because the dielectric wall electrically isolates the p-type fin structures from the n-type fin structures, leading to improved power and efficiency due to shorter n-type and p-type transistor spacing, as suggested by Ye (¶[0105]).
However, Kim in view of Ye does not teach a first silicide layer disposed on the first inner profile of the first epitaxial source/drain region,
wherein the first silicide layer source/drain contact feature extends from a first vertical level above a topmost of the plurality of first channels to a second vertical level below a lower most of the plurality of first channels.
In the same field of endeavor, Lin teaches a first silicide layer (Silicide layer; 322; Fig 3; ¶[0024]) disposed on the first inner profile (Inner profile of epitaxial material 306 shaped by silicide layer 322; Fig 3) of epitaxial source/drain region (Epitaxial material; 306; Fig 3; ¶[0025]),
wherein the first silicide layer extends from a first vertical level (Level above the topmost of channel layers 220; Fig 3) above a topmost of the plurality of first channels (Topmost channel layer; 220; Fig 3; ¶[0032]) to a second vertical level (Level lower than lowermost channel layer 220; Fig 3) below a lower most of the plurality of first channels (Lowermost channel layer; 220; Fig 3; ¶[0032]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a first silicide layer disposed on the first inner profile of the first epitaxial source/drain region, wherein the first silicide layer source/drain contact feature extends from a first vertical level above a topmost of the plurality of first channels to a second vertical level below a lower most of the plurality of first channels, as taught by Lin, with the semiconductor device as taught by Kim in view of Ye. One would have been motivated to do this with a reasonable expectation of success because the silicide layer extending along the topmost to lowermost channel layers allows for the length of the nanosheet channel layers between the source/drain regions to be controlled. Further, the silicide layer functions as a contact with lowered contact resistance for the source/drain regions (Lin; ¶[0024]).
Re Claim 10, (Original) Kim teaches the semiconductor device of claim 9, wherein the first source/drain contact feature (Left side source/drain contact/filling film/interlayer insulating film; 180/153/190; Fig 11; ¶[0234]) comprises an ILD portion (Interlayer insulating film; 190; Fig 11; ¶[0028]) disposed in an ILD layer (Interlayer insulating film; 190; Fig 11; ¶[0028]) and a core portion (Source/drain contact and filling film; 180/153; Fig 11; ¶[0234]) disposed in a first cavity (First source/drain recess and inner profile of filling film 153; 150R; Fig 11; ¶[0093]) defined by the first inner profile (Inner sidewalls of left side liner/insertion films 151/152; Fig 11).
Re Claim 11, (Original) Kim teaches the semiconductor device of claim 10, wherein the core portion (Source/drain contact and filling film; 180/153; Fig 11; ¶[0234]) of the first source/drain contact feature (Left side source/drain contact and filling film; 180/153; Fig 11; ¶[0234]) has an outer profile (Outside lining of filling film 153; Fig 11) matching the first inner profile (Inner sidewalls of left side liner/insertion films 151/152; Fig 11) of the first source/drain region (Left hand side semiconductor liner film/insertion film; 151/152; Fig 11; ¶[0103]).
Re Claim 12, (Original) Kim teaches the semiconductor device of claim 11, wherein the ILD portion (Interlayer insulating film; 190; Fig 11; ¶[0028]) has a first width (Width of ILD 190; Fig 11), and the core portion (Source/drain contact and filling film; 180/153; Fig 11; ¶[0234]) has a second width (Width of filling film 153; Fig 11), and the second width is wider than the first width.
Re Claim 13, (Original) Kim teaches thesemiconductor device of claim 11, wherein the first inner profile (Inner sidewalls of left side liner/insertion films 151/152; Fig 11) includes a plurality of valley sections (Valleys of inner profile of 151/152; See Fig 11 annotation) alternatively connected between a plurality of mountain sections (Mountains of inner profile of 151/152; See Fig 11 annotation).
Re Claim 14, (Original) Kim teaches the semiconductor device of claim 10, further comprising a sacrificial epitaxial source/drain region (Upper portion of semiconductor filling film 153; Fig 32) disposed around the first source/drain contact feature (Source/drain contact; 180; Fig 11; ¶[0234]).
Allowable Subject Matter
13. Claims 18 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 18 the closest prior art Kim, Da Hye et al. (Pub No. US 20230420519 A1) (hereinafter, Kim) in view of Wang, Wei Ren et al. (Pub No. KR 20230052196 A) (hereinafter, Wang) either singularly or in combination fails to anticipate or render obvious
“The method of claim 15,
wherein the etch stop layer comprises a semiconductor material, and a silicide layer is formed from the etch stop layer.”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 18, Kim discloses an etch stop layer comprising of semiconductor material, however Kim does not disclose a silicide formed from the etch stop layer of claim 15. Furthermore, Wang discloses a silicide region formed through an etch stop layer, but it would not be obvious to form the silicide region from the etch stop layer given the invention of Kim in view of Wang. Finally, referring to Figure 11 of Kim, it would not provide any advantages to the invention of Kim to form a silicide from the etch stop layer because the silicide 175 is intended to be a point of reduced contact resistance between an epitaxial material and a contact, whereas forming a silicide from the etch stop layer would render forming the epitaxial layer 153 meaningless because epitaxial layer 153 not considered a contact.
Regarding claim 22 the closest prior art Kim, Da Hye et al. (Pub No. US 20230420519 A1) (hereinafter, Kim) either singularly or in combination fails to anticipate or render obvious
“The method of claim 15, further comprising removing the etch stop layer prior to forming the silicide layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 22, Kim discloses an etch stop layer comprising of semiconductor material, however, referring to Figure 11 of Kim, the etch stop layer is anticipated by the semiconductor material 152, which must be present before forming the silicide 155, therefore there can be no combination of prior art would render it obvious to remove the etch stop layer prior to forming the silicide layer.
Conclusion
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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