DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 10/20/2025 has been accepted and entered. Claims 1-19 remain pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), and further in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10).
Regarding claim 1, Tsau64 discloses a method of manufacturing an electronic device ([0005], Fig 1), the method comprising:
treating a surface of a metal gate stack (Step 102 removing a dummy gate structure and exposing an interfacial layer so treating a surface of the metal gate, Fig 1) by flowing a metal-containing precursor (metal precursor 310 is delivered via an inert gas-[0031] L 7-8),
the metal gate stack comprising an interfacial layer on a top surface of a channel located between a source and a drain on a substrate (Interfacial layer 232 on top of a channel 204 located between a source 214 and a drain 214 on a substrate 202-Examiner's annotated Fig 3A),
Tsau64 does not discloses a method of manufacturing an electronic device wherein
flowing a metal-containing precursor over the surface of the metal gate stack,
to form a treated interfacial layer having metal atoms formed thereon and
depositing a high-K dielectric layer directly on the treated interfacial layer.
Chang04 teaches a method of manufacturing an electronic device comprising
to form a treated interfacial layer having metal atoms formed thereon (Step 106, form dipole pattern, step 108, drive material to first high k layer to form 282p, step 112 form a second high-k layer, so treating interfacial layer 104 having metal formed thereon-Fig 2, Fig 1)
depositing a high-K dielectric layer directly on the treated interfacial layer (Step 106, form dipole pattern, step 108, drive material to first high k layer 282p, step 112 form a second high-k layer 284, so treating interfacial layer IL having metal formed thereon 282p, and depositing high-k layer 284 directly on the treated interfacial layer IL+282P-Fig 2, Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Tsau64 and Chang04 combination does not disclose a method of manufacturing an electronic device comprising
flowing a metal-containing precursor over the surface of the metal gate stack,
NPLArimura10 teaches a method of manufacturing an electronic device comprising
flowing a metal-containing precursor over the surface of the metal gate stack (Metal sputtering on interfacial layer SiO2 so flowing a metal-containing precursor over the surface of the metal gate stack-page 1, C1, §3, L1-7, Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of Chang04, as taught by NPLArimura10 for the purpose of forming effective work function adjustment in metal/high-k stack (NPLarimura10: page 1, C1, §1, L1-3).
Regarding claim 2, Tsau64, Chang04, and NPLArimura10 combination discloses all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device
wherein the interfacial layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx),doped silicon, doped silicon oxide, or spin-on dielectrics (Silicon oxide-[0033] L12-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 3, Tsau64, Chang04, and NPLArimura10 combination discloses all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device
wherein the high-K dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx) (Layer 284 includes hafnium oxide-[0041] L 10-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 5, Tsau64, Chang04, and NPLArimura10 combination discloses all the elements of claim 1, as noted above.
Tsau64 further discloses a method of manufacturing an electronic device
wherein the metal-containing precursor is carried to the surface of the metal gate stack by an inert gas (metal precursor 310 is delivered via an inert gas-[0031] L 7-8).
Regarding claim 6, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
NPLArimura10 further teaches a method of manufacturing an electronic device
wherein the metal-containing precursor comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr),yttrium (Y), zirconium (Zr), or caesium (Cs) (Metal-La sputtering on interfacial layer SiO2 so the metal-containing precursor comprising lanthanum (La)-page 1, C1, §3, L1-7, Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of Chang04, as taught by NPLArimura10 for the purpose of forming effective work function adjustment in metal/high-k stack (NPLarimura10: page 1, C1, §1, L1-3).
Regarding claim 7, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
NPLArimura10 further teaches a method of manufacturing an electronic device
wherein the metal-containing precursor comprises one or more of lanthanum (La) or caesium (Cs) (Metal-La sputtering on interfacial layer SiO2 so the metal-containing precursor comprising lanthanum (La)-page 1, C1, §3, L1-7, Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of Chang04, as taught by NPLArimura10 for the purpose of forming effective work function adjustment in metal/high-k stack (NPLarimura10: page 1, C1, §1, L1-3).
Regarding claim 8, Tsau64, Chang04, and NPLArimura10 combination discloses all the elements of claim 1, as noted above.
Tsau64 further discloses a method of manufacturing an electronic device
wherein the metal-containing precursor comprises one or more of aluminum (AI), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo) (metal-containing precursor comprises Titanium-[0031] L 13).
Regarding claim 9, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the metal-containing precursor comprises one or more of aluminum (AI) or gallium (Ga) (metal-containing precursor comprises Aluminum or Gallium-[0012] L27-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NLPArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 11, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the channel comprises n-type material (Channel layer comprising n-type material 215n-Fig 1, [0011] L4-7 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64, in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 12, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the channel comprises p-type material (Channel layer comprising p-type material 215p-Fig 1, [0011] L4-7 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 13, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
further comprising flowing the metal-containing precursor over the surface of the high-K dielectric layer to form a dipole layer on the high-K dielectric layer (Step 106-Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 14, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 13, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
further comprising forming a metal gate layer on the dipole layer (metal gate layer 430 on dipole layer 279n/p-Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 15, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 14, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the metal gate layer comprises one or more of amorphous silicon, a metal, a metal carbide, a metal nitride, or a metal oxide (metal gate layer 430 comprises metal(s), such as Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi2, MoSi2, TaSi2, NiSi2, or combinations thereof-[0051] L 27-31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 16, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 15, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the metal gate layer comprises one or more of titanium aluminum carbide (TiAIC) or titanium nitride (TiN) (metal gate layer 430 comprises metal(s), such as Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi2, MoSi2, TaSi2, NiSi2, or combinations thereof-[0051] L 27-31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 17, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 15, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the metal gate layer has a thickness in a range of from 10 A to 30 A (metal grate layer 430 has a thickness of about 1 nm to about 5 nm so in a range of 10 A to 30 A-[0051] L 32-33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 18, Tsau64, Chang04, and NPLArimura10 combination teaches all the elements of claim 1, as noted above.
Chang04 further teaches a method of manufacturing an electronic device,
wherein the electronic device is a gate-all- around (GAA) device (Fig 3B-18B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of NPLArimura10, as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Regarding claim 19, Tsau64 discloses a method of manufacturing an electronic device ([0005], Fig 1), the method comprising:
treating a surface of a metal gate stack (Step 102 removing a dummy gate structure and exposing an interfacial layer so treating a surface of the metal gate, Fig 1) by
flowing a metal-containing precursor carried by an inert gas (metal precursor 310 is delivered via an inert gas-[0031] L 7-8),
the metal gate stack comprising an interfacial layer on a top surface of a channel located between a source and a drain on a substrate (Interfacial layer 232 on top of a channel 204 located between a source 214 and a drain 214 on a substrate 202-Examiner's annotated Fig 3A),
to form a treated interfacial layer having metal atoms formed thereon (Interfacial layer 236 is a metal-containing layer so having metal atoms thereon-Fig 1, Fig 5, [0031] L1-3),
the high-K dielectric layer comprising hafnium oxide (HfOx) (Layer 234 include hafnium oxide-[0030] L 17).
Tsau64 does not discloses a method of manufacturing an electronic device wherein
flowing a metal-containing precursor over the surface of the metal gate stack,
an interfacial layer comprising silicon oxide (SiOx)
the metal-containing precursor comprising one or more of aluminum (AI), lanthanum (La), caesium (Cs), or gallium (Ga); and
depositing a high-K dielectric layer directly on the treated interfacial layer.
Chang04 teaches a method of manufacturing an electronic device wherein
an interfacial layer comprises silicon oxide (SiOx) (Silicon oxide-[0033] L12-15),
the metal-containing precursor comprising one or more of aluminum (AI), lanthanum (La), caesium (Cs), or gallium (Ga) (Aluminum or Gallium-[0012] L27-29),
depositing a high-K dielectric layer directly on the treated interfacial layer (Step 106, form dipole pattern, step 108, drive material to first high k layer 282p, step 112 form a second high-k layer 284, so treating interfacial layer IL having metal formed thereon 282p, and depositing high-k layer 284 directly on the treated interfacial layer IL+282P-Fig 2, Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 as taught by Chang04 for the purpose of reducing power consumption and boosting device performance (Chang04:[0015] L3-4).
Tsau64 and Chang04 combination does not disclose a method of manufacturing an electronic device comprising
flowing a metal-containing precursor over the surface of the metal gate stack,
NPLArimura10 teaches a method of manufacturing an electronic device comprising
flowing a metal-containing precursor over the surface of the metal gate stack (Metal sputtering on interfacial layer SiO2 so flowing a metal-containing precursor over the surface of the metal gate stack-page 1, C1, §3, L1-7, Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of Chang04, as taught by NPLArimura10 for the purpose of forming effective work function adjustment in metal/high-k stack (NPLarimura10: page 1, C1, §1, L1-3).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), in view of Manabe et al. (US 20100327366 A1-Manabe66), in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), and further in view of Cheng et al. (US 20210098457 A1-Cheng83).
Regarding claim 4, Tsau64, Chang04, Manabe66, and NPLArimura10 combination discloses all the elements of claim 1, as noted above.
Tsau64, Chang04, Manabe66, and NPLArimura10 combination does not teach a method of manufacturing an electronic device
wherein the high-K dielectric layer comprises hafnium oxide (HfOx) and is formed by exposing the treated interfacial layer to hafnium tetrachloride (HfCl4) and water (H2O).
Cheng83 teaches a method of manufacturing an electronic device
wherein the high-K dielectric layer comprises hafnium oxide (HfOx) and is formed by exposing the treated interfacial layer to hafnium tetrachloride (HfCl4) and water (H2O) ([0081] L13-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of Chang04, in view of Manabe66, and further in view of NPLArimura10 as taught by Cheng83 for the purpose of forming ultra-low threshold voltage n-type devices and/or standard threshold voltage p-type devices (Cheng83: [0082] L14-16).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), in view of Manabe et al. (US 20100327366 A1-Manabe66), in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), and further in view of Lee et al. (US 20120285481 A1-Lee81).
Regarding claim 10, Tsau64, Chang04, Manabe66, and NPLArimura10 combination teaches all the elements of claim 3, as noted above.
Tsau64, Chang04, Manabe66, and NPLArimura10 combination does not teach a method of manufacturing an electronic device
wherein treating the surface of the metal gate stack occurs at a temperature in a range of from greater than or equal to 150 °C to less than or equal to 500 °C, a pressure of about 80 Torr, and a time period of from less than or equal to 10 seconds to less than or equal to 120 seconds.
Lee81 teaches a method of manufacturing an electronic device
wherein treating the surface of the metal gate stack occurs at a temperature in a range of from greater than or equal to 150 °C to less than or equal to 500 °C, a pressure of about 80 Torr, and a time period of from less than or equal to 10 seconds to less than or equal to 120 seconds (Temperature less than 760 °C so included a range of from greater than or equal to 150 °C to less than or equal to 500 °C-claim 10,[0044]; a process pressure in the chamber at between about 1 Torr and about 120 Torr so about 80 Torr-Claim 1, [0044]; about 1 seconds and about 36000 seconds so a time period of from less than or equal to 10 seconds to less than or equal to 120 seconds-[0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing an electronic device of Tsau64 in view of Chang04, in view of Manabe66, and further in view of NPLArimura10, as taught by Lee81 for the purpose of improving method of removing or cleaning substrate surface (Lee81:[0011]).
Response to Arguments
Applicant’s arguments see pages 7-12 of Remarks, filed on 02/09/2026 with respect to the newly added limitation for claim 1 and claim 9, these limitations have not been previously presented in the set of claims associated with the office action mailed on 10/20/2026. These new claims limitations are addressed in the rejections written above. Additionally, the arguments have been considered as following:
Applicant’s arguments shows that Tsau et al. (US20200119164A1-Tsau64) teaches at operation 106, depositing a metal-containing layer 236 over the high-K dielectric layer 234, and does not disclose, teach, or suggest forming a treated interfacial layer followed by depositing a high-K dielectric layer thereon. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Applicant’s arguments shows that Chang et al. (US 20210399104 A1-Chang04) relates to a dipole last process, which needs an annealing process. However the claim limitation does not include having or not an annealing process, the limitation recites “depositing a high-K dielectric layer directly on the treated interfacial layer”. Chang04 teaches a method of manufacturing an electronic device comprising depositing a high-K dielectric layer directly on the treated interfacial layer (Step 106, form dipole pattern, step 108, drive material to first high k layer 282p, step 112 form a second high-k layer 284, so treating interfacial layer IL having metal formed thereon 282p, and depositing high-k layer 284 directly on the treated interfacial layer IL+282P-Fig 2, Fig 1), as discussed in the claim rejection above.
Applicant’s arguments see pages 7-12 of Remarks, filed on 02/09/2026 with respect to claim 2-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims 1, 4, 7, 9, 10, 13, and 19 have been amended to further define the claimed subject matter see pages 4-7 of Amendments to Claims, filed on 10/20/2025.
Claim(s) 1-3, 5-9, 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), and further in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), as described above.
Therefore, claims 1-3, 5-9, 11-19 stand rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), and further in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), in view of Manabe et al. (US 20100327366 A1-Manabe66), in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), and further in view of Cheng et al. (US 20210098457 A1-Cheng83), as described above.
Therefore, claim 4 stands rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), and further in view of Cheng et al. (US 20210098457 A1-Cheng83).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), in view of Manabe et al. (US 20100327366 A1-Manabe66), in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), and further in view of Lee et al. (US 20120285481 A1-Lee81), as described above.
Therefore, claim 10 stands rejected under 35 U.S.C. 103 as being unpatentable over Tsau et al. (US20200119164A1-Tsau64) in view of Chang et al. (US 20210399104 A1-Chang04), in view of Arimura et al. (Appl. Phys. Lett. 96, 132902 (2010)-NPLArimura10), and further in view of Lee et al. (US 20120285481 A1-Lee81).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Manabe et al. (US 20100327366 A1-Manabe66) teaches a method of manufacturing an electronic device comprising:
to form a treated interfacial layer having metal atoms formed thereon (Metal oxide layer with metal atoms on top of treated interfacial layer 107-Fig 1) and
depositing a high-K dielectric layer directly on the treated interfacial layer (selectively forming a second adjusting metal layer 109a over the interfacial layer 107 of the gate stack followed by formation of the high-k gate insulating film 108 over the second adjusting metal 109a, so treating a surface of a metal stack 107-Fig 1 [0129]).
Cheng et al. (US 20210242092 A1) ) teaches a method of manufacturing an electronic device comprising:
to form a treated interfacial layer having metal atoms formed thereon (Forming a dipole layer directly on an interfacial layer-[0012], [0030]),
the metal- containing precursor comprising one or more of aluminum (AI), lanthanum (La),caesium (Cs), or gallium (Ga) (La2)3 so La-[0031], [0032]); and
depositing a high-K dielectric layer directly on the treated interfacial layer (High k dielectric layer 430 deposed on treated interfacial layer 210-Fig 10D).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 03/12/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812