DETAILED ACTION
This action is responsive to the amendment received January 22, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The prior §112 rejections are withdrawn in view of the amended claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nomura et al. (US 2008/0017965).
(Re Claim 1) Nomura teaches a semiconductor device, comprising (see Figs. 15A-C and supporting text):
a first circuit area (11) disposed over a substrate (1) and enclosed by a first seal ring structure (13);
a second circuit area (12) disposed over the substrate and enclosed by a second seal ring structure (14);
an internal scribe line (16) disposed between the first circuit area and the second circuit area; and
connecting seal structures (15) connecting the first seal ring structure and the second seal ring structures such that a part of the first seal ring structure, a part of the second seal ring structure and the connecting seal structures enclose the internal scribe line).
a first connecting seal structure (portion of 15, see figure below) including a first end connected to a first corner of the first seal ring structure and a second end connected to a first corner of the second seal ring structure; and
a second connecting seal structure (portion of 15, see figure below) including a first end connected to a second corner of the first seal ring structure and a second end connected to a second corner of the second seal ring structure,
wherein a part of the first seal ring structure, a part of the second seal ring structure, and the first and second connecting seal structures enclose the internal scribe line (see Figs. 15A-C, ¶¶75-78, 15 is common to/part of 13 and 14).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7-10, 12, 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. (US 2008/0017965).
(Re Claim 2) further comprising a third seal ring structure enclosing the first circuit area and the second circuit area.
In Nomura’s third embodiment, a third seal ring is not disclosed, however in the fifth embodiment (see Fig. 17), the third seal ring 15 can be formed as a double seal ring. Nomura also discloses the features of the different embodiments may be combined as desired (¶¶87-88). A PHOSITA would recognize that any one or all of the seal rings may be formed in duplicate to provide added protection and/or redundancy should one of the seals fail, and another outer 15 may obviously be added to the Fig. 15 embodiment for these reasons. This would add an additional ring of protection while not wasting valuable circuit area by not forming 13 and 14 as double rings.
(Re Claim 7) wherein: each of the first seal ring structure, the second seal ring structure, the first connecting seal structure, and the second connecting seal structure is composed of a first to (N-1)-th metal wire patterns vertically arranged and vias connecting vertically adjacent wire patterns, and the third seal ring structure is composed of an N-th wire pattern.
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14. Figs. 8-14 showing the seal rings are formed of a multilayer wiring pattern (e.g. PS1-LS6), noting 15 is common to/part of 13 and 14, and the layers ascribed to the first and second seal rings can arbitrarily be the plurality of lower N-M layers (e.g. PS1-PS6 or LS5-PS1, etc.). As modified above, the duplicate outer ring 15 comprises the LS6 feature in the uppermost layer of the wiring pattern corresponding to the Nth layer.
(Re Claim 8) further comprising a pad electrode composed of a wiring pattern in the N-th wiring pattern (see 22/LS6 in Figs. 13A-14).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
(Re Claim 9) wherein the N-th wiring pattern is an uppermost wiring layer of the semiconductor device (see Figs. 8-14 and discussion above, Nth wiring layer at LS6).
(Re Claim 10) further includes a connection pattern (17) connecting a circuit in the first circuit area and a circuit in the second circuit area and bridging over the internal scribe line.
(Re Claim 12) wherein no functional circuit is disposed in the internal scribe line (no functional circuits are disclosed or shown in any scribe lines, see entire disclosure).
(Re Claim 21) Nomura teaches a semiconductor device, comprising (see Figs. 15A-C and ¶¶75-78):
a first circuit (11) surrounded by a first lower seal ring structure (13); a second circuit (12) surrounded by a second lower seal ring structure (14);
a first connecting seal structure (portion of 15, see figure above) including a first end connected to a first corner of the first lower seal ring structure and a second end connected to a first corner of the second lower seal ring structure;
a second connecting seal structure (portion of 15, see figure above) including a first end connected to a second corner of the first lower seal ring structure and a second end connected to a second corner of the second lower seal ring structure;
a scribe line (16) separating the first lower seal ring structure from the second lower seal ring structure; and
an upper seal ring structure (15) formed on the first and second lower seal ring structures and the first and second connecting seal structures (Figs. 15A-15C).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14. Figs. 15A-C showing the three ring structures and cross sections in Figs. 8-12 and 14 showing how the rings 13-15 are formed in a multilayer interconnect structure. The third ring 15 overlaps and is common with/part of the first and second rings 13/14 (¶¶75-78), and may be arbitrarily ascribed to an upper layer(s) of the ring structure(s) while the first and second lower ring structures may be ascribed to lower layer(s) of the ring structures.
(Re Claim 22) wherein the upper seal ring structure covers the first and second connecting seal structures, covers three sides of the first lower seal ring structure and covers three sides of the second lower seal ring structure (Figs. 15A-C).
(Re Claim 23) further comprising circuit connection patterns (17) connecting the first circuit and the second circuit.
(Re Claim 24) wherein the circuit connection patterns (17) bridge the scribe line (Figs. 15A-C).
(Re Claim 25) Nomura teaches a semiconductor device, comprising (see Figs. 15A-C and ¶¶75-78, also note details of the circuit areas including ILDs, wiring layers, and transistors in Figs. 6A-11 and 13A-14):
a first region (11) including first multiple wiring layers connected to a first transistor (see Figs. 8, 12, and 14 showing multiple wiring layers connected to a transistor);
a first seal structure (13) around the first region;
a second region (12) including second multiple wiring layers connected to a second transistor (see Figs. 8, 12, and 14 showing multiple wiring layers connected to a transistor);
a second seal structure (14) around the second region;
a scribe line (16) between the first and second seal structures;
a first connecting seal (portion of 15, see figure above) including a first end connected to a first corner of the first seal structure and a second end connected to a first corner of the second seal structure; and
a second connecting seal (portion of 15, see figure above) including a first end connected to a second corner of the first seal structure and a second end connected to a second corner of the second seal structure, the first and second connecting seals and the first and second seal structures enclose the scribe line in a plan view (Figs. 15A-15C).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILDs, transistors, and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
(Re Claim 26) further comprising circuit connection patterns (17) connecting the first region and the second region, wherein the circuit connection patterns bridge the scribe line (Figs. 15A-C).
(Re Claim 27) further comprising a first pad layer on the first multiple wiring layers and a second pad layer on the second multiple wiring layers (see pads 22 in Figs. 13A-14).
(Re Claim 28) further comprising one or more interlayer dielectric layers formed on the first and second transistors (see Figs. 8-14, D1-D8).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. (US 2008/0017965) as applied above, and further in view of Ramachandran et al. (US 2023/0040308), Aleksov et al. (US 2012/0007211), and Burton et al. (US 2020/0066651).
(Re Claim 11) wherein the connection pattern is composed of a wiring pattern in an uppermost wiring layer of the semiconductor device.
Nomura does not disclose an example wherein the connection pattern is composed of a wiring pattern in an uppermost wiring layer of the semiconductor device. A PHOSITA would recognize the connection patterns are simply additional wiring patterns formed in the multilayer wiring patterns/ILD layers and can be formed at any level in the structure, including the uppermost layer, and will provide the desired function of connecting the circuits in different areas regardless of the elevation within the interconnect structure. Related art from Ramachandran teaches the connection patterns 140 can be formed in the uppermost layer of the wiring patterns, see Figs. 9-10 and 13-14. Related art from Burton also similarly teaches the connection patterns 324 can be formed in the uppermost layer of the wiring patterns, see Figs. 3A-3B. Related art from Aleksov also teaches the connection patterns, e.g. 342/350 can be formed in the uppermost layer of the wiring patterns, see Figs. 5-10. In view of the prior art, a PHOSITA would recognize that the connection patterns can be formed in the uppermost wiring patterns. This would allow for the lower rings to be formed continuously from the substrate all the way up to the highest metal layers thereby providing better protection.
--- Rejection 2 ----
Claims 1-3, 5-7, 9, 12, 21, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oishi et al. (US 2018/0350858).
(Re Claim 1) Oishi teaches a semiconductor device, comprising (see Figs. 41-43 and corresponding text):
a first circuit area (711L) disposed over a substrate (701) and enclosed by a first seal ring structure (712L);
a second circuit area (711R) disposed over the substrate and enclosed by a second seal ring structure (712R);
an internal scribe line (42) disposed between the first circuit area and the second circuit area; and
a first connecting seal structure (part of 713 between 712L and 712R in region C1) including a first end connected to a first corner of the first seal ring structure and a second end connected to a first corner of the second seal ring structure (the features are connected to one another, connected to may be indirect, e.g. through an intervening layer(s), connected to does not require direct contact or electrical connection, or to be continuous or contiguous, etc.); and
a second connecting seal structure (part of 713 between 712L and 712R in region C2) including a first end connected to a second corner of the first seal ring structure and a second end connected to a second corner of the second seal ring structure,
wherein a part of the first seal ring structure, a part of the second seal ring structure, and the first and second connecting seal structures enclose the internal scribe line (Figs. 41-43).
(Re Claim 2) further comprising a third seal ring structure enclosing the first circuit area and the second circuit area (upper layer(s) of 713a, e.g. 722-2 or 725-1 and up or just 722-3).
(Re Claim 3) each of the first seal ring structure, the second seal ring structure, the first connecting seal structure, and the second connecting seal structure is composed of wiring patterns in a first to (N-M)-th wiring layers vertically arranged relative to a main surface of the substrate and vias connecting vertically adjacent wiring patterns, and the third seal ring structure is composed of wiring patterns in a (N-M+1)-th to an N-th wiring layers vertically arranged and vias connecting vertically adjacent wiring patterns, where M <N (see Fig. 43).
(Re Claim 5) wherein the N-th wiring layer is an uppermost wiring layer of the semiconductor device (Fig. 43, layer 722-3).
(Re Claim 6) wherein M is 2 or 3 (Fig. 43, M may be 2 or 3 depending on what layer is arbitrarily ascribed to the first wiring layer).
(Re Claim 7) wherein: each of the first seal ring structure, the second seal ring structure, the first connecting seal structure, and the second connecting seal structure is composed of a first to (N-1)-th metal wire patterns vertically arranged and vias connecting vertically adjacent wire patterns, and the third seal ring structure is composed on an N-th wire pattern (Fig. 43).
(Re Claim 9) wherein the N-th wiring pattern is an uppermost wiring pattern of the semiconductor device (Fig. 43, layer 722-3).
(Re Claim 12) wherein no functional circuit is disposed in the internal scribe line (no functional circuits are disclosed or shown in any scribe lines, see entire disclosure).
(Re Claim 21) Oishi teaches a semiconductor device, comprising (see Figs. 41-43 and corresponding text):
a first circuit (711L) surrounded by a first lower seal ring structure (712L);
a second circuit (711R) surrounded by a second lower seal ring structure (712R);
a first connecting seal structure (part of 713 between 712L and 712R in region C1) including a first end connected to a first corner of the first lower seal ring structure and a second end connected to a first corner of the second lower seal ring structure (the features are connected to one another, connected to may be indirect, e.g. through an intervening layer(s), connected to does not require direct contact or electrical connection, or to be continuous or contiguous, etc.);
a second connecting seal structure (part of 713 between 712L and 712R in region C2) including a first end connected to a second corner of the first lower seal ring structure and a second end connected to a second corner of the second lower seal ring structure;
a scribe line (42) separating the first lower seal ring structure from the second lower seal ring structure; and
an upper seal ring structure (713a) formed on the first and second lower seal ring structures and the first and second connecting seal structures (Figs. 41-43).
(Re Claim 22) wherein the upper seal ring structure covers the first and second connecting seal structures, covers three sides of the first lower seal ring structure, and covers three sides of the second lower seal ring structure (Figs. 41-43).
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi et al. (US 2018/0350858) as applied above and further in view of Nomura et al. (US 2008/0017965), Furumiya et al. (US 2010/0164053), and Pichumani et al. (US 2013/0280530).
(Re Claim 4) further comprising a pad electrode composed of a wiring pattern in the N-th wiring layer.
(Re Claim 8) further comprising a pad electrode composed of a wiring pattern in the N-th wiring pattern.
Oishi is silent regarding a pad electrode composed of a wiring pattern in the N-th wiring layer. A PHOSITA would recognize Oishi’s device shown in Figs. 41-43 is obviously an overly simplified depiction lacking many details, e.g. the circuits, wiring layers, ILD layers, transistors, I/O pads, etc. A PHOSITA desiring to make, use, and improve upon Oishi’s device would be motivated to look to related art to teach additional details for a device where Oishi is silent. Related art from Nomura teaches a pad may be formed in the uppermost Nth layer of a multilayer wiring pattern (Figs. 13A-14, 22/L6). Related art from Furumiya also teaches forming pads 16 in the uppermost Nth wiring layer of a multilayer wiring pattern (Figs. 1-2). Related art from Pichumani also teaches forming pads in the uppermost Nth wiring layer of a multilayer wiring pattern. In view of the prior art, a PHOSITA would find it obvious to similarly form pads in Oishi’s devices for making electrical connections to the devices. Forming the pads in the upper layers provides easy access and the pads can be made larger to facilitate bonding.
Claims 10, 11, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi et al. (US 2018/0350858) as applied above and further in view of Ramachandran et al. (US 2023/0040308), Aleksov et al. (US 2012/0007211), and Burton et al. (US 2020/0066651).
(Re Claim 10) further includes a connection pattern (17) connecting a circuit in the first circuit area and a circuit in the second circuit area and bridging over the internal scribe line.
(Re Claim 11) wherein the connection pattern is composed of a wiring pattern in an uppermost wiring layer of the semiconductor device.
(Re Claim 23) further comprising circuit connection patterns connecting the first circuit and the second circuit.
(Re Claim 24) wherein the circuit connection patterns bridge the scribe line.
Oishi is silent regarding a connection pattern in the embodiment of Figs. 41-43, however in other embodiments Oishi discloses forming connection patterns (e.g. 662-1, 662-2, 662-3) between the circuit regions, bridging the scribe lines, wherein the connection patterns are formed in the uppermost wiring patterns, see Figs. 27 and 31. A PHOSITA would find it obvious to form the connection patterns in the uppermost wiring layer as shown to provide electrical connections between the circuit regions of the devices. Furthermore, a PHOSITA would recognize the connection patterns are simply additional wiring patterns formed in the multilayer wiring patterns/ILD layers and can be formed at any level in the structure, including the uppermost layer, and will provide the desired function of connecting the circuits in different areas regardless of the elevation within the interconnect structure. Related art from Ramachandran teaches the connection patterns 140 can be formed in the uppermost layer of the wiring patterns, see Figs. 9-10 and 13-14. Related art from Burton also similarly teaches the connection patterns 324 can be formed in the uppermost layer of the wiring patterns, see Figs. 3A-3B. Related art from Aleksov also teaches the connection patterns, e.g. 342/350 can be formed in the uppermost layer of the wiring patterns, see Figs. 5-10. In view of the prior art, a PHOSITA would recognize that the connection patterns can be formed in the uppermost wiring patterns. This would allow for the lower rings to be formed continuously from the substrate all the way up to the highest metal layers thereby providing better protection.
Claims 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi et al. (US 2018/0350858) as applied above and further in view of Nomura et al. (US 2008/0017965)
(Re Claim 25) Oishi teaches a semiconductor device, comprising (see Figs. 41-43 and corresponding text):
a first region including first multiple wiring layers connected to a first transistor (first circuit region 711L, wiring layers and transistors discussed below);
a first seal structure (712L) around the first region;
a second region including second multiple wiring layers connected to a second transistor (first circuit region 711R, wiring layers and transistors discussed below);
a second seal structure (712R) around the second region;
a scribe line (42) between the first and second seal structures;
a first connecting seal (part of 713 between 712L and 712R in region C1) including a first end connected to a first corner of the first seal structure and a second end connected to a first corner of the second seal structure (the features are connected to one another, connected to may be indirect, e.g. through an intervening layer(s), connected to does not require direct contact or electrical connection, or to be continuous or contiguous, etc.); and
a second connecting seal (part of 713 between 712L and 712R in region C2) including a first end connected to a second corner of the first seal structure and a second end connected to a second corner of the second seal structure, the first and second connecting seals and the first and second seal structures enclose the scribe line in a plan view (Figs. 41-43).
Oishi discloses the circuit regions however does not provide details of these regions. A PHOSITA would recognize Oishi’s device shown in Figs. 41-43 is obviously an overly simplified depiction lacking many details, e.g. the circuits, wiring layers, ILD layers, transistors, I/O pads, etc. A PHOSITA desiring to make, use, and improve upon Oishi’s device would be motivated to look to related art to teach additional details for a device where Oishi is silent. Related art from Nomura teaches the circuit regions of semiconductor devices conventionally include transistors connected to wiring layers in ILD layers of a multilayer interconnect structure (see Figs. 8-14). A PHOSITA would find it obvious to include transistors connected through wiring layers separated by ILD layers in the disclosed circuit regions according to Nomura since this allows for functional integrated circuits to be formed allowing for connections to be made throughout a 3D interconnect structure. This saves valuable circuit/substrate area thereby allowing for higher density and smaller circuits to be formed. Interconnect structures are well known in the art and have been standard practice for decades.
(Re Claim 26) further comprising circuit connection patterns connecting the first region and the second region, wherein the circuit connection patterns bridge the scribe line.
Oishi is silent regarding a connection pattern in the embodiment of Figs. 41-43, however in other embodiments Oishi discloses forming connection patterns 662-1, 662-2, 662-3, between the circuit regions, bridging the scribe lines, wherein the connection patterns are formed in the uppermost wiring patterns, see Figs. 27 and 31.
Related art from Nomura also discloses forming connection patterns 17 to connect adjacent circuit regions (Figs. 6C, 13C, 15C). The connection patterns enable multiple circuit regions to be connected to form larger multichip modules as desired with increased functionality without needing conventional interposers and/or RDLs.
(Re Claim 27) further comprising a first pad layer on the first multiple wiring layers and a second pad layer on the second multiple wiring layers.
Oishi is silent regarding pads on the multiple wiring patterns. A PHOSITA would recognize Oishi’s device shown in Figs. 41-43 is obviously an overly simplified depiction lacking many details, e.g. the circuits, wiring layers, ILD layers, transistors, I/O pads, etc. A PHOSITA desiring to make, use, and improve upon Oishi’s device would be motivated to look to related art to teach additional details for a device where Oishi is silent. Related art from Nomura teaches a pad may be formed on the multilayer wiring patterns (Figs. 13A-14, 22/L6). In view of the prior art, a PHOSITA would find it obvious to similarly form pads in Oishi’s devices for making electrical connections to the devices. Forming the pads in the upper layers as shown by Nomura provides easy access and the pads can be made larger to facilitate bonding.
(Re Claim 28) further comprising one or more interlayer dielectric layers formed on the first and second transistors (as modified above, see Nomura Figs. 8-14, D1-D8).
Response to Arguments
Applicant's arguments filed January 22, 2026, have been fully considered but they are not persuasive. Applicant argues the prior art used in the rejections above does not teach the amended limitations regarding the first and second connecting seals. The Examiner respectfully disagrees, see updated rejections above. Nomura’s portions of 15 identified above, and Oishi’s portions of 713 between 712L and 712R in regions C1 and C2 meet the limitations of the first and second connecting seals.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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