DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 6, 2026, has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 8, 10, 12, and 21-32 are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. (US 2008/0017965), of record.
(Re Claim 1) Nomura teaches a semiconductor device, comprising (see Figs. 15A-C and supporting text):
a first circuit area (11) disposed over a substrate (1) and enclosed by a first seal ring structure (13);
a second circuit area (12) disposed over the substrate and enclosed by a second seal ring structure (14);
an internal scribe line (16) disposed between the first circuit area and the second circuit area; and
a first connecting seal structure (portion of 15, see figure below) including a first end connected to a first corner of the first seal ring structure and a second end connected to a first corner of the second seal ring structure; and
a second connecting seal structure (portion of 15, see figure below) including a first end connected to a second corner of the first seal ring structure and a second end connected to a second corner of the second seal ring structure; and
a third seal ring structure (upper layer(s) of 15) enclosing the first circuit area and the second circuit area,
wherein a part of the first seal ring structure, a part of the second seal ring structure, and the first and second connecting seal structures enclose the internal scribe line (see Figs. 15A-C, ¶¶75-78, 15 is common to/part of 13 and 14),
the first seal ring structure, the second seal ring structure, the first connecting seal structure, and the second connecting seal structure include stacked wiring layer structures including wiring patterns and via contacts (see representative cross section in Figs. 8-12, noting the only difference in the Fig. 15 embodiment is the seal ring 15 is common with 13/14 rather than laterally adjacent as shown in Figs. 6 and 8, so in Fig. 15, 15/13/14 are understood to be the same stack of wiring instead of two adjacent stacks, wiring patterns LS, via patterns PS),
the stacked wiring layer structure of the first seal ring structure extends from a first wiring layer at a first height over a main surface the substrate to an (N-M)-th wiring layer at a second height over the main surface the substrate (layers PS1/LS1 – PS5/LS5),
the stacked wiring layer structure of the second seal ring structure extends from the first wiring layer at the first height over the main surface the substrate to the (N-M)-th wiring layer at the second height over the main surface the substrate (layers PS1/LS1 – PS5/LS5),
the stacked wiring layer structure of the first connecting seal structure extends from the first wiring layer at the first height over the main surface the substrate to the (N-M)-th wiring layer at the second height over the main surface the substrate (layers PS1/LS1 – PS5/LS5),
the stacked wiring layer structure of the second connecting seal structure extends from the first wiring layer at the first height over the main surface the substrate to the (N-M)-th wiring layer at the second height over the main surface the substrate (layers PS1/LS1 – PS5/LS5),
the third seal ring structure includes wiring structure extending from an (N-M+1)-th wiring layer to an N-th wiring layer, where M <N (PS6/LS6), and
the third seal ring structure is over the stacked wiring layer structures of the first seal ring structure, the second seal ring structure, and the first and second connecting seal structures (third seal ring structure top layers of 15 PS6/LS6).
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While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-12 and 14. Figs. 8-12 and 14 showing the seal rings are formed of a multilayer wiring pattern (e.g. PS1-LS6), noting 15 is common to/part of 13 and 14, and the layers ascribed to the first and second seal rings can arbitrarily be the plurality of lower N-M layers (e.g. PS1-PS6 or LS5-PS1, etc.).
(Re Claim 4) further comprising a pad electrode composed of a wiring pattern in the N-th wiring layer (see 22/LS6 in Figs. 13A-14).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
(Re Claim 5) wherein the N-th wiring layer is an uppermost wiring layer of the semiconductor device (the LS6 layer).
(Re Claim 6) wherein M is 2 or 3 (the layers may be selected such that M is 2 or 3, e.g. one may choose LS3 or LS4 as a first layer).
(Re Claim 8) further comprising a pad electrode composed of a wiring pattern in the N-th wiring layer (see 22/LS6 in Figs. 13A-14).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
(Re Claim 10) further includes a connection pattern (17) connecting a circuit in the first circuit area and a circuit in the second circuit area and bridging over the internal scribe line.
(Re Claim 12) wherein no functional circuit is disposed in the internal scribe line (no functional circuits are disclosed or shown in any scribe lines, see entire disclosure).
(Re Claim 21) Nomura teaches a semiconductor device, comprising (see Figs. 15A-C and ¶¶75-78):
a first circuit (11) over a substrate (1) and surrounded by a first lower seal ring structure (13); a second circuit (12) over the substrate and surrounded by a second lower seal ring structure (14);
a first connecting seal structure (portion of 15, see figure above) including a first end connected to a first corner of the first lower seal ring structure and a second end connected to a first corner of the second lower seal ring structure;
a second connecting seal structure (portion of 15, see figure above) including a first end connected to a second corner of the first lower seal ring structure and a second end connected to a second corner of the second lower seal ring structure;
a scribe line (16) separating the first lower seal ring structure from the second lower seal ring structure; and
an upper seal ring structure (15) formed on the first over the first and second lower seal ring structures and the first and second connecting seal structures (Figs. 15A-15C, 15 is common to/part of 13/14 and may be ascribed to the upper layer(s), e.g. LS6, PS6, ¶¶75-78),
wherein the first and second lower seal ring structures include stacked seal ring wiring layer structures extending from a first wiring layer at a first height over the substrate to an (N-1)-th wiring layer at a second height over the substrate, the first and second connecting seal structures include stacked connecting seal wiring layer structures extending from the first wiring layer at the first height over the substrate to the (N-1)-th wiring layer at the second height over the substrate, and the upper seal ring structure includes a N-th wire pattern (see representative cross sections in Figs. 8-12 and 14, the only difference in the Fig. 15 embodiment is the seal ring 15 is common with/part of 13/14 rather than laterally adjacent as shown in Figs. 6 and 8, in Fig. 15, 15/13 and 15/14 are understood to be layers of the same stack of wiring instead of two adjacent stacks, wiring patterns LS, via patterns PS, 15 is one or more upper/uppermost layers).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-12 and 14. Figs. 15A-C showing the three ring structures and cross sections in Figs. 8-12 and 14 showing how the rings 13-15 are formed in a multilayer interconnect structure. The third ring 15 overlaps and is common with/part of the first and second rings 13/14 (¶¶75-78), and may be arbitrarily ascribed to an upper layer(s) of the ring structure(s) while the first and second lower ring structures may be ascribed to lower layer(s) of the ring structures.
(Re Claim 22) wherein the upper seal ring structure covers the first and second connecting seal structures, covers three sides of the first lower seal ring structure, and covers three sides of the second lower seal ring structure (Figs. 15A-C).
(Re Claim 23) further comprising circuit connection patterns (17) connecting the first circuit and the second circuit (Figs. 15A-C).
(Re Claim 24) wherein the circuit connection patterns bridge the scribe line (16).
(Re Claim 25) Nomura teaches a semiconductor device, comprising (see Figs. 15A-C and ¶¶75-78, also note details of the circuit areas including ILDs, wiring layers, and transistors in Figs. 6A-11 and 13A-14):
a first region (11) including first multiple wiring layers connected to a first transistor wherein the first transistor is over a substrate (see Figs. 8, 12, and 14 showing multiple wiring layers connected to a transistor, substrate 1);
a first seal structure (13) around the first region;
a second region (12) including second multiple wiring layers connected to a second transistor wherein the second transistor is over the substrate (see Figs. 8, 12, and 14 showing multiple wiring layers connected to a transistor);
a second seal structure (14) around the second region;
a scribe line (16) between the first and second seal structures;
a first connecting seal (portion of 15, see figure above) including a first end connected to a first corner of the first seal structure and a second end connected to a first corner of the second seal structure; and
a second connecting seal (portion of 15, see figure above) including a first end connected to a second corner of the first seal structure and a second end connected to a second corner of the second seal structure, the first and second connecting seals and the first and second seal structures enclose the scribe line in a plan view (Figs. 15A-15C).
an upper seal structure (upper layers of 15 in 13/15 and 14/15, 15 is common to/pat of 13 and 14) over the first and second seal structures and the first and second connecting seals,
wherein the first and second connecting seals and the first and second seal structures enclose the scribe line in a plan view (Figs. 15A-C),
the first and second seal structures include seal structure wiring stacks comprising a first seal structure wiring layer and an upper seal structure wiring layer, the first seal structure wiring layer is at a first height over the substrate and the upper seal structure wiring layer is at a second height over the substrate, the first and second connecting seals include stacked connecting seal wiring stacks comprising a first connecting seal wiring layer and an upper connecting seal wiring layer, the first connecting seal wiring layer is at the first height over the substrate, and the upper connecting seal wiring layer is at the second height over the substrate, and the upper seal structure includes a wiring layer at a third height over the substrate, and the third height is greater than the second height (see representative cross sections in Figs. 8-12 and 14, the only difference in the Fig. 15 embodiment is the seal ring 15 is common with/part of 13/14 rather than laterally adjacent as shown in Figs. 6 and 8, in Fig. 15, 15/13 and 15/14 are understood to be layers of the same stack of wiring instead of two adjacent stacks, wiring patterns LS, via patterns PS, 15 is one or more upper/uppermost layers).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-12 and 14. Figs. 15A-C showing the three ring structures and cross sections in Figs. 8-12 and 14 showing how the rings 13-15 are formed in a multilayer interconnect structure. The third ring 15 overlaps and is common with/part of the first and second rings 13/14 (¶¶75-78), and may be arbitrarily ascribed to an upper layer(s) of the ring structure(s) while the first and second lower ring structures may be ascribed to lower layer(s) of the ring structures.
(Re Claim 26) further comprising circuit connection patterns (17) connecting the first region and the second region, wherein the circuit connection patterns bridge the scribe line.
(Re Claim 27) further comprising a first pad layer on the first multiple wiring layers and a second pad layer on the second multiple wiring layers (see 22/LS6 in Figs. 13A-14).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
(Re Claim 28) further comprising one or more interlayer dielectric layers (D1-D8) formed on the first and second transistors.
(Re Claim 29) wherein the N-th wire pattern is an uppermost wiring layer of the semiconductor device (uppermost layer of 13/15 and 14/15).
(Re Claim 30) further comprising a pad electrode composed of a wiring pattern in the N-th wire pattern (see 22/LS6 in Figs. 13A-14).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
(Re Claim 31) wherein an uppermost wiring layer of the semiconductor device includes wiring layer at the third height (uppermost layer 15).
(Re Claim 32. The semiconductor device of claim 31, wherein the uppermost wiring layer further comprising a pad electrode (see 22/LS6 in Figs. 13A-14).
While Nomura does not repeat the cross sections and descriptions for similar features for each embodiment (note ¶¶70, 75, further noting the features of the embodiments may be combined, ¶¶87-88), a PHOSITA would recognize the Fig. 15 embodiment obviously comprises the same ILD and wiring layers as in the embodiments shown in Figs. 8-14, and may similarly incorporate the pad 22 at LS6 for making an electrical connection to transistors in the circuits.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. (US 2008/0017965) as applied above, and further in view of Ramachandran et al. (US 2023/0040308), Aleksov et al. (US 2012/0007211), and Burton et al. (US 2020/0066651), all of record.
(Re Claim 11) wherein the connection pattern is composed of a wiring pattern in an uppermost wiring layer of the semiconductor device.
Nomura does not disclose an example wherein the connection pattern is composed of a wiring pattern in an uppermost wiring layer of the semiconductor device. A PHOSITA would recognize the connection patterns are simply additional wiring patterns formed in the multilayer wiring patterns/ILD layers and can be formed at any level in the structure, including the uppermost layer, and will provide the desired function of connecting the circuits in different areas regardless of the elevation within the interconnect structure. Related art from Ramachandran teaches the connection patterns 140 can be formed in the uppermost layer of the wiring patterns, see Figs. 9-10 and 13-14. Related art from Burton also similarly teaches the connection patterns 324 can be formed in the uppermost layer of the wiring patterns, see Figs. 3A-3B. Related art from Aleksov also teaches the connection patterns, e.g. 342/350 can be formed in the uppermost layer of the wiring patterns, see Figs. 5-10. In view of the prior art, a PHOSITA would recognize that the connection patterns can be formed in the uppermost wiring patterns. This would allow for the lower rings to be formed continuously from the substrate all the way up to the highest metal layers thereby providing better protection.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant asserts the applied prior art does not teach the amended claims. The Examiner respectfully disagrees, see updated rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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