DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 5-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KONDO (US 20220093727) in view of NAGATA (US 20200312962).
Regarding claim 1, KONDO discloses a semiconductor device comprising:
a first conductive substrate (1st conductivity type layer 101, see fig 1, para 17);
a first conductive epitaxial layer (the epitaxial layer 103, 105 and 129, see fig 1, para 17) disposed on the first conductive substrate;
a first conductive drift layer (the drift layer 103A and 103B, see fig 1, para 17) formed within the first conductive epitaxial layer;
a plurality of trenches (the trenches 121, see fig 1, para 16) formed in the first conductive epitaxial layer;
a shield electrode (field plate 125, see fig 1, para 16) formed in a lower portion of each of the plurality of trenches (125 are formed in lower parts of 121, see fig 1);
a shield oxide layer (the part of the insulator 123 around 121 in the bottom of the trench, see fig 1, 123, para 16) formed within each of the plurality of trenches and formed to surround the shield electrode (see fig 1);
a gate electrode (gate electrode 127 formed in 121 over 125, see fig 1, para 16) formed within each of the plurality of trenches and formed on the shield electrode;
a second conductive body region (second conductivity type 105, see fig 1, para 18) formed on an upper portion comprising a surface of the first conductive epitaxial layer between the plurality of trenches (105 is formed on an upper surface of 103 between 121, see fig 1),
a source region (fig 1, 129, para 16) formed on the second conductive body region;
an insulation layer (the insulator 113 above 127, see fig 1, 113, para 21) formed on the gate electrode;
a source contact layer (metal contact 115, see fig 1, para 16) formed in contact with the source region; and
a source electrode (fig 1, 117, para 16) formed on the source contact layer,
wherein a central portion of the second conductive body region is in contact with the source contact layer (105 is in contact with 115, see fig 1), and a lower surface of the second conductive body region is disposed lower at the central portion than a side portion of the second conductive body region in a direction toward the first conductive drift layer (the bottom surface of 105 is lower in the middle between trenches 121 than it is near the trenches 121, see fig 1), and
wherein the lower surface of the second conductive body region is curved continuously from the side portion to the central portion (the bottom surface of 105 is continuously curved, see fig 1), the central portion protruding toward the first conductive drift layer to define a lowest point of the lower surface (105 is curved convex towards 103, see fig 1).
KONDO fails to explicitly disclose a device comprising a drain electrode;
a first conductive substrate disposed on the drain electrode.
NAGATA teaches a device comprising a drain electrode (fig 1-2, 59, para 135);
wherein the first conductive substrate (fig 1-2, 2, para 22) is disposed on the drain electrode.
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the drain electrode wherein the substrate is on the drain electrode of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the drain electrode wherein the substrate is on the drain electrode of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 2, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO fails to explicitly disclose a device, wherein a depth of each trench is between 0.5 microns and 6 microns, and
wherein the depth of each trench is 0.3 to 0.9 times a depth of the epitaxial layer.
NAGATA teaches a device, wherein a depth of each trench is between 0.5 microns and 6 microns (trench 22 can be 5 microns deep, see para 78), and
wherein the depth of each trench is 0.3 to 0.9 times a depth of the epitaxial layer (epi layer 6 can be 10-15 microns thick, which would put a 5 micron deep trench 22 in this range, see para 32).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the element sizes of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the element sizes of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 3, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO further discloses a device, wherein a top surface of the gate electrode is lower than a top surface of the first conductive epitaxial layer (the top surface of 127 is lower than the top surface of 129, see fig 1).
Regarding claim 5, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO fails to explicitly disclose a device, wherein a ratio of a maximum width of the second conductive body region to a depth of each trench is 1:2 to 1:20.
NAGATA teaches a device, wherein a ratio of a maximum width of the second conductive body region to a depth of each trench is 1:2 to 1:20 (the trench depth can be 5 microns, see para 78, and the width of body 20 is the trench pitch which can be 1.5 microns, see para 68, minus the trench width which can be 1 micron, see para 77, giving a width of 20 as 0.5 microns which would give a ration of 1:10 which is in the range required).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the element sizes of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the element sizes of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Additionally, parameters such as the sizes of elements in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the depths of the gate electrode and size of the body region in the device of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 6, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO fails to explicitly disclose a device, wherein the first conductive drift layer comprises:
a first conductive high concentration drift layer formed adjacent to the substrate;
a first conductive medium concentration drift layer formed between the first conductive high concentration drift layer and the shield oxide layer; and
a first conductive low concentration drift layer formed between the first conductive medium concentration drift layer and the second conductive body region.
NAGATA teaches a device, wherein the first conductive drift layer comprises:
a first conductive high concentration drift layer (highly doped region 11, see fig 2-3, para 34) formed adjacent to the substrate (11 is next to 2, see fi g2);
a first conductive medium concentration drift layer (intermediate concentration layer 12, see fig 2-3, para 36) formed between the first conductive high concentration drift layer and the shield oxide layer (12 is between 11 and 31, see fig 2); and
a first conductive low concentration drift layer (low concentration layer 13, see fig 2-3, para 36) formed between the first conductive medium concentration drift layer and the second conductive body region (13 is between 12 and 20, see fig 2).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the drift layer doping of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the drift layer doping of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 7, KONDO and NAGATA disclose the semiconductor device of claim 6.
KONDO fails to explicitly disclose a device. wherein depths of the first conductive high concentration drift layer, the first conductive medium concentration drift layer, and the first conductive low concentration drift layer are different from each other.
NAGATA teaches a device. wherein depths of the first conductive high concentration drift layer, the first conductive medium concentration drift layer, and the first conductive low concentration drift layer are different from each other (11, 12 and 13 are located at different depths below the top surface of 6, see fig 2).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the drift layer doping of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the drift layer doping of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 8, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO further discloses a device, wherein the source contact layer simultaneously contacts the second conductive body region and the source region (115 is in contact with both 129 and 105, see fig 1).
Regarding claim 9, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO further discloses a device, further comprising: a gate oxide layer formed on a side surface and a lower surface of the gate electrode (the portion of the insulator 123 surrounding 127, see fig 1, para 16).
Regarding claim 10, KONDO and NAGATA disclose the semiconductor device of claim 9.
KONDO further discloses a device, wherein a side surface of the second conductive body region is in contact with the gate oxide layer (105 is in contact with the insulator 123 to the side of the gate 127, see fig 1),
wherein an upper surface of the second conductive body region is in contact with the source contact layer (the upper surface of 105 is in contact with 129, see fig 1), and
wherein the curved shape of the central portion of the second conductive body region minimizes a channel length at the side portion (because the sides of 105 curve up, the channel length is shorter than it would otherwise be, see fig 1).
Regarding claim 11, KONDO and NAGATA disclose the semiconductor device of claim 6.
KONDO fails to explicitly disclose a device, wherein a doping concentration of the first conductive drift layer gradually decreases from a contact surface with the first conductive substrate to the second conductive body region.
NAGATA teaches a device, wherein a doping concentration of the first conductive drift layer gradually decreases from a contact surface with the first conductive substrate to the second conductive body region (the doping concentration of 11 decreases from 2 towards 12, see fig 3, para 33).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the drift layer doping of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the drift layer doping of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 12, KONDO and NAGATA disclose the semiconductor device of claim 6.
KONDO fails to explicitly disclose a device, wherein a top surface of the first conductive medium concentration drift layer is out-diffused into a bottom surface of each trench or partially overlaps the bottom surface of each trench.
NAGATA teaches a device, wherein a top surface of the first conductive medium concentration drift layer is out-diffused into a bottom surface of each trench or partially overlaps the bottom surface of each trench (12 overlaps along a vertical line with the bottom surfaces of 22, see fig 2).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the drift layer doping of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the drift layer doping of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Regarding claim 13, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO fails to explicitly disclose a device, wherein a ratio of a depth of the second conductive body region to a depth of each trench is 1:2 to 1:30.
NAGATA teaches a device, wherein a ratio of a depth of the second conductive body region to a depth of each trench is 1:2 to 1:30 (the body region 20 can have a depth of 0.5 microns, see para 66, and the depth of the trench 22 can be 5 microns, see para 78, which would give a ratio of 1:10 which in in the range).
KONDO and NAGATA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO with the element sizes of NAGATA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KONDO with the element sizes of NAGATA in order to suppress a reduction in breakdown voltage and reduce a resistance of an epitaxial layer (see NAGATA para 17).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over KONDO (US 20220093727) in view of NAGATA (US 20200312962) and further in view of BALIGA (US 6545316).
Regarding claim 4, KONDO and NAGATA disclose the semiconductor device of claim 1.
KONDO and NAGATA fails to explicitly disclose a device, wherein a length of the second conductive body region is equal to or less than 1/2 of a length from an upper surface of the first conductive epitaxial layer to a lower surface of the gate electrode.
BALIGA teaches a device, wherein a length of the second conductive body region is equal to or less than 1/2 of a length from an upper surface of the first conductive epitaxial layer to a lower surface of the gate electrode (the gate electrode 127 can be 0.6 microns deep, and the body region 116 can have a dimension of 0.2 microns which is less than 1/2, see fig 3, para 9).
KONDO, NAGATA and BALIGA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KONDO and NAGATA with element sizes of BALIGA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device the device of KONDO and NAGATA with element sizes of BALIGA in order to achieve excellent current characteristics (see BALIGA para 9).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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