DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 5/21/2026 is acknowledged.
Applicant amended claims 1, 6, 11, and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2022/0069100) (hereafter Hwang), in view of Zhang et al. (US 2020/0258785) (hereafter Zhang), in further view of Lee et al. (US 2022/0359682) (hereafter Lee), in another further view of Kim et al. (US 2017/0148797) (hereafter Kim).
Regarding claim 1, Hwang discloses a method for fabricating a semiconductor device, comprising:
forming a first gate structure (first GS from the left corner of Fig. 10, paragraph 0018), a second gate structure (second GS from the left corner of Fig. 10) and a third gate structure (third GS from the left corner of Fig. 10) on a substrate 101 (Fig. 10, paragraph 0019), wherein the substrate 101 (Fig. 10) comprises a first region (left portion of 101 in Fig. 10), a second region (middle portion of 101 in Fig. 10), and a third region (right portion of 101 in Fig. 10);
forming three high-k dielectric layers (first 142, second 142, and third 142 from the left corner of Fig. 10, paragraph 0024) over the substrate 101 (Fig. 10) in the first region (left portion of 101 in Fig. 10), the second region (middle portion of 101 in Fig. 10) and the third region (right portion of 101 in Fig. 10) respectively;
forming a first epitaxial layer (first 110’ from the left corner of Fig. 10, paragraph 0100) on the first region (left portion of 101 in Fig. 10) adjacent to the first gate structure (first GS from the left corner of Fig. 10), wherein a top surface of the first epitaxial layer (first 110’ from the left corner of Fig. 10) comprises a first curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and a second curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”),
forming a second epitaxial layer (second 110’ from the left corner of Fig. 10, paragraph 0100) on the second region (middle portion of 101 in Fig. 10); and
forming a third epitaxial layer (third 110’ from the left corner of Fig. 10, paragraph 0100) on the third region (right portion of 101 in Fig. 10).
Hwang does not disclose forming a first gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the first region; and
forming a second gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the second region,
forming a third gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the third region under the third gate structure, and wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer, and the thickness of the second gate dielectric layer is greater than a thickness of the third gate dielectric layer.
Zhang discloses forming a first gate dielectric layer 90 (Fig. 10, paragraph 0061) disposed directly under and contacting the high-k dielectric layer (92, 82, and 72 in Fig. 10, paragraph 0061) in the first region (region of 10 with 40’ in Fig. 10); and
forming a second gate dielectric layer 80 (Fig. 10, paragraph 0060) disposed directly under and contacting the high-k dielectric layer (92, 82, and 72 in Fig. 10) in the second region (region of 10 with 30’ in Fig. 10),
forming a third gate dielectric layer 70 (Fig. 10, paragraph 0059) disposed directly under and contacting the high-k dielectric layer (92, 82, and 72 in Fig. 10) in the third region (region of 10 with 20’ in Fig. 10) under the third gate structure 110 (Fig. 10, paragraph 0068), and wherein a thickness (“t.sub.3” in paragraph 0061) of the first gate dielectric layer 90 (Fig. 10) is greater (see paragraph 0061, wherein “t.sub.3>t.sub.2>t.sub.1”) than a thickness (“t.sub.2” in paragraph 0061) of the second gate dielectric layer 80 (Fig. 10), and the thickness (“t.sub.2” in paragraph 0061) of the second gate dielectric layer 80 (Fig. 10) is greater (see paragraph 0061, wherein “t.sub.3>t.sub.2>t.sub.1”) than a thickness (“t.sub.1” in paragraph 0061) of the third gate dielectric layer 70 (Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang to include forming a first gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the first region; and forming a second gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the second region, forming a third gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the third region under the third gate structure, and wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer, and the thickness of the second gate dielectric layer is greater than a thickness of the third gate dielectric layer, as taught by Zhang, since the oxide thickness (Zhang, paragraph 0063) of the first, second, third, and fourth FET devices 20, 30, 40, 50 (Zhang, Fig. 10, paragraph 0063) can be adjusted to be successively or consecutively larger or thicker.
Hwang and Zhang do not disclose a top surface profile of the first epitaxial layer, a top surface profile of the second epitaxial layer and atop surface profile of the third epitaxial layer are different from one another.
Lee disclose a top surface profile of the first epitaxial layer (146 of 100L in Fig. 11B, paragraph 0028), a top surface profile of the second epitaxial layer (146 of right portion of 100S in Fig. 11B, paragraph 0028) and atop surface profile of the third epitaxial layer (146 of left portion of 100S in Fig. 11B, paragraph 0028) are different from one another.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang in view of Zhang to include a top surface profile of the first epitaxial layer, a top surface profile of the second epitaxial layer and atop surface profile of the third epitaxial layer are different from one another, as taught by Lee, since the diamond-like shape (Lee, paragraph 0010) of the epitaxial S/D features in the long channel regions or I/O regions provides an increased raise height, which in turn increases the surface area of the epitaxial S/D features for a subsequent S/D contact to conduct more current such that the contact resistance (Lee, paragraph 0010) of epitaxial S/D features in the long channel regions or I/O regions is reduced and the device performance of the transistors is improved.
Hwang, Zhang, and Lee do not disclose a topmost height of the first epitaxial layer, a topmost height of the second epitaxial layer, and a topmost height of the third epitaxial layer are different from each other.
Kim discloses a topmost height of the first epitaxial layer (506a-506c in Fig. 95, paragraph 0219), a topmost height of the second epitaxial layer (504a-504c in Fig. 95, paragraph 0209), and a topmost height of the third epitaxial layer (502a-502c in Fig. 95, paragraph 0209) are different (see Fig. 90 and paragraph 0229, wherein “the first depth D1 may be greater than the second and third depths D2 and D3. The second and third depths D2 and D3 may be substantially equal to or different from each other”) from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang in view of Zhang and Lee to include forming a first gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the first region; forming a second gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the second region; and a topmost height of the first epitaxial layer, a topmost height of the second epitaxial layer, and a topmost height of the third epitaxial layer are different from each other, as taught by Kim, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 2, Hwang further discloses the method of claim 1, wherein the first curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the second curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprise curves concave downward.
Regarding claim 3, Hwang further discloses the method of claim 2, wherein the top surface of the first epitaxial layer (first 110’ from the left corner of Fig. 10) comprises a third curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a dip of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) connecting the first curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the second curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”).
Regarding claim 4, Hwang further discloses the method of claim 3, wherein the third curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a dip of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprises a curve concave upward.
Regarding claim 5, Hwang further discloses the method of claim 1, further comprising: forming the first gate structure (first GS from the left corner of Fig. 10) on the first region (region of 101 covered by first GS from the left corner of Fig. 10), the second gate structure (second GS from the left corner of Fig. 10) on the second region (region of 101 covered by second GS from the left corner of Fig. 10), and the third gate structure (third GS from the left corner of Fig. 10) on the third region (region of 101 covered by third GS from the left corner of Fig. 10);
forming the second epitaxial layer (second 110’ from the left corner of Fig. 10, paragraph 0100) adjacent to the second gate structure (second GS from the left corner of Fig. 10), wherein a top surface of the second epitaxial layer (second 110’ from the left corner of Fig. 10) comprises a fourth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the fifth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”); and
forming the third epitaxial layer (third 110’ from the left corner of Fig. 10, paragraph 0100) adjacent to the third gate structure (third GS from the left corner of Fig. 10).
Regarding claim 6, Hwang further discloses the method of claim 5, wherein the fourth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and a fifth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprise curves concave downward.
Regarding claim 7, Hwang further discloses the method of claim 6, wherein the top surface of the second epitaxial layer (second 110’ from the left corner of Fig. 10) comprises a sixth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first low point between the first bump of top surface of 110’ and the second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) connecting the fourth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the fifth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”).
Regarding claim 8, Hwang further discloses the method of claim 7, wherein the sixth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first low point between the first bump of top surface of 110’ and the second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprises a curve concave upward.
Regarding claim 9, Hwang further discloses the method of claim 5, wherein the third epitaxial layer (third 110’ from the left corner of Fig. 10; and see paragraph 0029, wherein “hexagonal shape”) comprises a hexagon.
Regarding claim 11, Hwang discloses a semiconductor device, comprising:
a first gate structure (first GS from the left corner of Fig. 10, paragraph0018), a second gate structure (second GS from the left corner of Fig. 10) and a third gate structure (third GS from the left corner of Fig. 10) on a substrate 101 (Fig. 10, paragraph 0019), wherein the substrate 101 (Fig. 10) comprises a first region (left portion of 101 in Fig. 10), a second region (middle portion of 101 in Fig. 10), and a third region (right portion of 101 in Fig. 10);
three high-k dielectric layers (first 142, second 142, and third 142 from the left corner of Fig. 10, paragraph 0024) over the substrate 101 (Fig. 10) in the first region (left portion of 101 in Fig. 10), the second region (middle portion of 101 in Fig. 10) and the third region (right portion of 101 in Fig. 10) respectively;
a first epitaxial layer (first 110’ from the left corner of Fig. 10, paragraph 0100) adjacent to the first gate structure (first GS from the left corner of Fig. 10), wherein a top surface of the first epitaxial layer (first 110’ from the left corner of Fig. 10) comprises a first curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and a second curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”).
a second epitaxial layer (second 110’ from the left corner of Fig. 10, paragraph 0100) on the second region (middle portion of 101 in Fig. 10); and
a third epitaxial layer (third 110’ from the left corner of Fig. 10, paragraph 0100) on the third region (right portion of 101 in Fig. 10).
Hwang does not disclose a first gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the first region; and
a second gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the second region,
a third gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the third region under the third gate structure, and wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer, and the thickness of the second gate dielectric layer is greater than a thickness of the third gate dielectric layer.
Zhang discloses a first gate dielectric layer 90 (Fig. 10, paragraph 0061) disposed directly under and contacting the high-k dielectric layer (92, 82, and 72 in Fig. 10, paragraph 0061) in the first region (region of 10 with 40’ in Fig. 10); and
a second gate dielectric layer 80 (Fig. 10, paragraph 0060) disposed directly under and contacting the high-k dielectric layer (92, 82, and 72 in Fig. 10) in the second region (region of 10 with 30’ in Fig. 10),
a third gate dielectric layer 70 (Fig. 10, paragraph 0059) disposed directly under and contacting the high-k dielectric layer (92, 82, and 72 in Fig. 10) in the third region (region of 10 with 20’ in Fig. 10) under the third gate structure 110 (Fig. 10, paragraph 0068), and wherein a thickness (“t.sub.3” in paragraph 0061) of the first gate dielectric layer 90 (Fig. 10) is greater (see paragraph 0061, wherein “t.sub.3>t.sub.2>t.sub.1”) than a thickness (“t.sub.2” in paragraph 0061) of the second gate dielectric layer 80 (Fig. 10), and the thickness (“t.sub.2” in paragraph 0061) of the second gate dielectric layer 80 (Fig. 10) is greater (see paragraph 0061, wherein “t.sub.3>t.sub.2>t.sub.1”) than a thickness (“t.sub.1” in paragraph 0061) of the third gate dielectric layer 70 (Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang to form a first gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the first region; and a second gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the second region, a third gate dielectric layer disposed directly under and contacting the high-k dielectric layer in the third region under the third gate structure, and wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer, and the thickness of the second gate dielectric layer is greater than a thickness of the third gate dielectric layer, as taught by Zhang, since the oxide thickness (Zhang, paragraph 0063) of the first, second, third, and fourth FET devices 20, 30, 40, 50 (Zhang, Fig. 10, paragraph 0063) can be adjusted to be successively or consecutively larger or thicker.
Hwang and Zhang do not disclose a top surface profile of the first epitaxial layer, a top surface profile of the second epitaxial layer and atop surface profile of the third epitaxial layer are different from one another.
Lee disclose a top surface profile of the first epitaxial layer (146 of 100L in Fig. 11B, paragraph 0028), a top surface profile of the second epitaxial layer (146 of right portion of 100S in Fig. 11B, paragraph 0028) and atop surface profile of the third epitaxial layer (146 of left portion of 100S in Fig. 11B, paragraph 0028) are different from one another.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang in view of Zhang to include a top surface profile of the first epitaxial layer, a top surface profile of the second epitaxial layer and atop surface profile of the third epitaxial layer are different from one another, as taught by Lee, since the diamond-like shape (Lee, paragraph 0010) of the epitaxial S/D features in the long channel regions or I/O regions provides an increased raise height, which in turn increases the surface area of the epitaxial S/D features for a subsequent S/D contact to conduct more current such that the contact resistance (Lee, paragraph 0010) of epitaxial S/D features in the long channel regions or I/O regions is reduced and the device performance of the transistors is improved.
Hwang, Zhang, and Lee do not disclose a topmost height of the first epitaxial layer, a topmost height of the second epitaxial layer, and a topmost height of the third epitaxial layer are different from each other.
Kim discloses a topmost height of the first epitaxial layer (506a-506c in Fig. 95, paragraph 0219), a topmost height of the second epitaxial layer (504a-504c in Fig. 95, paragraph 0209), and a topmost height of the third epitaxial layer (502a-502c in Fig. 95, paragraph 0209) are different (see Fig. 90 and paragraph 0229, wherein “the first depth D1 may be greater than the second and third depths D2 and D3. The second and third depths D2 and D3 may be substantially equal to or different from each other”) from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang in view of Zhang and Lee to include a topmost height of the first epitaxial layer, a topmost height of the second epitaxial layer, and a topmost height of the third epitaxial layer are different from each other, as taught by Kim, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 12, Hwang further discloses the semiconductor device of claim 11, wherein the first curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the second curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprise curves concave downward.
Regarding claim 13, Hwang further discloses the semiconductor device of claim 12, wherein the top surface of the first epitaxial layer (first 110’ from the left corner of Fig. 10) comprises a third curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a dip of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) connecting the first curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the second curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”).
Regarding claim 14, Hwang further discloses the semiconductor device of claim 13, wherein the third curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that first 110’ from the left corner of Fig. 10 having a dip of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprises a curve concave upward.
Regarding claim 15, Hwang further discloses the semiconductor device of claim 11, further comprising: forming the first gate structure (first GS from the left corner of Fig. 10) on the first region (region of 101 covered by first GS from the left corner of Fig. 10), the second gate structure (second GS from the left corner of Fig. 10) on the second region (region of 101 covered by second GS from the left corner of Fig. 10), and the third gate structure (third GS from the left corner of Fig. 10) on the third region (region of 101 covered by third GS from the left corner of Fig. 10);
forming a second epitaxial layer (second 110’ from the left corner of Fig. 10, paragraph 0100) adjacent to the second gate structure (second GS from the left corner of Fig. 10), wherein a top surface of the second epitaxial layer (second 110’ from the left corner of Fig. 10) comprises a fourth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and a fifth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”); and forming a third epitaxial layer (third 110’ from the left corner of Fig. 10, paragraph 0100) adjacent to the third gate structure (third GS from the left corner of Fig. 10).
Regarding claim 16, Hwang further discloses the semiconductor device of claim 15, wherein the fourth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the fifth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprise curves concave downward.
Regarding claim 17, Hwang further discloses the semiconductor device of claim 16, wherein the top surface of the second epitaxial layer (second 110’ from the left corner of Fig. 10) comprises a sixth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first low point between the first bump of top surface of 110’ and the second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) connecting the fourth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) and the fifth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”).
Regarding claim 18, Hwang further discloses the semiconductor device of claim 17, wherein the sixth curve (see Fig. 10, wherein each 110’ on left side of Fig. 10 having 110’ on right side of Fig. 10 such that second 110’ from the left corner of Fig. 10 having a first low point between the first bump of top surface of 110’ and the second bump of top surface of 110’ from the right corner of Fig. 10; and see paragraph 0102, wherein “curved crystal surface of the source/drain region 110′”) comprises a curve concave upward.
Regarding claim 19, Hwang further discloses the semiconductor device of claim 15, wherein the third epitaxial layer (third 110’ from the left corner of Fig. 10; and see paragraph 0029, wherein “hexagonal shape”) comprises a hexagon.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Zhang, Lee, and Kim as applied to claims 5 and 15 above, and further in view of Terada et al. (US 2014/0284681) (hereafter Terada).
Regarding claim 10, Hwang in view of Zhang, Lee, and Kim discloses the method of claim 5, however Hwang, Lee, and Kim do not disclose the first region comprises a high-voltage (HV) region with a rated voltage of over 5 V and not more than 40 V, the second region comprises a medium-voltage (MV) region with a rated voltage of not less than 2 V and not more than 5 V, and the third region comprises a low-voltage (LV) region with a rated voltage of less than 2 V.
Terada discloses the first region 40 (Fig. 3A, paragraph 0056) comprises a high-voltage (HV) region (“HV-CMOS (High Voltage-Complementary Metal Oxide Semiconductor) region” in paragraph 0056; and see paragraph 0058, wherein “over 5V and not more than 40V”) with a rated voltage of over 5 V and not more than 40 V, the second region 70 (Fig. 3A, paragraph 0056) comprises a medium-voltage (MV) region (“MV-CMOS (Middle Voltage-Complementary Metal Oxide Semiconductor) region” in paragraph 0056; and see paragraph 0067, wherein “not less than 2V and not more than 5V”) with a rated voltage of not less than 2 V and not more than 5 V, and the third region 90 (Fig. 3A, paragraph 0056) comprises a low-voltage (LV) region (“LV-CMOS (Low Voltage-Complementary Metal Oxide Semiconductor) region” in paragraph 0056; and see paragraph 0078, wherein “less than 2V”) with a rated voltage of less than 2 V.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang in view of Zhang, Lee, and Kim to include a high-voltage (HV) region with a rated voltage of over 5 V and not more than 40 V, the second region comprises a medium-voltage (MV) region with a rated voltage of not less than 2 V and not more than 5 V, and the third region comprises a low-voltage (LV) region with a rated voltage of less than 2 V, as taught by Terada, since the active region (Terada, paragraph 0020) may be formed in plural numbers so as to be adjacent across the element separation portion, and floating gates on the active regions adjacent to each other may overlap at their end portions with the element separation portion in common such that the memory cell (Terada, paragraph 0021) can also be miniaturized.
Regarding claim 20, Hwang in view of Zhang, Lee, and Kim discloses the method of claim 15, however Hwang, Lee, and Kim do not disclose the first region comprises a high-voltage (HV) region with a rated voltage of over 5 V and not more than 40 V, the second region comprises a medium-voltage (MV) region with a rated voltage of not less than 2 V and not more than 5 V, and the third region comprises a low-voltage (LV) region with a rated voltage of less than 2 V.
Terada discloses the first region 40 (Fig. 3A, paragraph 0056) comprises a high-voltage (HV) region (“HV-CMOS (High Voltage-Complementary Metal Oxide Semiconductor) region” in paragraph 0056; and see paragraph 0058, wherein “over 5V and not more than 40V”) with a rated voltage of over 5 V and not more than 40 V, the second region 70 (Fig. 3A, paragraph 0056) comprises a medium-voltage (MV) region (“MV-CMOS (Middle Voltage-Complementary Metal Oxide Semiconductor) region” in paragraph 0056; and see paragraph 0067, wherein “not less than 2V and not more than 5V”) with a rated voltage of not less than 2 V and not more than 5 V, and the third region 90 (Fig. 3A, paragraph 0056) comprises a low-voltage (LV) region (“LV-CMOS (Low Voltage-Complementary Metal Oxide Semiconductor) region” in paragraph 0056; and see paragraph 0078, wherein “less than 2V”) with a rated voltage of less than 2 V.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hwang in view of Zhang, Lee, and Kim to include a high-voltage (HV) region with a rated voltage of over 5 V and not more than 40 V, the second region comprises a medium-voltage (MV) region with a rated voltage of not less than 2 V and not more than 5 V, and the third region comprises a low-voltage (LV) region with a rated voltage of less than 2 V, as taught by Terada, since the active region (Terada, paragraph 0020) may be formed in plural numbers so as to be adjacent across the element separation portion, and floating gates on the active regions adjacent to each other may overlap at their end portions with the element separation portion in common such that the memory cell (Terada, paragraph 0021) can also be miniaturized.
Response to Arguments
Applicant's arguments filed 5/21/2026 have been fully considered.
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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