Prosecution Insights
Last updated: April 19, 2026
Application No. 18/111,433

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§112
Filed
Feb 17, 2023
Examiner
GUMEDZOE, PENIEL M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
87%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
1080 granted / 1302 resolved
+14.9% vs TC avg
Minimal +4% lift
Without
With
+3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
1325
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1302 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 02/17/23 & 10/18/23 &01/26/24 & 03/12/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner. Claim Objections Claim 11 and 13-16 are objected to because of the following informalities: Line 2 of claim 11 should recites “…first dielectric…”. Appropriate correction is required. Claim 13 should recites on line 1 “… of claim 12…” instead of “… claim 13..” as claim 13 cannot depend on itself. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 13-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 13 recites “and wherein the first substrate electrically connects the first electronic component through the support element.”. The question with this limitation is: the first substrate electrically connects the first electronic component to what? It is unclear. Claim 14 recites “and a third electronic component under the second substrate and electrically connects the first electronic component through the second substrate.”. It appears that the subject of the expression “electrically connects” is the third electronic component, and as such, the question with this limitation is: electrically connects the first electronic component to what? Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 11-13 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karzenos (US 2006/0172459). a. Re claim 1, Karzenos discloses an electronic device, comprising: a first carrier C1 (see annotated fig. 9A below; see previous figures such as fig. 5A and related text for example for more details on unlabeled structural elements on fig. 9A; see fig. 9A and related text as well as remaining of disclosure for more details); a second carrier C2 disposed over the first carrier; and a reinforcement R connected to the second carrier and configured (i.e. capable) to prevent the second carrier from being recessed toward the first carrier (encapsulant R is a rigid structure capable of preventing the second carrier from being recessed toward the first carrier as can be seen in fig. 9A). a'. In the alternative to the above, Karzenos discloses an electronic device, comprising: a first carrier 12 (see fig. 4 and at least [0025]-[0029]); a second carrier 42 disposed over (i.e. either connected to, or in alternative as overlying carrier 12 in fig. 4 rotated 180 degrees around an axis orthogonal to the plan of fig. 4) the first carrier; and a reinforcement 47 connected to the second carrier and configured (i.e. capable) to prevent the second carrier from being recessed toward the first carrier ([0025] discloses that the encapsulant, thus encapsulant 47, is provided to ensure rigidity of the lower package, and as such, encapsulant 47 is capable of preventing the second carrier from being recessed toward the first carrier). PNG media_image1.png 755 1422 media_image1.png Greyscale b. Re claim 2, the electronic device of claim 1, further comprises a first electronic component (492 or 494; [0180]) connected to the first carrier, a second electronic component 592 disposed over the first electronic component and connected to the second carrier and a third electronic component 594 encapsulated by the reinforcement. c. Re claim 3, a hardness of the first carrier is greater than a hardness of the second carrier (this is implicit for fig. 4 since 12 is a rigid substrate while 42 is a flexible substrate; [0025]-[0026]). d. Re claim 4, a thickness of the first carrier is greater than a thickness of the second carrier (carrier 12 is thicker than carrier 42 on fig. 4). e. Re claim 11, the second carrier comprises a first dielectric layer DL1 (see annotated fig. 9A above) and a second dielectric layer DL2, and wherein the first dielectric layer is closer to the first carrier than the second dielectric layer and a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer (explicit on annotated fig. 9A). f. Re claim 12, Karzenos discloses an electronic device, comprising: a first electronic component EC1 (see annotated fig. 11C below; see previous figures such as fig. 5A and related text for example for more details on unlabeled structural elements on fig. 11C; see fig. 11C and related text as well as remaining of disclosure for more details); a support element SE adjacent to the first electronic component; and a unit U supported by the support element, wherein the unit comprises: a second electronic component EC2 disposed over the first electronic component; and a reinforcement (R or R’ or R&R’) configured (i.e. capable) to space (at least in part) the second electronic component apart from the first electronic component. PNG media_image2.png 761 1369 media_image2.png Greyscale g. Re claim 13 an din view of the 112 1st rejection above, the unit comprises a first substrate SUB between (at least in part) the reinforcement and the second electronic component, and wherein the first substrate electrically connects the first electronic component to the second electronic component through the support element (explicit on annotated fig. 11C). e. Re claim 17, Karzenos discloses an electronic device, comprising: a coreless substrate 512 (see fig. 6A and related text noting that wiring substrate has one dielectric layer sandwiched between top and bottom metal layers 521 and 523, and as such, is basically a coreless substrate); at least one electronic component 514 mounted on the coreless substrate; at least one support element 417 configured (i.e. capable) to support the coreless substrate; and a reinforcement 517 connected to the coreless substrate and configured (i.e. capable) to prevent the coreless substrate from collapsing due to a weight of the at least one electronic component (encapsulant 517 is rigid and capable of preventing substrate 512 from collapsing due to a weight of the at least one electronic component as seen on fig. 6A). Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2016/0293581). a. Re claim 1, Lin et al disclose an electronic device, comprising: a first carrier (100e or 600 or 226 or 126; see fig. 3, and related text; see [0046], [0023] and remaining of disclosure for more details); a second carrier 326 (fig. 3, [0052]) disposed over the first carrier; and a reinforcement 304 connected to the second carrier and configured (i.e. capable) to prevent the second carrier from being recessed toward the first carrier (encapsulant 304 is an encapsulant as the described and claimed reinforcement and therefore is capable of performing the same claimed function; see MPEP 2112.01 (I. PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT) Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)). b. Re claim 5, wherein the second carrier comprises a plurality of conductive vias (see tapered via portion of interconnects 321) tapered toward the first carrier. Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al. (US 2020/0083172, cited on IDS). a. Re claim 1, Hsieh et al. disclose an electronic device, comprising: a first carrier 71 (see fig. 7 and related text; see [0035] and remaining of disclosure for more details); a second carrier 723 disposed over the first carrier; and a reinforcement 73 connected to the second carrier and configured (i.e. capable) to prevent the second carrier from being recessed toward the first carrier (encapsulant 73 is a rigid structure that is present between carrier 723 and carrier 71, and as such, is capable of preventing carrier 723 from being recessed toward carrier 71 as can be seen on fig. 7). b. Re claim 6, the reinforcement covers a lateral surface of the second carrier (explicit on fig. 7). Allowable Subject Matter Claims 7-10 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Takano et al. (US 2014/0151891) disclose a structure similar to the claimed invention wherein an encapsulant 33 is used to ensure rigidity of a substrate 13 (see [0060]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Feb 17, 2023
Application Filed
Jan 10, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604736
SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE
2y 5m to grant Granted Apr 14, 2026
Patent 12593394
HEAT TRANSFER FROM NON-GROUNDABLE ELECTRONIC COMPONENTS
2y 5m to grant Granted Mar 31, 2026
Patent 12593698
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12593581
DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12593673
SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
87%
With Interview (+3.7%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1302 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month