DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 05/06/2026 has been entered. The rejection of claims 1-2, 4-6, 8-14, and 16-19 under 35 U.S.C. § 112(b) set forth in the previous Office action is withdrawn in view of the amendments to claims 1, 6, and 13, which clarify the spatial relationship of the porous semiconductor material relative to the recited wells. Claims 1-20 are pending and under examination. Claims 3, 7, 15, and 20 remain withdrawn from consideration as being drawn to a nonelected invention. Claims 1, 2, 6, 13, and 14 have been amended. No new matter has been added.
Response to Arguments
Applicant’s arguments filed 4/14/2026 with respect to the rejections of claims 1-2, 4-6, 8-14, and 16-19 under 35 U.S.C. § 103 have been fully considered but are not persuasive. Regarding the arguments on pages 6-9 Maeda (US20010036690A1) expressly discloses that the trench-type isolation structure 16 "goes through the porous silicon layer 2" ([0065]; see also [0074]), confirming that the porous silicon layer 2 extends across the location between the wells. Maeda further discloses a first porous layer and an adjacent second porous layer "being connected to said first porous layer" as a buried layer (claim 9; [0020]; [0036]). Maeda therefore teaches porous semiconductor material spanning continuously between two adjacent wells. The rejections are maintained as restated below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1).
Regarding claim 1, Maeda teaches a structure (FIGS. 4, 5, and 14; semiconductor device) comprising:
a first well in a semiconductor substrate (n-well 18 in silicon substrate 10; [0065]);
a second well in the semiconductor substrate, adjacent to the first well (p-well 17 formed adjacent to n-well 18 in the silicon substrate 10, forming a pn junction at their interface; [0065], [0074]); and
a porous semiconductor material disposed partially in and extending between the first well and the second well (porous silicon layer 2 as a buried layer; Maeda discloses a first porous layer in a first semiconductor region and a second porous layer in an adjacent second semiconductor region “being connected to said first porous layer” (claim 9; [0020]; [0036]), the connected porous layers forming a continuous buried porous semiconductor material disposed partially in each of the first and second wells and extending between them).
Regarding claim 2, Maeda teaches the structure of claim 1, wherein the porous semiconductor material is at an interface of and spans uninterrupted between the first well which abuts the second well (the first and second porous layers are connected as a single buried porous layer (claim 9; [0020]), and the first semiconductor region (n-well 18) and the adjacent second semiconductor region (p-well 17) abut at their interface to form a pn junction ([0074]); the connected porous layer thus spans uninterrupted across the interface between the abutting wells).
Regarding claim 4, Maeda teaches the structure of claim 2, wherein the first well comprises an N-well (n-well 18) and the second well comprises a P-well (p-well 17) (FIGS. 12-14; [0065]).
Regarding claim 5, Maeda teaches the structure of claim 2, further comprising at least one shallow trench isolation structure at the interface of the first well and the second well (trench-type isolation structure 16 formed in the interface between the first and second semiconductor regions; [0065], [0074]; claim 9).
Regarding claim 6, Maeda teaches the structure of claim 5, wherein the porous semiconductor material is under the at least one shallow trench isolation structure and is completely below the at least one shallow trench isolation structure and does not extend to an upper surface of the semiconductor substrate, wherein the porous semiconductor material extends continually from the first well to the second well (porous silicon layer 2 is a buried layer formed inside the silicon region below the upper surface in which the well and source/drain regions are formed, [0058], [0060], FIGS. 4, 5, 14, such that the porous material is completely below and does not extend to the upper surface; and the first and second porous layers being connected as a buried layer (claim 9; [0020]; [0036]) extend continually from the first well to the second well).
Regarding claim 9, Maeda teaches the structure of claim 1, wherein the porous semiconductor material comprises porous silicon which extends laterally into the first well and the second well, below a top surface of the semiconductor substrate (porous silicon layer 2 as a buried layer, the first and second porous layers being connected ([0020]; [0058]; claim 9), extending laterally into both wells below the top surface of the substrate).
Claims 8, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1), and further in view of Gauthier (US20110147794A1).
Regarding claim 8, Maeda teaches the structure of claim 5, wherein the at least one shallow trench isolation structure comprises plural shallow trench isolation structures extending into the first well and the second well (FIG. 14, trench-type isolation structure 16 extending into n-well 18 and p-well 17).
But Maeda does not disclose isolating diffusion regions connecting to an anode and to a cathode.
However, Gauthier teaches the shallow trench isolation structures comprise plural shallow trench isolation structures extending into the first well and the second well (FIG. 1A, plurality of STIs extending into the n-well 101 and p-well 115), and isolating diffusion regions connecting to an anode (anode 130) and to a cathode (cathode 125).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Maeda by integrating the diffusion regions and isolation arrangement of the silicon controlled rectifier (SCR) of Gauthier, in order to improve performance as described in Gauthier [0006]. The combination is the use of a known technique to improve a similar device in the same way, yielding predictable results. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); MPEP 2143(I)(C), (D).
Regarding claim 13, Maeda teaches a structure (FIGS. 4, 5, and 14; semiconductor device) comprising:
a p-well in a semiconductor substrate (p-well 17 in silicon substrate 10; [0065]);
an n-well in the semiconductor substrate and abutting the p-well (n-well 18 formed adjacent to and abutting p-well 17, forming a pn junction at their interface; [0065], [0074]);
shallow trench isolation structures extending into the n-well and the p-well (trench-type isolation structure 16 extending into n-well 18 and p-well 17; [0065], [0074]); and
a porous semiconductor material disposed at junction of and spanning between the n-well and the p-well (porous silicon layer 2 as a buried layer; the first porous layer and the adjacent second porous layer being connected as a continuous buried layer (claim 9; [0020]; [0036]), disposed at the junction of the n-well and the p-well and spanning between them).
But Maeda does not disclose first diffusion regions in the n-well connecting to an anode; second diffusion regions in the p-well connecting to a cathode; and shallow trench isolation structures isolating the first diffusion regions and the second diffusion regions.
However, Gauthier teaches first diffusion regions in the n-well connecting to an anode (FIG. 1A, P+ region 130 forming the anode of the SCR 100); second diffusion regions in the p-well connecting to a cathode (N+ region 125 forming the cathode of the SCR 100); and shallow trench isolation structures isolating the first and second diffusion regions ([0026]; contacts and isolation for triggering the SCR 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Maeda to include the anode/cathode diffusion regions isolated by shallow trench isolation as taught by Gauthier, in order to provide an SCR configuration with improved performance, as described in Gauthier [0006]. See KSR, 550 U.S. at 417; MPEP 2143(I)(C), (D).
Regarding claim 16, Maeda in view of Gauthier teaches the structure of claim 13, wherein the porous semiconductor material comprises porous silicon ([0058], porous silicon layer 2 as a buried layer extending between the wells; claim 9, [0020]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1) in view of Gauthier (US20110147794A1) as applied to claim 13 above, and further in view of Huang (US20130161757A1).
Regarding claim 14, Maeda in view of Gauthier teaches the structure of claim 13, wherein the porous semiconductor material is under a shallow trench isolation structure at the junction of then-well and the p-well (Fig. 14 of Gauthier, trench- type isolation structure 16 extending into n-well 18 and p-well 17).
But Maeda does not disclose the porous semiconductor material is completely below the shallow trench isolation structure and does not extend to an upper surface of the semiconductor substrate.
However, Huang teaches the porous semiconductor material is completely below the shallow trench isolation structure and does not extend to an upper surface of the semiconductor substrate (porous silicon of additional isolation region 3 is completely under the STI region and an isolation region 4 and does not extend to an upper surface of the semiconductor substrate 1).
It would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the invention, to modify the structure and method for semiconductor device of Maeda (US20010036690A1) and by further integrating the alternative the structure and method for CMOS device of Huang (US20130161757A1). The combination of these familiar elements would improve the performances, as described in paragraph [0021] of Huang.
Claims 10-12 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1) as applied to claim 1, in view of Gauthier (US20110147794A1) as applied to claim 13 above, and further in view of Menard (US20150084094A1).
Regarding claims 10 and 17, Maeda teaches the structure of claim 1 and Maeda in view of Gauthier teaches the structure of claim 13 respectively, but does not disclose porous silicon emitter short-circuits 30 with a resistivity of 103 to 104 Ω.cm, and Para [0054] discloses that the porous silicon can be made more resistive than layer 7 by using a lower doping level.
However, Para [0026] of Menard discloses porous silicon emitter short-circuits 30 with a resistivity of 103 to 104 Ω.cm, and Para [0054] discloses that the porous silicon can be made more resistive than layer 7 by using a lower doping level.
It would have been obvious to one of ordinary skill in the art, based on common knowledge of porous silicon properties and doping control, to implement a porous semiconductor material with greater resistivity than the substrate, as all the claimed elements were well-known, or considered common knowledge in the art. In re Ahlert, 424 F.2d 1088, 1091, 165 USPQ 418, 420 (CCPA 1970).
Regarding claims 11 and 18, Maeda teaches the structure of claim 1 and Maeda in view of Gauthier teaches the structure of claim 13 respectively, but does not disclose the porous semiconductor material comprises an electrical resistivity greater than 1000 ohm-cm.
However, Menard teaches the porous semiconductor material comprises an electrical resistivity greater than 1000 ohm-cm (Para [0026] of Menard, porous silicon of emitter short-circuits 30 is selected in a range from 103 to 104 Ω.cm.).
Regarding claims 12 and 19, Maeda teaches the structure of claim 1 and Maeda in view of Gauthier teaches the structure of claim 13 respectively, but does not disclose he porous semiconductor material is free of crystalline grains and grain boundaries characteristic of a polycrystalline semiconductor material.
However, Para [0042] of Menard discloses that the porous silicon behaves differently from single-crystal silicon with respect to temperature-dependent resistivity, indicating a distinct material phase and structure. However, Menard does not explicitly teach whether the porous silicon is free of crystalline grains and grain boundaries, as required by claims 12 and 19.
It would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention, in view of the teachings related to the porous silicon fabricated by electrochemical or stain etching of single-crystal silicon substrates often results in either amorphous or nanocrystalline porous silicon, which lacks the well-defined crystalline grains and grain boundaries characteristic of polyproline silicon, as all the claimed elements were well-known, or considered common knowledge in the art. In re Ahlert, 424 F.2d 1088, 1091, 165 USPQ 418, 420 (CCPA 1970).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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