DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 5/12/2025 is acknowledged. Claims 1, 3, 7, 15 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim, and election was made without traverse in the amendment filed on 5/12/2025.
Therefore, claims 1-2, 4-6, 8-14 and 16-19 have been fully considered in examination.
Response to Arguments
Applicant’s arguments, filed on 9/4/2025, with respect to the rejection(s) of claim(s) 1-2, 4-6, 8-14, and 16-19 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1-2, 4-6, 8-14 and 16-19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a porous semiconductor material extending in the first well and second well”. It is unclear because it does not specify the spatial relationship between the porous semiconductor material and the first and second wells; whether the porous semiconductor material is continuous across the first and second wells, partially disposed within each well, or merely overlaps the wells.
Claim 6 recites “completely below”. It is unclear whether “below” is measured relative to the shallow trench isolation structure, the original semiconductor surface, or another structural boundary.
Claim 13 recites “a porous semiconductor material at junction of the n-well and the p-well”. It is unclear because it does not specify the spatial relationship between the porous semiconductor material and the n-well and p-wells; whether the porous semiconductor material is continuous across the n-well and p-wells, partially disposed within each well, or merely overlaps the wells.
Claims 2, 4-6, 8-12, 14 and 16-19 are also rejected being dependent upon rejected claims 1 and 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1).
Regarding claim 1, Maeda teaches a structure (Fig. 14, semiconductor device) comprising:
a first well (n-well 18) in a semiconductor substrate (silicon substrate 10);
a second well in the semiconductor substrate, adjacent to the first well (p-well 17 formed adjacent to p-well 17 in the silicon substrate 10, forming a pn junction); and
a porous semiconductor material extending in the first well and the second well (Para [0058], a porous silicon layer 2 as a buried layer, extending from p-well 17 to n-well 18).
It would have been obvious to one of ordinary skill in the art to form the porous semiconductor material such that it extends in the first well and the second well, since the relative placement and extent of a porous semiconductor region with respect to doped well regions is a matter of routine design choice and constitutes a predictable variation of Maeda.
Regarding claim 2, Maeda teaches the structure of claim 1, wherein the porous semiconductor material is at an interface of the first well which abuts the second well (Fig. 14, porous silicon layer 2 as a buried layer, extending from p-well 17 to n-well 18, at an interface where the p-well 17 and n-well 18 abut to form a pn junction).
Regarding claim 4, Maeda teaches the structure of claim 2, wherein the first well comprises an N-well (Fig. 14, n-well 18) and the second well comprises a P-well (p-well 17).
Regarding claim 5, Maeda teaches the structure of claim 2, further comprising at least one shallow trench isolation structure at the interface of the first well and the second well (Fig. 14, trench- type isolation structure 16).
Regarding claim 6, Maeda teaches the structure of claim 5, wherein the porous semiconductor material is under the at least one shallow trench isolation structure and the porous semiconductor material is completely below and does not extend to an upper surface of the semiconductor substrate (Fig. 14, porous silicon layer 2 is under the trench- type isolation structure 16 and does not extend to an upper surface of the silicon substrate 10).
Claim(s) 8-9, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1), and further in view of Gauthier (US20110147794A1).
Regarding claim 8, Maeda teaches the structure of claim 5, wherein the at least one shallow trench isolation structure comprises plural shallow trench isolation structures extending into the first well and the second well (Fig. 14, trench- type isolation structure 16 extending into n-well 18 and p-well 17) .
But Maeda does not disclose isolating diffusion regions connecting to an anode and to a cathode.
However, Gauthier teaches the wherein the at least one shallow trench isolation structure comprises plural shallow trench isolation structures extending into the first well and the second well (Fig. 1A, plurality of STIs extending into the n-well 101 and p-well 115), and isolating diffusion regions connecting to an anode (anode 130) and to a cathode (cathode 125).
It would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the invention, to modify the structure and method for semiconductor device of Maeda (US20010036690A1) and by further integrating the alternative the structure and method for a silicon controlled rectifier (SCR) of Gauthier (US20110147794A1). The combination of these familiar elements would improve the performances, as described in paragraph [0006] of Gauthier.
Regarding claim 9, Maeda teaches the structure of claim 1, wherein the porous semiconductor material comprises porous silicon which extends laterally into the first well and the second well (Para [0058], a porous silicon layer 2 as a buried layer, extending from p-well 17 to n-well 18).
But Maeda does not disclose the porous semiconductor material is below a top surface of the semiconductor substrate.
However, Gauthier teaches a top surface of the semiconductor substrate 105 is covering both side of the p-well 115 and n-well 110 (Fig. 1A), so that by using the method and structure of Gauthier in the semiconductor device of Menard, the device would comprise the porous semiconductor material is below a top surface of the semiconductor substrate.
It would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the invention, to modify the structure and method for semiconductor device of Maeda (US20010036690A1) and by further integrating the alternative the structure and method for a silicon controlled rectifier (SCR) of Gauthier (US20110147794A1). The combination of these familiar elements would improve the performances, as described in paragraph [0006] of Gauthier.
Regarding claim 13, Maeda teaches a structure (Fig. 14, semiconductor device) comprising:
a p-well (p-well 17) in a semiconductor substrate (silicon substrate 10);
an n-well in the semiconductor substrate and abutting the p-well (p-well 17 formed adjacent to p-well 17 in the silicon substrate 10, forming a pn junction);
shallow trench isolation structures extending into the n-well and the p-well (Fig. 14, trench- type isolation structure 16 extending into n-well 18 and p-well 17); and
a porous semiconductor material at junction of the n-well and the p-well (Para [0058], a porous silicon layer 2 as a buried layer, extending from p-well 17 to n-well 18).
But Maeda does not disclose first diffusion regions in the n-well connecting to an anode; second diffusion regions in the p-well and connecting to a cathode; and shallow trench isolation structures isolating the first diffusion regions and the second diffusion regions.
However, Gauthier teaches first diffusion regions in the n-well connecting to an anode (Fig. 1A, P+ region 130 forms the anode of the SCR 100);
second diffusion regions in the p-well and connecting to a cathode (N+ region 125 forms the cathode of the SCR 100); and
shallow trench isolation structures isolating the first diffusion regions and the second diffusion regions (Para [0026], contact 13 for the N+ region 135 and a contact 122 for the P+ region 120 for triggering the SCR 100).
It would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the invention, to modify the structure and method for semiconductor device of Maeda (US20010036690A1) and by further integrating the alternative the structure and method for a silicon controlled rectifier (SCR) of Gauthier (US20110147794A1). The combination of these familiar elements would improve the performances, as described in paragraph [0006] of Gauthier.
Regarding claim 16, Maeda in view of Gauthier teaches the structure of 13, Maeda teaches the porous semiconductor material comprises porous silicon which extends laterally into the first well and the second well (Para [0058], a porous silicon layer 2 as a buried layer, extending from p-well 17 to n-well 18).
But Maeda does not disclose the porous semiconductor material is below a top surface of the semiconductor substrate.
However, Gauthier teaches a top surface of the semiconductor substrate 105 is covering both side of the p-well 115 and n-well 110 (Fig. 1A), so that by using the method and structure of Gauthier in the semiconductor device of Menard, the device would comprise the porous semiconductor material is below a top surface of the semiconductor substrate.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1) in view of Gauthier (US20110147794A1) as applied to claim 13 above, and further in view of Huang (US20130161757A1).
Regarding claim 14, Gauthier in view of Menard teaches the structure of claim 13, wherein the porous semiconductor material is under a shallow trench isolation structure at the junction of then-well and the p-well (Fig. 14 of Gauthier, trench- type isolation structure 16 extending into n-well 18 and p-well 17).
But Gauthier does not disclose the porous semiconductor material is completely below the shallow trench isolation structure and does not extend to an upper surface of the semiconductor substrate.
However, Huang teaches the porous semiconductor material is completely below the shallow trench isolation structure and does not extend to an upper surface of the semiconductor substrate (porous silicon of additional isolation region 3 is completely under the STI region and an isolation region 4 and does not extend to an upper surface of the semiconductor substrate 1).
It would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the invention, to modify the structure and method for semiconductor device of Maeda (US20010036690A1) and by further integrating the alternative the structure and method for CMOS device of Huang (US20130161757A1). The combination of these familiar elements would improve the performances, as described in paragraph [0021] of Huang.
Claim(s) 10-12, 17-19, is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US20010036690A1) as applied to claim 1, Maeda (US20010036690A1) in view of Gauthier (US20110147794A1) as applied to claim 13 above, and further in view of Menard (US20150084094A1).
Regarding claims 10 and 17, Maeda teaches the structure of claim 1 and Maeda in view of Gauthier teaches the structure of claim 13 respectively, but does not disclose porous silicon emitter short-circuits 30 with a resistivity of 103 to 104 Ω.cm, and Para [0054] discloses that the porous silicon can be made more resistive than layer 7 by using a lower doping level.
However, Para [0026] of Menard discloses porous silicon emitter short-circuits 30 with a resistivity of 103 to 104 Ω.cm, and Para [0054] discloses that the porous silicon can be made more resistive than layer 7 by using a lower doping level.
It would have been obvious to one of ordinary skill in the art, based on common knowledge of porous silicon properties and doping control, to implement a porous semiconductor material with greater resistivity than the substrate, as all the claimed elements were well-known, or considered common knowledge in the art. In re Ahlert, 424 F.2d 1088, 1091, 165 USPQ 418, 420 (CCPA 1970).
Regarding claims 11 and 18, Maeda teaches the structure of claim 1 and Maeda in view of Gauthier teaches the structure of claim 13 respectively, but does not disclose the porous semiconductor material comprises an electrical resistivity greater than 1000 ohm-cm.
However, Menard teaches the porous semiconductor material comprises an electrical resistivity greater than 1000 ohm-cm (Para [0026] of Menard, porous silicon of emitter short-circuits 30 is selected in a range from 103 to 104 Ω.cm.).
Regarding claims 12 and 19, Gauthier in view of Menard teaches the structure of claims 1 and 13 respectively, but does not disclose he porous semiconductor material is free of crystalline grains and grain boundaries characteristic of a polycrystalline semiconductor material.
However, Para [0042] of Menard discloses that the porous silicon behaves differently from single-crystal silicon with respect to temperature-dependent resistivity, indicating a distinct material phase and structure. However, Menard does not explicitly teach whether the porous silicon is free of crystalline grains and grain boundaries, as required by claims 12 and 19.
It would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention, in view of the teachings related to the porous silicon fabricated by electrochemical or stain etching of single-crystal silicon substrates often results in either amorphous or nanocrystalline porous silicon, which lacks the well-defined crystalline grains and grain boundaries characteristic of polyproline silicon, as all the claimed elements were well-known, or considered common knowledge in the art. In re Ahlert, 424 F.2d 1088, 1091, 165 USPQ 418, 420 (CCPA 1970).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/ Examiner, Art Unit 2897