Prosecution Insights
Last updated: May 29, 2026
Application No. 18/112,707

METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE WITH REDUCED ENCROACHMENT OF ACTIVE REGIONS AND A SEMICONDUCTOR STRUCTURE THEREFROM

Non-Final OA §103
Filed
Feb 22, 2023
Priority
Aug 25, 2021 — divisional of 11/688,624
Examiner
SLUTSKER, JULIA
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nanya Technology Corporation
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
822 granted / 1067 resolved
+9.0% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
29 currently pending
Career history
1118
Total Applications
across all art units

Statute-Specific Performance

§103
87.4%
+47.4% vs TC avg
§102
6.9%
-33.1% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1067 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Sawada (US 2015/0221722) in view of DE’210 (DE 10025210, Machine Translation is provided) and Applicant’s Admission of the Prior Art (AAPA). Regarding claim 1, Sawada discloses a semiconductor structure, comprising: a silicon substrate (Fig.4, numerals 1; [0058]); a plurality of first trenches (W3) with one or more sizes filled with a first dielectric material (Fig. 4, numeral 9C) formed in the silicon substrate (1) along a first dimension; a plurality of second trenches (W1) with one or more sizes filled with a second dielectric material (9a) formed in the silicon substrate (1) along a second dimension; and a plurality of active regions (Fig.9, numeral 1a; 1c; 1b) with one or more sizes formed in the silicon substrate (1), wherein each of the active regions is rectangular-shaped and separated from each other by the first trenches (5) filled with the first dielectric material and the second trenches (4) filled with the second dielectric material (Fig.9). Sawada does not disclose (1) that the plurality of the active regions forming MOS transistor has round corners at two ends where contact provided external electrical connection with source/drain regions of the MOS transistors land on; (2) that the second dimension is perpendicular to the first dimension. Regarding element (1), DE’210 however discloses that the plurality of the active regions has round corners (Fig.2, numeral 11) at two ends where contact (Fig.3, numeral 13) provided external electrical connection with source/drain regions of the MOS transistors land on (Fig. 9, numeral 80). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Sawada with DE’210 to have the plurality of the active regions forming MOS transistor has round corners at two ends where contact provided external electrical connection with source/drain regions of the MOS transistors land on for the purpose increasing the drain current of a transistor (DE’210; column 5, lines 35-30). Regarding element (2), AAPA discloses that the second dimension is perpendicular to the first dimension (Fig.5A). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Sawada with AAPA to have the second dimension is perpendicular to the first dimension because this is a tradition method for forming active regions and STI structures (Applicant’s Specification, [0004]). Regarding claim 2, Sawada discloses wherein the first trench has a different size from that of the second trench (Fig. 4; numerals W3; W1). Regarding claim 3, Sawada does not disclose where the first trenches are interdigitated with the second trenches. AAPA however discloses where the first trenches are interdigitated with the second trenches (Fig.5A). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Sawada with AAPA to have the first trenches are interdigitated with the second trenches because this is a tradition method for forming active regions and STI structures (Applicant’s Specification, [0004]). Response to Arguments Applicant’s arguments with respect to claim(s) 1-3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JULIA SLUTSKER/Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Feb 22, 2023
Application Filed
Jun 17, 2025
Non-Final Rejection mailed — §103
Sep 02, 2025
Response Filed
Oct 21, 2025
Final Rejection mailed — §103
Jan 05, 2026
Request for Continued Examination
Jan 23, 2026
Response after Non-Final Action
Feb 05, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.6%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1067 resolved cases by this examiner. Grant probability derived from career allowance rate.

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