Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0029420, filed on 3/6/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maegawa (US 20210183827 A1) in view of Kaloyeros et al.
Regarding claim 1, Maegawa teaches, in FIG. 14, a portion of a display device with a “pixel area” 1 (display area) and a “dummy area” 2 (non-display area) on a substrate 30 with “light emitting layer[s]” 12 (light emitting elements), a ”passivation film” 27 (overcoat layer) over the light emitting elements which extends from the display area to the non-display area, and “light shielding layer” 24 (barrier layer) disposed over the overcoat layer in the non-display layer, and not disposed in the display area.
However, Maegawa does not teach that the barrier layer comprises silicon nitride.
Kaloyeros et al teaches, in paragraph 1: “the appeal of [silicon nitride] based coatings is attributed to their highly desirable combination of physical, mechanical, electrical, and optoelectronic properties” and in paragraph 4: “SiNxCy and SiNx coatings are used or suggested as passivation layers in flexible electroluminescent devices.”
It would have been obvious to combine the Maegawa and Kaloyeros et al such that the barrier layer, which is itself part of the larger display device taught by Maegawa, comprises silicon nitride, as taught and motivated by Kaloyeros. This is prima facie obviousness because it amounts to the use of known materials for their known purpose. See KSR Internation Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 2-6, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maegawa (US 20210183827 A1) in view of Kaloyeros et al, in further view of Park (US 20140191256 A1).
Regarding claim 2, Park teaches, in FIG. 25c. a pad portion comprising “drain electrode” 175 (which one having ordinary skill in the art will apricate as functioning as a pad electrode, as it is exposed) in a non-display area, in which a “photosensitive film pattern” 400a (which one having ordinary skill in the art would appreciate as functioning as a barrier layer) is not disposed in the pad portion. The examiner also notes that the context of the invention implies the aforementioned structure is employed in the plural.
It would have been obvious to one having ordinary skill in the art to combine Maegawa with Kaloyeros et al and Park such that the display device and composition taught by Maegowa and Kaloyeros et al comprises a pad portion described above as taught by Park. One having ordinary skill the art would be motivated create such a structure in order to provide contacts to external driving circuits.
Regarding claim 3, Maegawa further teaches, in FIG. 2, that the barrier layer 24 surrounds a display area.
Regarding claim 4, Park further teaches, in FIG. 25C, that a pad portion comprises a first pad hole in barrier layer 400a and a second pad hole in “organic layer” 180y, which overlap in plan view.
It would have been obvious to one having ordinary skill in the art to combine Maegawa with Kaloyeros and Park such that the display device and composition taught by Maegawa and Kaloyeros comprises a first and second pad hole exposing the pad electrodes. One having ordinary skill in the art would be motivated to do this in order to recess the pad electrode, allowing it to more easily couple to other buried components.
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Regarding claim 5, Park further teaches, in FIG. 25C, that a width of the first pad hole is less than a width of the second pad hole in a direction perpendicular to the thickness direction of the substrate:
Regarding claim 6, as shown above, Park teaches a first pad hole in an overcoat layer (as explained above) and a second pad hole in “organic layer” 180y. The examiner notes that the “organic layer” 180y could be appreciated by one having ordinary skill in the art to function as an overcoat layer. The examiner also notes that the second hole, in this context, provides a path through both the barrier and overcoat layer, and therefore penetrates both layers.
Regarding claim 14, Maegawa teaches a display area, light emitting elements on a substrate in the display area, an overcoat layer on both the display area and a non-display area, and a barrier layer on the overcoat layer in the non-display area, as shown above. Additionally, Kaloyeros et al teaches that this overcoat can be made of silicon nitride, and Park teaches a pad portion in which pad electrodes are disposed, as shown above.
Regarding claim 15, Park further teaches a pad hole penetrating the overcoat layer and exposing the pad electrodes with the barrier layer disposed in the pad hole, in FIG. 25C.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maegawa (US 20210183827 A1) in view of Kaloyeros et al, in further view of Park (US 20140191256 A1) and Son (US 20190181198 A1).
Regarding claim 7, Maegawa, Kaloyeros et al, and Park teach the limitations of claim 6, but do not teach a first and second top surface in the overcoat layer.
Son teaches, in FIG. 7L, a series of insulating layers 10, 20, 30, 40 (which one having ordinary skill in the art will appreciate to be a barrier layer) and buffer layer BLF, barrier layer BRL, and buried layer BL (which one of ordinary skill in the art will appreciate to be an overcoat layer). The overcoat layer has a first and second lateral side which are connected by a first top surface, and a second top surface connected to the first lateral side.
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It would have been obvious to one having ordinary skill in the art to combine Maegawa, Kaloyeros et al and Park with Son such that the pad hole taught by Park comprises the first and second lateral sides and top surfaces taught by Son. One having ordinary skill in the art would be motivated to do so in order to maximize the surface area of the “top” surfaces so as to reduce stress on the substrate when objects are mounted in the contact pad holes.
Regarding claim 8, Son further teaches that the first and second lateral sides of the overcoat layer are aligned and coincide with each other in the second pad hole (as the lines of the surfaces are parallel), as shown in the FIG. 7L.
Regarding claim 9, Son further teaches that the barrier layer contacts the second top surface of the overcoat layer, as shown in 7L.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maegawa (US 20210183827 A1) in view of Kaloyeros et al, in further view of Song (US 20200381502 A1).
Regarding claim 10, Maegawa and Kaloyeros et al teach the limitations of claim 1, however, they do not teach a dam and a hole portion in the non-display area.
Song teaches, in FIG. 6 a “first dam” 610 and a “second dam” 620 with a hole portion therebetween in a “peripheral area” Pa (non-display area). Further, a “first organic layer” (which one of ordinary skill in the art will appreciate to function as a barrier layer) and a “second inorganic layer” 530 (disposed on the barrier layer), which one of ordinary skill in the art will appreciate to be an overcoat layer both overlap the dam and the hole portion in a plan view. Finally, FIG. 4 shows that this structure surrounds the display are in plan view.
It would have been obvious to one having ordinary skill in the art to combine Maegawa and Kaloyeros et al with Song such that the overall semiconductor structure and composition taught by Maegawa and Kaloyeros et al comprises a dam and hole portion as above described above by Song. One having ordinary skill in the art would be motivated to make a dam and a hole portion in order to prevent the overflow of display-area coatings into the non-display area.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maegawa (US 20210183827 A1) in view of Kaloyeros et al, in further view of Y. Park (US 20220037623 A1).
Regarding claim 11, Maegawa and Kaloyeros et al teach the display panel shown above, however, they do not teach specific capping layers, a low reflective layer oriented on a capping layer, and a color filter layer.
Y. Park teaches, in FIG. 10, light emitting elements LD, a first capping layer CP1 on the light emitting elements, a low refractive layer LRL disposed on the first capping layer, a second capping layer CP2 disposed on the low-refractive layer, and a color filter layer CFL. Further, in the summary section, Y. Park teaches “the present disclosure provides a low refractive layer capable of improving display quality and light efficiency” and “the second capping layer CPL2 may prevent or reduce permeation of impurities such as external moisture and/or air into the color filter layer CFL” (paragraph 0195).
It would have been obvious to one having ordinary skill in the art to combine Maegawa and Kaloyeros et all with Y. Park such that the display region comprises the various light layers taught by Y. Park. One having ordinary skill in the art is motivated to include the low refractive layer and capping layers for the reasons taught by park, ordinary skill in the art is apprised of the reasons to include a color filter layer (i.e. to ensure purity of color displayed).
Regarding claim 12, Y. Park further teaches, in paragraph 0207, “in one exemplary embodiment, a space between a lower plate of a display panel PNL including the substrate SUB and a display layer DPL, and an upper plate of the display panel PNL including the upper substrate UPL, the color filter layer CFL, the low refractive layer LRL, and the color conversion layer CCL may be filled with an overcoat layer OC.” The examiner notes that placing the overcoat layer between the substrate and encapsulation layer ENC of FIG. 7 places the overcoat layer on the color filter layer.
Regarding claim 13, Y. Park teaches that an overcoat layer can be disposed between the color filter layer and the substrate, meaning that the overcoat layer would be disposed between the color filter layer and the second capping layer as it appears in FIG. 7.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maegawa (US 20210183827 A1) in view of Kaloyeros et al, in further view of Park (US 20140191256 A1) and Yoon (US 20190334061 A1).
Regarding claim 16, Maegawa, Kaloyeros et al, and Park teach the limitations of claim 14, but do not teach a via exposed by the pad hole.
Yoon teaches, in FIG. 1, a recessed region ME, which does not include light emitting elements, and a “transparent electrode layer” 120 (which one having ordinary skill in the art will appreciate to be a via) extending from the non-display region to the region with display elements (display area). FIG. 15A shows a “plurality of insulating layers” 140P and “extended portion of the insulating pattern 140S” (paragraph 0049), which one having ordinary skill in the art would appreciate to be overcoat and barrier layers, respectively. Additionally, the top surface of the via layer is exposed by a pad hole.
It would have been obvious to one having ordinary skill in the art to modify Maegawa, Kaloyeros et al, and Park with Shin such that the above described display panel comprises the via layer taught by Shin. One having ordinary skill in the art motivated to create such a via as an obvious means of electrically connecting an external data source to light emitting elements.
Regarding claim 17, Yoon further teaches, in FIG. 15A features the barrier layer in contact with the top surface of the via layer in the pad hole.
It would have been obvious to one having ordinary skill in the art to combine Maegawa, Kaloyeros et al, and Park with Yoon such that the above panel structure features the barrier layer in contact with the top surface of the via layer in the pad hole. This is because depositing the barrier layer on the overcoat layer after creating the via in the overcoat layer creates the option to either have the barrier layer not overlap the hole, overlap the hole partially, or overlap the hole as it is described above (touching the via with an opening in the middle), and therefore the above described structure is one of three well defined, predictable outcomes. See KSR Internation Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 18, Yoon further teaches, in FIG. 15A, that the barrier layer covers a lateral side of the overcoat layer corresponding to an inner circumferential surface of the pad hole and contacts the lateral side of the overcoat layer.
It would have been obvious to one having ordinary skill in the art to modify the aforementioned display panel such that the barrier layer covers and is in contact with the lateral side of the inner circumferential surface of the pad hole, as this is a property of two of the three obvious design choices one can make when designing a pad hole in an overcoat layer with a barrier layer directly thereupon. See above and KSR Internation Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 19, Maegawa, Kaloyeros et al, and Park teach the limitations of claim 14, but they do not teach two electrodes spaced across from each other with an insulating layer disposed on both electrodes.
Kim teaches, in FIG. 6, two “connection patterns” (one of which is labeled CNP, the other, to its right, is unlabeled, both of which are appreciated by one of ordinary skill in the art to be electrodes) on a substrate and spaced across from one another. A “sealing layer” SL1 (insulating layer) is on these electrodes. In addition, a first and second electrode (one of which is labeled EL1, the other is to the right of the labeled specimen) are in electrical contact with light emitting elements OL. Further, in “Description of Related Art,” Kim explains that the aforementioned structure solves “a problem in that an aperture is decreased by a black matrix positioned between the respective pixels and high resolution display performance is degraded.”
Regarding claim 20, Maegawa further teaches, in FIG. 1 an ”N side layer” 11, a “light emitting layer” 12, and a “P side layer” 13 disposed such that the emission layer is between the P-type and N-type layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897