DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 10/21/2025. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 03/28/2023.
Oath/Declaration
The oath or declaration filed on 02/23/2023 is acceptable.
Election/Restrictions
Applicant’s election of species II (Fig 5-6): claims 1-18 in the reply filed on 10/21/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). The election is without traverse because the response is incomplete.
This office action considers claims 1-20 pending for prosecution, wherein claims 19-20 are withdrawn from further consideration, and 1-18 are presented for examination.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over KINOSHITA et al (US 2018/0012960 A1; hereafter KINOSHITA) in view of Zhao (US 2019/0157081 A1; hereafter Zhao).
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Regarding claim 1, KINOSHITA discloses a high electron mobility transistor (HEMT), comprising:
a substrate (Fig. [8], substrate 120);
a channel layer (Fig. [8], channel 202, para [ 0096]) disposed on the substrate (Fig. [8], substrate 120);
a barrier layer (nitride semiconductor layer 203, construed as barrier layer, Para [ 0096]) disposed on the channel layer (Fig. [8], channel 202, para [ 0096]);
a P-type III-V composition layer (Fig. [8], p-type nitride semiconductor layer 105, Para [ 0115]) disposed on the barrier layer (nitride semiconductor layer 203, construed as barrier layer, Para [ 0096]);
a gate electrode (Gate electrode 106, Para [ 0065]) disposed on the P-type III-V composition layer (Fig. [8], p-type nitride semiconductor layer 105, Para [ 0115]); and
a layer (nitride semiconductor layer 204, construed as a layer, Para [ 0086]) disposed on the channel layer (Fig. [8], channel 202, para [ 0096]), between the P-type III-V composition layer (Fig. [8], p-type nitride semiconductor layer 105, Para [ 0115]) and the barrier layer (nitride semiconductor layer 203, construed as barrier layer, Para [ 0096]), wherein the layer comprises a sunken surface (nitride semiconductor layer 204, Para [ 0086]).
But KINOSHITA does not disclose explicitly layer is carbon containing layer.
In a similar field of endeavor, Zhao discloses layer is carbon containing layer (Para [0077] discloses “C—GaN denoting “carbon-doped GaN” with a carbon concentration of about 2E19 cm.sup.−3”).
Since KINOSHITA and Zhao are both from the similar field of endeavor, and Zhao discloses carbon doped nitride semiconductor layer. Therefore, the purpose disclosed by Zhao would have been recognized in the pertinent art of KINOSHITA.
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of Zhao teaching “a layer is carbon containing layer (Para [0077] discloses “C—GaN denoting “carbon-doped GaN” with a carbon concentration of about 2E19 cm.sup.−3”)” for further advantage such carbon dopants GaN are unique as sub-bandgap states that act as a donor, acceptor and simultaneously block high voltages with low leakage currents.
Regarding claim 2, KINOSHITA and Zhao disclose the high electron mobility transistor according to claim 1, Zhao further discloses wherein a dopant concentration of carbon in the carbon containing layer is 1E15-1E21/cm3 (Para [0077]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of Zhao teaching “wherein a dopant concentration of carbon in the carbon containing layer is 1E15-1E21/cm3 (Para [0077])” with a carbon concentration of about 2E19 cm.sup.−3”)” for further advantage such carbon dopants GaN are unique as sub-bandgap states that act as a donor, acceptor and simultaneously block high voltages with low leakage currents.
Regarding claim 3, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 1, Zhao further discloses wherein the carbon containing layer comprises silicon carbide, or carbon doped III-V compound (Para [0077]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of Zhao teaching “wherein the carbon containing layer comprises silicon carbide, or carbon doped III-V compound” with a carbon concentration of about 2E19 cm.sup.−3”)” for further advantage such carbon dopants GaN are unique as sub-bandgap states that act as a donor, acceptor and simultaneously block high voltages with low leakage currents.
Regarding claim 4, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 3, Zhao further discloses wherein the carbon doped III-V compound comprises carbon doped gallium nitride (C:GaN), carbon doped aluminum gallium nitride (C:AlGaN), carbon doped silicon (C:Si) or carbon doped boron nitride (C:BN) (Para [0077]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of Zhao teaching “wherein the carbon doped III-V compound comprises carbon doped gallium nitride (C:GaN), carbon doped aluminum gallium nitride (C:AlGaN), carbon doped silicon (C:Si) or carbon doped boron nitride (C:BN) (Para [0077])” for further advantage such carbon dopants GaN are unique as sub-bandgap states that act as a donor, acceptor and simultaneously block high voltages with low leakage currents.
Regarding claim 6, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 1, KINOSHITA further discloses wherein the P-type III-V composition layer comprises a divalent dopant (Para [ 0066]).
Regarding claim 7, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 6, KINOSHITA further discloses wherein the divalent dopant comprises magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be) or iron (Fe) (Para [ 0066]).
Regarding claim 8, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 1, KINOSHITA further discloses wherein the barrier layer comprises Al1iGa1ixN, and the X1 is a constant greater than 0 and less than 1 (Para [ 0103]).
Regarding claim 15, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 1, KINOSHITA further discloses further comprising a source electrode (source electrode 107, Para [ 0073]) and a drain electrode (drain electrode 108, Para [ 0074]) disposed on the layer (nitride semiconductor layer 204, construed as a layer, Para [ 0086]), at two sides of the gate electrode (gate electrode 106, Para [ 0076]).
But KINOSHITA does not disclose explicitly layer is carbon containing layer.
In a similar field of endeavor, Zhao discloses layer is carbon containing layer (Para [0077] discloses “C—GaN denoting “carbon-doped GaN” with a carbon concentration of about 2E19 cm.sup.−3”).
Since KINOSHITA and Zhao are both from the similar field of endeavor, and Zhao discloses carbon doped nitride semiconductor layer. Therefore, the purpose disclosed by Zhao would have been recognized in the pertinent art of KINOSHITA.
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of Zhao teaching “a layer is carbon containing layer (Para [0077] discloses “C—GaN denoting “carbon-doped GaN” with a carbon concentration of about 2E19 cm.sup.−3”)” for further advantage such carbon dopants GaN are unique as sub-bandgap states that act as a donor, acceptor and simultaneously block high voltages with low leakage currents.
Regarding claim 17, KINOSHITA discloses a method of forming a high electron mobility transistor (Fig. [8]), comprising:
providing a substrate (Fig. [8], substrate 120);
forming a channel layer (Fig. [8], channel 202, para [ 0096]) on the substrate (Fig. [8], substrate 120);
forming a barrier layer (nitride semiconductor layer 203, construed as barrier layer, Para [ 0096]) on the channel layer (Fig. [8], channel 202, para [ 0096]);
forming a P-type III-V composition layer (Fig. [8], p-type nitride semiconductor layer 105, Para [ 0115]) on the barrier layer (nitride semiconductor layer 203, construed as barrier layer, Para [ 0096]);
forming a gate electrode (Gate electrode 106, Para [ 0065]) on the P-type III-V composition layer (Fig. [8], p-type nitride semiconductor layer 105, Para [ 0115]); and
forming a layer (nitride semiconductor layer 204, construed as a layer, Para [ 0086]) on the channel layer (Fig. [8], channel 202, para [ 0096]), between the P-type III-V composition layer (Fig. [8], p-type nitride semiconductor layer 105, Para [ 0115]) and the barrier layer (nitride semiconductor layer 203, construed as barrier layer, Para [ 0096]), wherein the layer comprises a sunken surface (nitride semiconductor layer 204, Para [ 0086]).
But KINOSHITA does not disclose explicitly layer is carbon containing layer.
In a similar field of endeavor, Zhao discloses layer is carbon containing layer (Para [0077] discloses “C—GaN denoting “carbon-doped GaN” with a carbon concentration of about 2E19 cm.sup.−3”).
Since KINOSHITA and Zhao are both from the similar field of endeavor, and Zhao discloses carbon doped nitride semiconductor layer. Therefore, the purpose disclosed by Zhao would have been recognized in the pertinent art of KINOSHITA.
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of Zhao teaching “a layer is carbon containing layer (Para [0077] discloses “C—GaN denoting “carbon-doped GaN” with a carbon concentration of about 2E19 cm.sup.−3”)” for further advantage such carbon dopants GaN are unique as sub-bandgap states that act as a donor, acceptor and simultaneously block high voltages with low leakage currents.
Claims 5, 9-10 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over KINOSHITA et al (US 2018/0012960 A1; hereafter KINOSHITA) in view of Zhao (US 2019/0157081 A1; hereafter Zhao) as applied claims above and further in view of Ramer et al (US 2016/0099345 A1; hereafter Ramer).
Regarding claim 5, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 1, KINOSHITA further discloses wherein the P-type III-V composition layer comprises a first thickness (P-type nitride semiconductor layer 105 is, for example, a p-type GaN layer having a film thickness of approximately 100 nm, Para [ 0066]).
But KINOSHITA and Zhao do not disclose explicitly the carbon containing layer comprises a second thickness, and the second thickness is 1/10~1/100 of the first thickness.
In a similar field of endeavor, Ramer discloses the carbon containing layer comprises a second thickness, and the second thickness is 1/10~1/100 of the first thickness (“one or more carbon doped gallium nitride (c-GaN) layers is grown to a thickness greater than 1 nm and less than 500 nm”, Para [ 0014], based on that, second thickness can be 1/10~1/100 of the first thickness).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA and Zhao in light of Ramer teaching “the carbon containing layer comprises a second thickness, and the second thickness is 1/10~1/100 of the first thickness ( one or more carbon doped gallium nitride (c-GaN) layers is grown to a thickness greater than 1 nm and less than 500 nm, Para [ 0014], based on that, second thickness can be 1/10~1/100 of the first thickness)” for further advantage such as to achieve desire thickness and improves withstand voltage characteristic of the gate of the device.
Regarding claim 9, KINOSHITA and Zhao disclose the high electron mobility transistor according to claim 1, But KINOSHITA and Zhao do not disclose explicitly further comprising:
another carbon containing layer disposed on the channel layer, between the buffer layer and the channel layer, wherein the another carbon containing layer comprises a planar surface and a dopant concentration of carbon in the carbon containing layer is 1E15-1E21/cm3.
In a similar field of endeavor, Ramer discloses another carbon containing layer disposed on the channel layer, between the buffer layer and the channel layer (Fig 2, channel layer stack 206 is formed by epitaxially growing alternating layers of undoped gallium nitride (GaN) 221, 223, and 225, and layers of carbon doped gallium nitride (c-GaN) 220, 222, 224, and 226. Examiner interpreted carbon doped layer 222 disposed between layer 204, as barrier layer and layer 224, as channel layer), wherein the another carbon containing layer comprises a planar surface and a dopant concentration of carbon in the carbon containing layer is 1E15-1E21/cm3 (Fig 2A, carbon doped layer 222, Para [0030-0031]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA and Zhao in light of Ramer teaching “another carbon containing layer disposed on the channel layer, between the buffer layer and the channel layer (Fig 2, channel layer stack 206 is formed by epitaxially growing alternating layers of undoped gallium nitride (GaN) 221, 223, and 225, and layers of carbon doped gallium nitride (c-GaN) 220, 222, 224, and 226. Examiner interpreted carbon doped layer 222 disposed between layer 204, as barrier layer and layer 224, as channel layer), wherein the another carbon containing layer comprises a planar surface and a dopant concentration of carbon in the carbon containing layer is 1E15-1E21/cm3 (Fig 2A, carbon doped layer 222, Para [0030-0031])” for further advantage such as to provide positive threshold voltage, reduces the gate leakage of the device, and improves the withstand voltage characteristic of the gate of the device.
Regarding claim 10, KINOSHITA and Zhao in light of Ramer disclose the high electron mobility transistor according to claim 9, Ramer further discloses further comprising:
a spacer layer (Fig 2, undoped gallium nitride GaN 221, construed as spacer layer, Para [ 0030-0031]) disposed between the barrier layer (layer 204, as barrier layer, Para [ 0030-0031]) and the channel layer (Fig 2, layer 224, as channel layer, Para [ 0030-0031]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA and Zhao in light of Ramer teaching “(Fig 2, undoped gallium nitride GaN 221, Para [ 0030-0031]) disposed between the barrier layer (layer 204, as barrier layer, Para [ 0030-0031]) and the channel layer (Fig 2, layer 224, as channel layer, Para [ 0030-0031])” for further advantage such as to provide positive threshold voltage, reduces the gate leakage of the device, and improves the withstand voltage characteristic of the gate of the device.
Regarding claim 12, KINOSHITA and Zhao in light of Ramer disclose the high electron mobility transistor according to claim 10, Ramer further discloses wherein the spacer layer (Fig 2, undoped gallium nitride GaN 221, construed as spacer layer, Para [ 0030-0031]) is disposed under the another carbon containing layer (carbon doped layer 222, Para [ 0030-0031]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA and Zhao in light of Ramer teaching “wherein the spacer layer (Fig 2, undoped gallium nitride GaN 221, construed as spacer layer, Para [ 0030-0031]) is disposed under the another carbon containing layer (carbon doped layer 222, Para [ 0030-0031])” for further advantage such as to provide positive threshold voltage, reduces the gate leakage of the device, and improves the withstand voltage characteristic of the gate of the device.
Regarding claim 13, KINOSHITA and Zhao in light of Ramer disclose the high electron mobility transistor according to claim 10, KINOSHITA further discloses wherein the barrier layer comprises Alx2Gal-X2N, and the x2 is a constant greater than or equal to 0 and less than 1(nitride semiconductor layer 203, construed as barrier layer, Para [ 0090, 0096]).
Regarding claim 14, KINOSHITA and Zhao in light of Ramer disclose high electron mobility transistor according to claim 13, Ramer further discloses wherein the spacer layer comprises a III-V material (Fig 2, undoped gallium nitride GaN 221, construed as spacer layer, Para [ 0030-0031]) which is different from a III-V material of the barrier layer (buffer layer 204 can be gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), Para [ 0027], construed as barrier layer).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA and Zhao in light of Ramer teaching “wherein the spacer layer comprises a III-V material (Fig 2, undoped gallium nitride GaN 221, construed as spacer layer, Para [ 0030-0031]) which is different from a III-V material of the barrier layer (buffer layer 204 can be gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), Para [ 0027], construed as barrier layer)” for further advantage such as to provide positive threshold voltage, reduces the gate leakage of the device, and improves the withstand voltage characteristic of the gate of the device.
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over KINOSHITA et al (US 2018/0012960 A1; hereafter KINOSHITA) in view of Zhao (US 2019/0157081 A1; hereafter Zhao) as applied claims above and further in view of IUCOLANO et al (US 2019/0229203 A1; hereafter IUCOLANO).
Regarding claim 16, KINOSHITA in light of Zhao discloses the high electron mobility transistor according to claim 1, But KINOSHITA and Zhao do not disclose explicitly wherein sidewalls of the P-type III-V composition layer are vertical aligned with two sides of the gate electrode.
In a similar field of endeavor, IUCOLANO discloses wherein sidewalls of the P-type III-V composition layer are vertical aligned with two sides of the gate electrode (Fig 2, gate electrode 14 and the doped region 12 vertically aligned with two sides, Para [ 0012-0014]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA and Zhao in light of IUCOLANO teaching “wherein sidewalls of the P-type III-V composition layer are vertical aligned with two sides of the gate electrode (Fig 2, gate electrode 14 and the doped region 12 vertically aligned with two sides, Para [ 0012-0014])” for further advantage such as prevents the increase in the ON state resistance, and reduces concentration in the heterostructure.
Allowable Subject Matter
Claims 11 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 11, The high electron mobility transistor according to claim 10, wherein the spacer layer is disposed on the another carbon containing layer
Regarding claim 18, The method of forming a high electron mobility transistor according to claim 17, wherein the carbon containing layer is formed after forming the P-type III-V composition layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898