DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Pub No. 20200083474), in view of Kwak et al (US Pub No. 20140217397), in view of Park et al (US Pub No. 20200321292), in view of Moon et al (US Pub No.20200295310).
With respect to claim 1, Lee et al discloses a first substrate (100,Fig.5) including: a display area (DA); and a non-display area adjacent to the display area (PA); a second substrate (300) disposed on the first substrate; and a sealing member (400) disposed in a sealing area of the non-display area (400E-100IE) to bond the first substrate to the second substrate (Fig.5), wherein the first substrate comprises: a first base portion (101-120); a buffer layer (109); a semiconductor layer (134) overlapping the lower light blocking layer, on the buffer layer (it is not directly on, because the claim does not require it, Fig.5); a gate insulating layer (103) on the semiconductor layer; and, and a gate electrode (140) overlapping the semiconductor layer (Fig.5), on the gate insulating layer (Fig.5), and the sealing member (400) on the periphery area (Fig.5).
However, Lee et al does not explicitly disclose a lower light blocking layer; a semiconductor layer overlapping the lower light blocking layer; a first conductive layer comprising a first signal line, on the first base portion; a buffer layer on the first conductive layer; a second conductive layer comprising a second signal line and a third signal line electrically connected to the first signal line, wherein the gate electrode, the first signal line and the third signal line comprises a same material. On the other hand, Kwak et al discloses that on the non-display area (NA,Fig.2A), a first conductive layer (220A) comprising a first signal line (221A all the way left,Fig.2A), on the first base portion (210A); a buffer layer on and covering the first conductive layer (262A, this is equivalent to the base the buffer layer in the primary reference) ; a second conductive layer comprising a second signal line (221A in the middle) and a third signal line electrically (221A all the way to the right) connected to the first signal line (Fig.2A); and in plan view, the first signal line is disposed between the second signal line and the third signal line (Fig.2A), wherein the gate electrode (Para 110), the first signal line (Para 96) and the third signal line (Para 96) comprises a same material (such as molybdenum).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Lee et al according to the teachings of the Kwak et al such that first and second and third signal lines are formed on the periphery such that in plan view, the first signal line is disposed between the second signal line and the third signal line, and the first signal line overlaps the sealing member, in order to make a wiring portion on the periphery region to power up the device in the display region. Furthermore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Lee et al according to the teachings of the Kwak et al such that first and second and third signal lines and the gate electrode are formed from the same material, in order to increase the speed of the manufacturing by depositing all the material at the same time.
However, the arts cited above do not explicitly disclose a lower light blocking layer; a semiconductor layer overlapping the lower light blocking layer. On the other hand, Park et al discloses a lower light blocking layer (LB,Fig.7); a semiconductor layer (AP.Fig.7) overlapping the lower light blocking layer (Fig.7). It would have been obvious to one of ordinary skill in the art at the time of the filing of the inventio to modify the arts cited above according to the teachings of the Park et al such that light blocking layer is formed under the channel layer, in order to minimize the outside noise, thereby Improving the picture quality.
However, the arts cited above do not explicitly disclose the second signal line overlaps the sealing member in thickness direction of the substrate; wherein a material of the gate electrode is the same as a material of the first signal line and a material of the third signal line and the second signal line and the lower light blocking layer comprises a different material from the gate electrode, the first signal line and the third signal line, and wherein a material of the second signal line is the same as material of the lower light blocking layer. However, Moon et al discloses the second signal line (W2,Fig.4) overlaps the sealing member (610) in thickness direction of the substrate (y direction of the substrate); wherein a material of the gate electrode (para 125,G1)is the same as a material of the first signal line (W1 to the right) and a material of the third signal line (W1 to the left, Para 125) and the second signal line (W2) and the lower light blocking layer (BSM), and wherein a material of the second signal line is the same as material of the lower light blocking layer (Para 126). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Moon et al such that light blocking material and the second signal line have the same material and the first and third electrodes have the same material as the gate electrode, in order to increase the yield of the device. However, the arts cited above do not explicitly disclose the light blocking layer and the gate electrode have different material. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that gate electrodes are made from copper and BSM made from molybdenum in order to cut the cost and improve the device reliability or as a design choice.
With respect to claim 2, Kwak et al discloses wherein the second conductive layer further comprises a first pad (222A) electrically connected to an outer end of the second signal line (Fig.2A).
With respect to claim 3, Lee et al discloses wherein the first substrate further comprises a passivation layer (109) on the second conductive layer (82).
With respect to claim 4, Kwak et al discloses wherein the first substrate further comprises a via layer (264A) on the passivation layer.
With respect to claim 5, Kwak et al discloses wherein the via layer includes an organic insulating material (Para 114).
With respect to claim 6, Kwak et al in view of Lee et al discloses wherein the via layer does not overlap the sealing member (Para 57, Fig.5)
With respect to claim 7, Lee et al in view of Kwak et al discloses wherein the sealing member (400) is in direct contact with the passivation layer (109) .
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Pub No. 20200083474), in view of Kwak et al (US Pub No. 20140217397), in view of Park et al (US Pub No. 20200321292), in view of Won et al 9US Pub No. 20200245071), in view of Moon et al (US Pub No.20200295310).
With respect to claim 16, Lee et al discloses, wherein the second substrate (300); however, the arts cited above do not explicitly disclose comprises: a second base portion facing the first base portion; a color filter layer on the second base portion; and a light conversion pattern layer on the color filter layer. On the other hand, Won et al discloses a second base portion (112,CFL,QDL,FL,Fig.7) facing the first base portion (111,TFL,EML); a color filter layer (CFL) on the second base portion; and a light conversion pattern layer(QDL) on the color filter layer. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Won et al such that that color filter and light conversion layers are formed on the second substrate, in order to separate the lights from each other as a design choice.
With respect to claim 17, Won et al discloses further comprising a filler (FL) between the first substrate (111) and the second substrate (112).
Allowable Subject Matter
Claims 8-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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