DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1, 8, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al. (10263060).
With regard to claim 1, Noh et al. disclose a display apparatus (for example, see fig. 2) comprising:
a substrate (110);
a first silicon-based transistor (a transistor including an active layer 131) disposed over the substrate (110) and including a first semiconductor layer (131) and a first gate electrode (132) which overlap each other, the first semiconductor layer (131) including: a silicon-based semiconductor material (for example, column 8, lines 13, 14);
at least one insulating layer (114; or 114, 115, 116) on the first gate electrode (132);
a first oxide-based transistor (a transistor including an active layer 141) including a semiconductor layer (141) on the at least one insulating layer (114), the semiconductor layer (141) including: an oxide-based semiconductor (for example. Column 9, lines 39, 40);
a first connection electrode (referred to as “A” by examiner’s annotation shown in fig. 2 below; wherein the first connection electrode A is forming in via hole to secure the electrical connection between the transistors) electrically connecting the first semiconductor layer (131) of the first silicon-based transistor to the semiconductor layer (141) of the first oxide-based transistor; and
a bottom metal layer (120) disposed between the substrate (110) and the first silicon-based transistor (the transistor including the active layer 131) and overlapping the first semiconductor layer (131) of the first silicon-based transistor,
wherein a portion (referred to as “120A” by examiner’s annotation shown in fig. 2 below) of the bottom metal layer (120) overlaps a contact interface (referred to as “131A” by examiner’s annotation shown in fig. 2 below) between the first connection electrode (A) and the semiconductor layer (131) of the first oxide-based transistor.
wherein the bottom metal layer (120) overlaps an end (referred to as “A1” by examiner’s annotation shown in fig. 2 below) of a contact interface between the first connection electrode (A) contacting the first semiconductor layer (131) of the first silicon-based transistor (the transistor including the active layer 131) and an opposite end (referred to as “A2” by examiner’s annotation shown in fig. 2 below) of the first connection electrode (A) indirectly contacting the semiconductor layer (141) of the first oxide-based transistor (the transistor including an active layer 141).
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With regard to claim 8, Noh et al. disclose a storage capacitor including a first capacitor electrode (133) and a second capacitor electrode (151) which overlap each other on the first silicon-based transistor (the transistor having the active layer 131), wherein the at least one insulating layer (114, 115, 116) includes: a first inter-insulating layer (115) between the first capacitor electrode (133) and the second capacitor electrode (151); and a second inter-insulating layer (116) over the first inter-insulating layer (115), and wherein the second capacitor electrode (151) is disposed under the second inter-insulating layer (116), and the semiconductor layer (141) of the first oxide-based transistor is disposed on (on the bottom surface) the second inter-insulating layer (116).
With regard to claim 9, Noh et al. disclose the second capacitor electrode (151) is adjacent to the first connection electrode (A) and does not overlap the first connection electrode (A) in a plan view (a cross-sectional view including a plan view).
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (10263060) in view of Yoon et al. (9660090).
With regard to claim 4, Noh et al. do not clearly disclose the bottom metal layer has a voltage level of a constant voltage.
However, Yoon et al. disclose the bottom metal layer (103) has a voltage level of a constant voltage. (for example, column 8, lines 21 – 23, fig. 3).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Noh et al.’s device to have the bottom metal layer has a voltage level of a constant voltage as taught by Yoon et al. in order to secure the high quantity efficiency of electric charges in the light-shielding pattern for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
5. Claims 5, 6, are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (10263060) in view of Wang et al. (20250017096).
With regard to claims 5, 6, Noh et al. disclose a plurality of inorganic insulating layers (111, 112) between the substrate and the first connection electrode (A), wherein the plurality of inorganic insulating layers (111, 112) includes the at least one insulating layer, but Noh et al. do not clearly disclose a valley having a first depth is defined in the plurality of inorganic insulating layers in a thickness direction, wherein at least a portion of the valley vale is filled with an organic insulating material.
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However, Wang et al. disclose a valley (referred to as “107A” by examiner’s annotation shown in fig. 2 below) having a first depth is defined in the plurality of inorganic insulating layers (portions of layer 106 functioning as inorganic insulating layers) in a thickness direction, wherein at least a portion of the valley (107A) is filled with an organic insulating material (109).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Noh et al.’s device to have a valley having a first depth is defined in the plurality of inorganic insulating layers in a thickness direction, wherein at least a portion of the valley is filled with an organic insulating material as taught by Wang et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (10263060) in view of Sharma et al. (12183668).
With regard to claim 10, Noh et al. do not clearly disclose a distance between one lateral side of the second capacitor electrode and one lateral side of the first connection electrode adjacent to each other is equal to or greater than about 0.5 micrometer in the plan view.
However, Sharma et al. disclose a distance between one lateral side of the second capacitor electrode and one lateral side of the first connection electrode adjacent to each other is 10 micrometer in the plan view (a cross-sectional view including the plan view). (for example, the capacitor is laterally spaced apart from the TSV structure by a distance of 10 microns wherein TSV structure including electrode material forming the TSV and functioning as the first connection electrode; and the capacitor inherently including the second capacitor electrode; for example, see claim 24).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Noh et al.’s device to have a distance between one lateral side of the second capacitor electrode and one lateral side of the first connection electrode adjacent to each other is or greater than about 0.5 micrometer in the plan view as taught by Sharma et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
1. Claim 2 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the first semiconductor layer includes a channel region which is bent, and a drain region arranged on one side of the channel region and connected to the first connection electrode, wherein the portion of the bottom metal layer overlaps the channel region of the first semiconductor layer which is bent, and the drain region as recited in claim 2.
9. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a second silicon-based transistor including a second semiconductor layer and a second gate electrode, wherein the second semiconductor layer includes a silicon-based semiconductor, and the second gate electrode overlaps the second semiconductor layer; and a first lower scan line electrically connected to the second gate electrode of the second silicon-based transistor, wherein the first lower scan line has an isolated shape in a plan view and is electrically connected to a first upper scan line disposed on the first lower scan line and crossing the valley in the plan view as recited in claim 7.
1. Claims 11, 13 - 20 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the first semiconductor layer of the first silicon-based semiconductor pattern includes a channel region which is bent and an impurity region, the impurity region being arranged on one side of the channel region, and being connected to the first connection electrode, wherein the portion of the bottom metal layer overlaps the channel region of the first semiconductor layer which is bent and the impurity region as recited in claim 11.
Response to Amendment
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812