Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant’s response of 12/17/2025 has been entered in the record and considered. Applicant’s arguments with respect to the rejection claims (1-2) under 35 USC 102(a)(1) have been considered but they are not persuasive for the reasons as discussed below. Claims 1-2 are rejected. Claims 3-12 are allowed. Claims 13-23 are cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2018/0033804 to Bae et al. (Bae).
Regarding independent claim 1, Bae discloses a display apparatus (Fig. 6) comprising:
a substrate (Fig. 6: 100);
an oxide semiconductor layer (Fig. 6: 130) above the substrate, and comprising a first channel area (¶0050 and see Examiner’s Mark-up below) of a first transistor (first transistor is formed where 110 is formed), and a second channel area (¶0050 and see Examiner’s Mark-up below) of a second transistor (second transistor is formed where 111 is formed) spaced from the first channel area;
a first conductive layer (Fig. 6: 110 and ¶0048) between the substrate and the oxide semiconductor layer, and comprising a first gate electrode (see Examiner’s Mark-up below for first gate electrode) connected to the second transistor and overlapping the first channel area (gate 110 is capacitively couple to the channel 130 which is then connected to the second transistor); and
a second conductive layer (Fig. 6: 141 and 160 and ¶0055, UBR 141 and 160 are currently considered to be a second conductive layer because both 141 and 160 each has a single layer and they have the same material) above the oxide semiconductor layer, and comprising a shielding layer (141, see Examiner’s Mark-up below for shielding layer, it is noted that it is well known in the art that source electrode function as a shielding layer) overlapping the first channel area, and a second gate electrode (160, see Examiner’s Mark-up below for second gate electrode) overlapping the second channel area.
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Regarding independent claim 1, Bae discloses a display apparatus (Fig. 12) comprising:
a substrate (see Examiner’s Mark-up below, item 1120);
an oxide semiconductor layer (Fig. 6: 130) above the substrate, and comprising a first channel area (¶0050 and see Examiner’s Mark-up below) of a first transistor (first transistor is formed where 110 is formed), and a second channel area (¶0050 and see Examiner’s Mark-up below) of a second transistor (second transistor is formed where 111 is formed) spaced from the first channel area;
a first conductive layer (Fig. 6: 160 and ¶0050) between the substrate and the oxide semiconductor layer, and comprising a first gate electrode (see Examiner’s Mark-up below for first gate electrode: 160) connected to the second transistor overlapping the first channel area (gate 160 is connected to the 150 which is then connected to the second transistor; it is noted that anything in a circuit is connected one with another directly or indirectly); and
a second conductive layer (Fig. 6: 110 and 111 and ¶0074) above the oxide semiconductor layer (see Examiner’s Mark-up below), and comprising a shielding layer (111, see Examiner’s Mark-up below for shielding layer) overlapping the first channel area, and a second gate electrode (110, see Examiner’s Mark-up below for second gate electrode) overlapping the second channel area.
It is noted that the second substrate 1120 showing in Fig. 12 is placed above the structure of Fig. 6. The whole structure when comes together and flip upside down will meet the claim limitations.
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Regarding claim 2, Bae discloses wherein the shielding layer (111) and the second gate electrode (110) comprise a same material and have a same layer structure (¶0048 explicitly discloses that the shielding layer (111) and the second gate electrode (110) comprise a same material and have a same layer structure).
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2021/0181554 to Hong et al. (Hong).
Regarding independent claim 1, Hong discloses a display apparatus (Fig. 4) comprising:
a substrate (Fig. 4: 210);
an oxide semiconductor layer (Fig. 4: A1 and A2; ¶0088) above the substrate, and comprising a first channel area (Fig. 4: 31) of a first transistor (TR1), and a second channel area Fig. 4: 33) of a second transistor (TR2) spaced from the first channel area;
a first conductive layer (Fig. 4: LS1) between the substrate (210) and the oxide semiconductor layer (A1 and A2), and comprising a first gate electrode (Fig. 4: LS1: it is noted that it is well known in the art that a light shielding layer LS1 function as a gate electrode) connected (it is noted that anything in a circuit is connected one with another directly or indirectly; in Fig. 4) to the second transistor (TR2) overlapping the first channel area (31); and
a second conductive layer (Fig. 4: G1 and G2) above the oxide semiconductor layer, and comprising a shielding layer (it is noted that it is well known in the art that gate electrode function as a shielding layer) overlapping the first channel area, and a second gate electrode (G2) overlapping the second channel area.
Allowable Subject Matter
Claims 3-12 are allowed.
The following is an examiner’s statement of reasons for allowance:
The examiner’s reasons for allowing claims 3-12 are of record in the September 26, 2025 Office action.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
Applicants argued “Bae does not appear to disclose that the alleged first gate electrode 110 is "connected to [a] second transistor."
Applicants also argued that “Hong does not appear to disclose that the alleged first gate electrode LS1 is "connected to the second transistor"(e.g., to transistor TR2).
However, in response, the Examiner respectfully disagrees.
Figure. 6 of Bae shows that the gate 110 is capacitively couple to the channel 130 which is then connected to the second transistor.
Figure. 5 of Hong shows that the gate LS1 is connected to 220 which is then connected to the second transistor (TR2).
During examination, claim terms are given their broadest reasonable interpretation (BRI) consistent with the specification and as understood by one of ordinary skill in the art. See MPEP § 2111. The claim does not expressly limit the phrase “connected to” to a direct ohmic or physical contact, nor does the specification provide a special definition or disclaimer restricting the scope of “connected.” Therefore, the Examiner interprets “connected to” broadly to encompass both direct and indirect electrical coupling, including capacitive coupling or other forms of electrical communication between circuit elements.
The applied reference teaches a structure in which the first gate electrode is electrically associated with circuitry of a second transistor through an intervening dielectric or conductive structure, such that electrical influence is imparted between the elements. One of ordinary skill in the art would recognize that such an arrangement constitutes an electrical connection or coupling, even if the connection is indirect or mediated through capacitive effects rather than a direct conductive path.
Accordingly, under the broadest reasonable interpretation standard, the claimed limitation of the first gate electrode being “connected to” the second transistor reads on the disclosure of the applied reference because the reference teaches at least an indirect electrical connection/coupling between these elements. The claim language does not require a direct wire, metal line, or continuous conductive path, and no such restriction can be imported from the specification into the claims. See MPEP § 2111.01.
Therefore, Applicant’s argument that the reference fails to disclose the claimed “connected to” relationship is not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
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