DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the RCE filed 6/22/2026 in which claim 26 was added.
Claims 1, 2, 6, 7, 10-20, and 23-26 are pending and presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 6, and 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites in lines 8-9 that "the silicon dioxide of the first gate dielectric layer [has] a higher density than the silicon dioxide of the second gate dielectric layer" and in lines 15-16 that "the first gate dielectric layer is disposed between the second gate dielectric layer and the gate conductor layer". The amendment filed 3/19/2026 introduced by new claim 21 (which was later incorporated into independent claim 1) that the first gate dielectric has a higher density than the second gate dielectric when the first gate dielectric is between the second gate dielectric and the gate conductor. However, the disclosure as originally filed only provides that the first gate dielectric 32 has a higher density than the second gate dielectric 34 when the first gate dielectric 32 is between the semiconductor substrate and the second gate dielectric 34, see Figs. 4-7 and [0033]. Therefore, the combination of limitations of the first gate dielectric having a higher density than the second gate dielectric when the first gate dielectric is between the second gate dielectric and the gate conductor is new matter as it was not described in the specification as filed. Claims 2, 6, and 7 inherit the deficiencies of claim 1. Appropriate correction is required.
Claims 23-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 23 recites in lines 21-22 that "the silicon dioxide of the first gate dielectric layer has a higher density than the silicon dioxide of the second gate dielectric layer" and in lines 16-17 that "the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer". The amendment filed 3/19/2026 introduced by new claim 21 (which was later incorporated into independent claim 23) that the first gate dielectric has a higher density than the second gate dielectric when the first gate dielectric is between the second gate dielectric and the gate conductor. However, the disclosure as originally filed only provides that the first gate dielectric 32 has a higher density than the second gate dielectric 34 when the first gate dielectric 32 is between the semiconductor substrate and the second gate dielectric 34, see Figs. 4-7 and [0033]. Therefore, the combination of limitations of the first gate dielectric having a higher density than the second gate dielectric when the first gate dielectric is between the second gate dielectric and the gate conductor is new matter as it was not described in the specification as filed. Claims 24 and 25 inherit the deficiencies of claim 23. Appropriate correction is required.
Important to Note
Examiner notes that the reference Sugahara (JP 2018200919) provided in the IDS filed by applicant on 6/22/2026 teaches in Fig. 1 and [0028] of the attached machine translation where the first gate dielectric 61 comprises silicon dioxide (silica glass comprises silicon dioxide) and can have a density higher than that of second gate dielectric 62, which comprises silicon dioxide, when the first gate dielectric is between the substrate and the second gate dielectric 62.
Allowable Subject Matter
Claims 10-20 and 26 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Cai (US 2020/0343370 and Cai hereinafter), discloses a method of forming a structure for a field-effect transistor (Figs. 1-2J; 100; [0011]), the method comprising: forming a doped region (Fig. 1; 109; [0013]) in a semiconductor substrate (comprising 120, 101, 110, 109, and 108; [0011]-[0013]); forming a trench (Fig. 1; 103; [0012]) including a plurality of sidewalls (left and right sidewall of 103) extending from a top surface (top of 109) of the semiconductor substrate (comprising 120, 101, 110, 109, and 108) into the semiconductor substrate (comprising 120, 101, 110, 109, and 108), wherein the semiconductor substrate (comprising 120, 101, 110, 109, and 108) comprises a wide bandgap semiconductor material (substrate can comprise a material such as SiC; [0008]); forming a first gate dielectric layer (Fig. 1; inner half of 115; [0012]) disposed on the sidewalls of the trench (103); forming a second gate dielectric layer (Fig. 1; claim doesn’t establish a material difference between the first and second gate dielectric layers so Examiner interprets them to be the same material, such as the material of 115, and the second gate dielectric layer is the outer half of 115; [0012]) disposed on the sidewalls of the trench (103); forming a gate conductor layer (Fig. 1; 105; [0012]) inside the trench (103); forming a dielectric layer (Fig. 1; 111; [0013]) including a first portion (111 that is directly over 105) on the gate conductor layer (105) and a second portion (111 that is directly over the top surface of 109) on the top surface (top of 109) of the semiconductor substrate (comprising 120, 101, 110, 109, and 108); and forming an electrode (Fig. 1; 122 is the source electrode; [0014]) coupled (through 112; [0014]) to the doped region (109), wherein the first gate dielectric layer (inner half of 115) is disposed between the gate conductor layer (105) and the second gate dielectric layer (outer half of 115), the first portion (111 that is directly over 105) of the dielectric layer (111) is thicker (111 that is directly over 105 extends from the bottom surface of 122 to the top of 105 that is recessed relative to the top of 109 which is thicker than 111 that is directly over the top of 109 that extends from the bottom surface of 122 to the top of 109) than the second portion (111 that is directly over the top surface of 109) of the dielectric layer (111), and the first portion (111 that is directly over 105) of the dielectric layer (111) is disposed between the gate conductor layer (105) and the electrode (122). Cai fails to expressly disclose wherein the gate conductor layer comprises silicon, and forming the dielectric layer including the first portion on the gate conductor layer and the second portion on the top surface of the semiconductor substrate comprises: oxidizing the silicon of the gate conductor layer and the wide bandgap semiconductor material of the semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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