DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Applicant’s amendments of claim 1 and cancellation of claim 2 in the reply filed on 12 March 2026 are acknowledged. Claims 18-26 were previously withdrawn as pertaining to an unelected invention. Claims 5 and 11 were previously withdrawn as pertaining to unelected species.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-8, 10, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rajashekhar et al (US 20210202703 A1, hereinafter “Rajashekhar”).
Regarding claim 1 – Rajashekhar discloses a NOR-type memory device ([0046], Fig. 15A), comprising: a plurality of device layers (considered as 24, 31, and 26 together [0052]) stacked on a substrate (9 [0052]), wherein each of the plurality of device layers comprises a first source/drain region (24 [0052]) and a second source/drain region (26 [0052]) at opposite ends of the device layer in a vertical direction (Fig. 15B), and a channel region (60 [0123]) between the first source/drain region and the second source/drain region in the vertical direction (Fig. 15B); and a gate stack (56 [0088] and 52, 54, and 66 [0121]) that extends vertically with respect to the substrate to pass through each of the plurality of device layers (Fig. 15A), wherein the gate stack comprises a gate conductor layer (66 [0121]) and a memory functional layer (52 and 54 [0121]) disposed between the gate conductor layer and the device layer (Fig. 15B), and a memory cell (300 [0094]) is defined at an intersection of the gate stack and the device layer; wherein the memory functional layer comprises a first layer (54 [0121]), and the first layer has a plurality of portions that correspond to the plurality of device layers respectively and are discontinuous with each other in the vertical direction (Fig. 15B), wherein the plurality of portions of the first layer in the memory functional layer are self-aligned with the first source/drain regions, the second source/drain regions and the channel regions comprised in the plurality of device layers respectively (54 is self-aligned to 24, 60, and 26, Rajashekhar [0145] and Fig. 15B).
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Regarding claim 3 – Rajashekhar further discloses the NOR-type memory device according to claim 1, wherein the memory functional layer further comprises a second layer extending continuously in the vertical direction (52, Rajashekhar [0121] and Fig. 15B).
Regarding claim 4 – Rajashekhar further discloses the NOR-type memory device according to claim 3, wherein the first layer is a conductive layer (54L, Rajashekhar [0089]), and the second layer is an insulating layer (52, Rajashekhar [0092]).
Regarding claim 6 – Rajashekhar further discloses the NOR-type memory device according to claim 1, further comprising: a plurality of isolation layers (34, Rajashekhar [0109]), wherein the plurality of device layers and the plurality of isolation layers are alternately stacked on the substrate (Rajashekhar Fig. 15A), and each of the plurality of device layers is between isolation layers in the vertical direction (Rajashekhar Fig. 15A), wherein each of the plurality of portions of the first layer of the memory functional layer is located between isolation layers in the vertical direction (Rajashekhar Fig. 15A).
Regarding claim 7 – Rajashekhar further discloses the NOR-type memory device according to claim 6, wherein each of the plurality of device layers and the plurality of isolation layers has a sidewall opposite to the gate stack (IS, annotated Rajashekhar Fig. 5A), and wherein the sidewall of the isolation layer is protruded transversely with respect to the sidewall of the device layer towards the gate stack (Protrusion, annotated Rajashekhar Fig. 5A), and each of the plurality of portions of the first layer of the memory functional layer is disposed in a recess (349, Rajashekhar [0072] and Fig. 4) defined by a sidewall of a corresponding device layer (60, Rajashekhar Fig. 15B), the isolation layer above the corresponding device layer, and the isolation layer below the corresponding device layer (recess lateral extent defined by edge of isolation layers 34, Rajashekhar Fig. 4).
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Regarding claim 8 – Rajashekhar further discloses the NOR-type memory device according to claim 6, wherein a hole (49, Rajashekhar [0069]) extending vertically is provided in the plurality of device layers and the plurality of isolation layers (Fig. 4), and the gate stack is formed in the hole (Rajashekhar Fig. 15A), and wherein a portion of the hole (349, Rajashekhar [0072]) corresponding to the device layer is expanded transversely with respect to a portion of the hole corresponding to the isolation layer (Rajashekhar Fig. 4), and each of the plurality of portions of the first layer of the memory functional layer is disposed in a portion of the hole corresponding to a corresponding device layer (54, Rajashekhar Fig. 15A).
Regarding claim 10 – Rajashekhar further discloses the NOR-type memory device according to claim 8, wherein each of the plurality of portions of the first layer of the memory functional layer extends on a sidewall of the corresponding device layer in the hole, without extending to a top surface of the isolation layer below the corresponding device layer in the hole and a bottom surface of the isolation layer above the corresponding device layer in the hole (54 does not extend to 34, Rajashekhar Fig. 15B).
Regarding claim 15 – Rajashekhar further discloses the NOR-type memory device according to claim 1, wherein the device layer comprises: a base layer (36, Fig. 15B); and a semiconductor layer (60, Rajashekhar Fig. 15B) on a sidewall of the base layer facing the gate stack, wherein the semiconductor layer is in form of a nanosheet, and the channel region is substantially formed in the semiconductor layer (Channel formed by 60L, which can be a nanosheet of 1-30 nm thick, Rajashekhar [0083]).
Regarding claim 17 – Rajashekhar further discloses the NOR-type memory device according to claim 1, wherein the memory functional layer comprises a floating gate layer or a charge trapping layer as the first layer (Rajashekhar [0121]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar et al (US 20210202703 A1, hereinafter “Rajashekhar”), in view of Hshieh et al (US 20020195655 A1, hereinafter “Hshieh”).
Regarding claim 14 – Rajashekhar discloses all the limitations of claim 6.
Rajashekhar fails to expressly disclose a doping concentration in the first source/drain region decreases towards the channel region in the vertical direction, and a doping concentration in the second source/drain region decreases towards the channel region in the vertical direction.
However, Hshieh discloses a doping concentration in a source region decreases towards the channel region in the vertical direction (Hshieh [0052] and annotated Fig. 11B). Since Rajashekhar teaches the drain and source regions are symmetrical (Rajashekhar [0055]), the same can be applied to a drain doping concentration towards the channel of the NOR-type memory device.
Hshieh discloses a semiconductor device that comprises a vertical source and a channel region, similar to the stacked 3D memory device of Rajashekhar. Hshieh teaches the source has a decreasing concentration profile into an epitaxial channel layer, allowing the advantage of diffusion to the desired channel length (Hshieh [0011] and [0052]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hshieh and Rajashekhar to incorporate source and drain doping concentrations that decrease towards the channel region for the advantage of setting the desired channel length.
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Claims 9, 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar et al (US 20210202703 A1, hereinafter “Rajashekhar”), in view of Kim et al (US 20100155810, hereinafter “Kim”).
Regarding claim 9 – Rajashekhar discloses all the limitations of claim 8.
Rajashekhar fails to disclose each of the plurality of portions of the first layer of the memory functional layer extends on a sidewall of the corresponding device layer in the hole, on a top surface of the isolation layer below the corresponding device layer in the hole, and on a bottom surface of the isolation layer above the corresponding device layer in the hole.
However, Kim discloses each of the plurality of portions (Kim Fig. 2A) of the first layer of the memory functional layer (131, Kim [0043] and Fig. 2D) extends on a sidewall (127, Kim [0043] and Fig. 2D) of the corresponding device layer in the hole, on a top surface of the isolation layer below the corresponding device layer in the hole (Kim Fig. 2D), and on a bottom surface of the isolation layer above the corresponding device layer in the hole (Kim Fig. 2D).
Kim is analogous to Rajashekhar in the area of 3D nonvolatile memory. Kim teaches the first layer of the memory functional layer is limited to following the contour of the vertical sidewall of active layers and the horizontal surfaces of the isolation protrusions for separation of memory segments, to prevent stored charges from moving upwardly or downwardly, thus improving reliability of the nonvolatile memory device (Kim [0127]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rajashekhar and Kim to limit placement of the first layer of the memory functional layer in a recess following the contour of the sidewall of the active layer and horizontal surfaces of the isolation protrusions for the well-known benefit of improved reliability of the nonvolatile memory device.
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Regarding claim 27 – Rajashekhar discloses all the limitations of claim 1.
Rajashekhar fails to disclose an electronic apparatus comprising the NOR-type memory device according to claim 1.
However, Kim discloses an electronic apparatus (Kim [0130]) comprising the NOR-type memory device according to claim 1 (Kim Fig. 9).
Combining Rajashekhar with Kim's teaching of a memory device in an electronic apparatus is a case of prima facie obviousness, as they are used for the same function. See MPEP 2144.06(I). Furthermore, it is common industry practice to use memory devices in a wide variety of electronic apparatus.
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Regarding claim 28 – Rajashekhar modified Kim discloses all the limitations of claim 27.
The combination of Rajashekhar and Kim further discloses the electronic apparatus comprises a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply (a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a digital music player, a memory card or all the electronic devices capable of transmitting data and/or receiving data in a wireless environment, Kim [0133]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar et al (US 20210202703 A1, hereinafter “Rajashekhar”), in view of Or-Bach et al (US 20210233901 A1, hereinafter “Or-Bach”).
Regarding claim 16 – Rajashekhar discloses all the limitations of claim 1.
Rajashekhar fails to disclose the device layer comprises a single crystal semiconductor material.
However, Or-Bach discloses the device layer comprises a single crystal semiconductor material (by epitaxy, Or-Bach [0104]).
Or-Bach presents the construction of a NOR-type memory device, similarly to Rajashekhar. Or-Bach teaches the use of epitaxial layers for singe crystal construction, for the benefit of chip stacking by layer transfer (Or-Bach [0068-0069]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rajashekhar and Or-Bach to use single crystal material for the benefit of chip stacking techniques.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar et al (US 20210202703 A1, hereinafter “Rajashekhar”), in view of Or-Bach et al (US 20210233901 A1, hereinafter “Or-Bach”), and further in view of Chaudhry et al (US 20030064567 A1, hereinafter “Chaudhry”).
Regarding claim 12 – Rajashekhar discloses all the limitations of claim 6.
Rajashekhar fails to disclose the isolation layer contains a dopant identical to a dopant in the first source/drain region and a dopant in the second source/drain region.
However, Or-Bach discloses a sacrificial layer between active layers can be replaced by isolation material (Or-Bach [0087]), and the isolation material can be a form of silicon oxide (Or-Bach [0077]). Chaudhry teaches further that such an oxide with phosphorous or boron doping can be used as a dopant source for adjacent silicon layers (Chaudhry [0023] and [0035]).
Or-Bach is analogous to Rajashekhar because they both describe 3D NOR-type memory devices incorporating active layers parallel to a substrate. Or-Bach teaches replaceable layers for the benefit of keeping source and drain layers undoped during the deposition process to avoid autodoping (Or-Bach [0174]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rajashekhar and Or-Bach by using a replaceable layer to dope the source and drain after deposition to avoid autodoping.
Chaudhry is analogous to Rajashekhar because a field effect device is described involving doped silicon regions. Chaudhry teaches using doped glass to diffuse dopant into an adjacent silicon region for the advantage of self-aligned source/drain regions (Chaudhry [0035]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Rajashekhar, Or-Bach, and Chaudhry to implement dopant diffusion into silicon from doped glass for the advantage of self-aligned source/drain regions.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar et al (US 20210202703 A1, hereinafter “Rajashekhar”), in view of Or-Bach et al (US 20210233901 A1, hereinafter “Or-Bach”), and further in view of Chaudhry et al (US 20030064567 A1, hereinafter “Chaudhry”), and further in view of MPEP 2112(III).
Regarding claim 13 – Rajashekhar modified by Or-Bach and Chaudhry discloses all the limitations of claim 12.
The combination of Rajashekhar, Or-Bach, and Chaudhry fails to disclose a concentration of the dopant in the isolation layer is equal to or higher than a doping concentration in the first source/drain region and a doping concentration in the second source/drain region.
However, it is an inherent consequence of diffusion that the concentration of the dopant in the isolation layer is equal to or higher than a doping concentration in the first source/drain region and a doping concentration in the second source/drain region. The diffusion source determines the maximum concentration and gradient. Therefore, the highest concentration possible in the source/drain region is that of the dopant source, and this property is inherently present in the prior art. See MPEP 2112(III).
Response to Arguments
The applicant states “Rajashekhar’s memory material layer 54 is only aligned with the channel 60 and not aligned with the source/drain layers 24/26”.
However, the examiner respectfully points out that the first layer 54 of Rajashekhar’s memory functional layer is self-aligned to an array of layers, including 22, 60, and 24, and is therefore self-aligned to all three, as explained in Rajashekar [0145] and shown in Fig. 15B.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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