DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 5/25/2026.
Claims 13-18, 21-29 and 31-35 are pending. Claims 1-12, 19-20 and 30 are cancelled. Claims 13 and 32 are currently amended. Claims 13, 21 and 32 are independent.
Response to Arguments
Applicants' arguments and amendments, filed 5/25/2026, with respect to independent claim 13, although substantive and pertinent to expediting the prosecution of the current application, are considered not persuasive, respectfully, for the reasons that follow.
Regarding independent claim 13, the claim has been amended to recite “forming a plurality of solder bumps on a bottom surface of the RDL structure”, which applicants contend is not disclosed or taught by the prior art, including Lee and/or Wu (Remarks 8-10).
Applicants’ contentions are fully considered, however are not found persuasive, since as noted below in the rejections of independent claim 13 Figure 6 of Lee discloses forming a plurality of solder bumps 420 (“solder balls”- ¶0135) on a bottom surface of the RDL structure 120, since solder bumps 420 are formed indirectly on the bottom surface of RDL structure 120 and Figures 12-14 of Wu disclose forming a plurality of solder bumps 66 (“connectors… solder balls”- ¶0046) on a bottom surface of the RDL structure 34/40, since solder bumps 66 are formed indirectly on the bottom surface of RDL structure 34/40.
Thus, for the aforementioned reasons the rejection is deemed proper.
Applicants' arguments and amendments, filed 5/25/2026, with respect to independent claim 32, although substantive and pertinent to expediting the prosecution of the current application, are considered moot and not persuasive, respectfully, in light of new grounds of rejections made using the combined teachings of Lee and Bowers as noted below in the rejection of independent claim 32.
A. Prior-art rejections based at least in part by Lee
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2012/0018871 A1, hereinafter “Lee”).
Regarding independent claim 13, Lee discloses a method of forming a package module, the method comprising:
attaching a plurality of semiconductor dies 200 (“semiconductor chip”- ¶0188) to an interposer 100 (“semiconductor chop”- ¶0189) including a redistribution layer (RDL) structure 120 (“wiring layer”- ¶0057) (see Fig. 13B);
attaching a module stiffener 310 (“supporter”- ¶0190, which prevents warpage and thereby acts as a “module stiffener”- ¶0073) to the interposer 100 adjacent to the plurality of semiconductor dies 200 and over a metal layer 128 (“wiring pattern… formed of metal”- ¶0062; see Fig. 1 for notation) in the RDL structure 120 in a diagonal direction (see Fig. 13C);
forming a molding material layer 330 (“molding member”- ¶0194) on the interposer 100 around the plurality of semiconductor dies 200 and the module stiffener 310 (see Fig. 13D); and
forming a plurality of solder bumps 420 (“solder balls”- ¶0135) on a bottom surface of the RDL structure 120, since solder bumps 420 are formed indirectly on the bottom surface of RDL structure 120 (see Fig. 6).
Regarding claim 16, Lee discloses wherein the attaching of the module stiffener 310 comprises attaching at least one stiffener segment 310 (see Figs. 2A-2F and 13C), and
wherein the forming of the molding material layer 330 comprises forming the molding material layer 330 around the at least one stiffener segment 310 (see Fig. 13D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Bowers (US 2019/0267334 A1).
Regarding independent claim 32, Lee discloses a method of making a package structure, the method comprising:
forming a package module 1000a (“stack package”- ¶0055) including an interposer 100 (“semiconductor chop”- ¶0189) including a redistribution layer (RDL) structure 120 (“wiring layer”- ¶0057), a semiconductor die 200 (“semiconductor chip”- ¶0056) on the interposer 100, a module stiffener 310 (“supporter”- ¶0190, which prevents warpage and thereby acts as a “module stiffener”- ¶0073) on the interposer 100 adjacent to the semiconductor die 200 and over a metal layer 128 (“wiring pattern… formed of metal”- ¶0062; see Fig. 1 for notation) in the RDL structure 120 in a diagonal direction, a molding material layer 330 (“molding member”- ¶0194) on the interposer 100 around the semiconductor die 200 and the module stiffener 310, and a plurality of connection bumps 130 (“connection bumps”- ¶0057) on a bottom surface of the RDL structure 120, since bumps 130 are formed indirectly on the bottom surface of RDL structure 120, wherein the molding material layer 330 comprises an inner molding material layer portion (i.e., the portion of 310 between die 200 and 310) adjacent an inner side of the module stiffener 310 having a width greater than a width of an outer molding material layer portion (i.e., the portion of 310 between 310 and the outer edge of 330) adjacent an outer side of the module stiffener 310 such that the module stiffener 310 is embedded in the molding material layer 330 (see Figs. 1-2A and 13A-13G);
attaching the package module 1000a to a package substrate 400 (“substrate”- ¶0129) (see Fig. 6); and
forming a package underfill layer 450 (“underfill layer”- ¶0136) on the package substrate 400 around the package module 1000a (see Fig. 6).
Lee does not expressly disclose wherein the connection bumps are formed of solder such that they can be interpreted as solder bumps.
Figure 1 of Bowers discloses a semiconductor device comprising connection bumps 23 (“bumps”- ¶0029) which are formed of solder and thus solder bumps (¶0029).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee such that the connection bumps are formed of solder such that they can be interpreted as solder bumps as taught by Bowers for the purpose of utilizing a suitable and well-known bump material for the connection bumps known to those skilled in the art (Bowers ¶0029).
Regarding claim 33, Lee discloses wherein the forming of the package module 1000a comprises:
attaching the semiconductor die 200 to an interposer wafer 110 (“semiconductor layer”- ¶0057) (see Fig. 13B);
attaching the module stiffener 310 to the interposer wafer 110 around the semiconductor die 200 (see Fig. 13C);
forming the molding material layer 330 on the interposer wafer 110 around the semiconductor die 200 and the module stiffener 310 (see Fig. 13D); and
dicing the interposer wafer 110 to form the package module 1000a (see Fig. 13G).
Regarding claim 34, Lee discloses the method further comprising:
attaching a package stiffener 430 (“external molding member”, which protects the device from external heat, moisture, shocks, or pressure and thereby would provide structural/physical support and act as a “package stiffener”- ¶0142) to the package substrate 400 around the package module 1000a (see Fig. 7).
B. Prior-art rejections based at least in part by Lee (alternative embodiment)
Claim Rejections - 35 USC § 102
Claims 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (alternative embodiment).
Regarding independent claim 13, Lee discloses a method of forming a package module, the method comprising:
attaching a plurality of semiconductor dies 200 (“semiconductor chip”, with the embodiment shown in Fig. 5 with multiple chips 200- ¶¶0120, 0188) to an interposer 100 (“semiconductor chop”- ¶0189) including a redistribution layer (RDL) structure 120 (“wiring layer”- ¶0057) (see Figs. 5 and 13B);
attaching a module stiffener 310 (“supporter”- ¶0190, which prevents warpage and thereby acts as a “module stiffener”- ¶0073) to the interposer 100 adjacent to the plurality of semiconductor dies 200 and over a metal layer 128 (“wiring pattern… formed of metal”- ¶0062; see Fig. 1 for notation) in the RDL structure 120 in a diagonal direction (see Figs. 5 and 13C);
forming a molding material layer 330 (“molding member”- ¶0194) on the interposer 100 around the plurality of semiconductor dies 200 and the module stiffener 310 (see Figs. 5 and 13D); and
forming a plurality of solder bumps 420 (“solder balls”- ¶0135) on a bottom surface of the RDL structure 120, since solder bumps 420 are formed indirectly on the bottom surface of RDL structure 120 (see Fig. 6).
Regarding claim 14, Lee discloses wherein the attaching of the module stiffener 310 to the interposer 100 comprises attaching a module stiffener ring 311 (“ring-shaped portion”- ¶0088) to the interposer 100, such that the module stiffener ring 311 laterally surrounds the plurality of semiconductor dies 200 in a top view, and the forming of the plurality of solder bumps 420 comprises forming the plurality of solder bumps 420 outside the module stiffener 310, since bumps 420 extend beyond the perimeter of module stiffener 310 (see Figs. 2A, 5, 6 and 13C).
Regarding claim 15, Lee discloses wherein the forming of the molding material layer 330 comprises forming the molding material layer 330 inside the module stiffener ring 311 and outside the module stiffener ring 311 such that the module stiffener ring 311 is embedded in the molding material layer 330 (see Figs. 2A, 5 and 13D).
C. Prior-art rejections based at least in part by Wu
Claim Rejections - 35 USC § 102
Claims 13 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 2020/0365525 A1, hereinafter “Wu”).
Regarding independent claim 13, Wu discloses a method of forming a package module, the method comprising:
attaching a plurality of semiconductor dies 28, 44 (“dies”- ¶¶0015, 0027) to an interposer 32 (“interposer wafer”- ¶0012) including a redistribution layer (RDL) structure 34/40 (collectively 34 “substrate” and 40 “redistribution structure”- ¶¶0021, 0023) (see Fig. 4);
attaching a module stiffener 54 (“dummy dies”, which prevent warpage and thereby acts as a “module stiffener”- ¶0038) to the interposer 32 adjacent to the plurality of semiconductor dies 28, 44 and over a metal layer (i.e., “metallization patterns”- ¶0023) in the RDL structure 34/40 in a diagonal direction (see Fig. 7);
forming a molding material layer 58 (“encapsulant”- ¶0043) on the interposer 32 around the plurality of semiconductor dies 28, 32 and the module stiffener 54 (see Fig. 8); and
forming a plurality of solder bumps 66 (“connectors… solder balls”- ¶0046) on a bottom surface of the RDL structure 34/40, since solder bumps 66 are formed indirectly on the bottom surface of RDL structure 34/40 (see Figs. 12-14).
Regarding claim 16, Wu discloses wherein the attaching of the module stiffener 54 comprises attaching at least one stiffener segment 54 (i.e., the different segments of 54; see Figs. 6A-7), and
wherein the forming of the molding material layer 58 comprises forming the molding material layer 58 around the at least one stiffener segment 54 (see Fig. 8).
Regarding claim 17, Wu discloses the method further comprising:
forming an adhesive layer 56 (“attaching structures”- ¶0040) on the interposer 32, wherein the interposer 32 further comprises a plurality of dielectric layers (i.e., the dielectric layer of 34 and the “dielectric layers” except the topmost dielectric layer in 40- ¶¶0021, 0023) and the metal layer comprises a plurality of metal layers (i.e., “metallization patterns”- ¶0023) formed within the plurality of dielectric layers, and the attaching of the module stiffener 54 to the interposer 32 comprises affixing the module stiffener 54 to the interposer 32 over the plurality of metal layers in a diagonal direction with the adhesive layer 56 (see Fig. 7).
Regarding claim 18, Wu discloses wherein the interposer 32 further comprises an upper passivation layer (i.e., the topmost dielectric layer in 40- ¶0023) on the plurality of dielectric layers, and the module stiffener 54 is attached to the upper passivation layer (see Fig. 7).
Allowable Subject Matter
Claims 21-29, 31 and 35 are allowed.
Regarding independent claim 21, the claim is allowed, because the claim has been amended to incorporate the allowable subject matter of claim 30 as previously indicated in line number 7 of the office action mailed on 8/5/2025.
Claims 22-29, 31 and 35 are allowed as being dependent on allowed claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/ Primary Examiner, Art Unit 2817
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