Prosecution Insights
Last updated: May 29, 2026
Application No. 18/116,269

PACKAGE STRUCTURE

Final Rejection §103
Filed
Mar 01, 2023
Examiner
ANGUIANO, MICHAEL
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
2 (Final)
39%
Grant Probability
At Risk
3-4
OA Rounds
3m
Est. Remaining
69%
With Interview

Examiner Intelligence

Grants only 39% of cases
39%
Career Allowance Rate
7 granted / 18 resolved
-29.1% vs TC avg
Strong +30% interview lift
Without
With
+29.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
22 currently pending
Career history
73
Total Applications
across all art units

Statute-Specific Performance

§103
92.0%
+52.0% vs TC avg
§102
1.6%
-38.4% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 18 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments RE: the objection to the drawings, the amendments the claims resolve the prior issues of claimed subject matter not being shown in the drawings. Accordingly, the objection to the drawings is withdrawn. RE: the objection to claim 3, Applicant’s amendment resolves the typographical error in this claim, therefore this objection is withdrawn. RE: the rejection of claims 1-13 under 35 USC 112(b), Applicant’s amendments resolve the issues of indefiniteness, accordingly this rejection is withdrawn. RE: the rejection of the claims under 35 USC 103, Applicant’s amendments and arguments have been fully considered. However, further search and consideration prompted the new grounds of rejection presented herein. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-5, 7-8, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN112242363A (“Lai”; previously cited in Office Action dated Nov. 4, 2025) in view of WO2021119930A1 (“Hu”; previously cited in Office Action dated Nov. 4, 2025), further in view of US5847929A (“Bernier”), further in view of WO2010098028A1 (“Sakamoto”). RE: Claim 1, Lai discloses A package structure (2 in FIG. 2 or 2’ in FIG. 2’), comprising: an electronic component (left 21’ in FIG. 2, 2’); a heat dissipating element (23 in FIG. 2 or 23’ in FIG. 2’) disposed over the electronic component; and an adhesive layer (32) disposed between the electronic component, a thermal conductive layer (31) surrounded by the adhesive layer. Lai does not explicitly disclose: the adhesive layer spaced apart from the electronic component; wherein the thermal conductive layer has a first side convex toward the adhesive layer and a second side convex toward the adhesive layer, a curvature of the first side being different from that of the second side of the thermal conductive layer, an inner surface of the adhesive layer being concave toward an outer lateral surface of the adhesive layer. In the same field of endeavor, Hu shows in FIG. 3, the ring shaped adhesive layer 60 is spaced apart from the chip 21. The thermal interface material layer 30 is shown disposed over the chip 21 and extending laterally from the left portion of the adhesive layer 60 to the right portion of the adhesive layer 60. The thermal interface material layer 30 is shown extending beyond the left and right edges of the chip 21. See pg. 20, line 23 to pg. 21 line 10 and pg. 21 lines 21-24, pg. 22, lines 10-17. Further, Lai discloses the thermal conductivity coefficient of the first heat dissipation adhesive material 31 is greater than that of the second heat dissipation adhesive material 32, pg. 13, lines 7-8. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the heat dissipating adhesive 31 extend beyond left, right edges of the left 21’ in FIG. 2 so that the heat dissipating adhesive 32 is spaced apart from the left 21’ as taught by Hu to improve heat dissipation, as the adhesive 31 has a greater thermal conductivity coefficient than the adhesive 32. As a result, the adhesive 32 would be spaced apart from left 21’ from a first space. In the same field of endeavor, Bernier discloses in FIG. 6: wherein a second adhesive layer (322 is flexible epoxy, silicone, see Col. 9, lines 45-65) has a first side convex toward a first adhesive layer (324; left side of 322 convex toward 324; 324 is an epoxy adhesive, silicon adhesive, flexible epoxy, Col. 9, lines 45-65) and a second side convex toward the first adhesive layer (right side of 322 convex toward 324), a curvature of the first side being different from that of the second side of the second adhesive layer (FIG. 6 shows the curvature of the left side 322 is different from that of the right side 322), an inner surface of the first adhesive layer being concave toward an outer lateral surface of the first adhesive layer (FIG. 6 shows an inner surface of the first adhesive layer 324 being concave toward an outer lateral surface of 324). FIG. 6 shows the left and right sides of 322 bulging or protruding outward, with the left side protruding further outward compared to the right side, causing 324 to have concave inner surfaces. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the left and right sides of the thermally conductive layer 31 to bulge outward, causing the adhesive layer 32 to have concave inner surfaces, with the left side protruding further outward as taught by Bernier in order to further improve heat dissipation, by increasing the amount of the thermally conductive layer present. Additionally or alternatively, in the same field of endeavor, Sakamoto discloses in FIG. 1: a curvature of the first side (left side of heat transfer sheet member 13) being different from the curvature of the second side (right side of 13) of the thermal conductive layer. FIG. 1 shows the difference in curvatures of the left and right sides of 13 is due to the angled bottom surface of the heat dissipating element 15 to accommodate differently sized semiconductor elements 11, 12, see pg. 7, lines 10-26. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make modify the orientation of the bottom surface of the heat dissipating element 23 to be angled, thereby causing the curvatures of the left and right sides of 31 to be different as taught by Sakamoto in order to accommodate differently sized electronic components. RE: Claim 2, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 1, wherein the adhesive layer is free from overlapping the electronic component from a top view, and a top surface of the adhesive layer is noncoplanar with a top surface of the electronic component (As modified, 31 would extend beyond left, right edges of left 21’ in FIG. 2 of Lai, and therefore the adhesive layer 32 would be free from overlapping left 21’ from a top view; FIG. 2 Lai shows the top surface of 32 contacts and extends along the bottom surface of the heat dissipating element 23; FIG. 1 Sakamoto shows the top surface of 13 is noncoplanar with the top surface of 11, 12; Accordingly as modified, as the bottom surface of the heat dissipating element 23 is angled and 32 contacts and extends along the bottom surface of 23, the top surface of 32 would be angled and nonconplanar with the top surface of 21’). RE: Claim 3, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 2, wherein the thermal conductive layer overlaps the electronic component (As modified, 31 overlaps left 21’ in FIG. 2 Lai). RE: Claim 4, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 3, wherein the thermal conductive layer exceeds an edge of the electronic component from a top view (As modified, 31 would exceed left, right edges of left 21’ in FIG. 2 of Lai from a top view). RE: Claim 5, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 1, further comprising: an encapsulant (22) encapsulating the electronic component, wherein the electronic component is exposed from a top surface of the encapsulant, and the adhesive layer is disposed over the encapsulant (FIG. 2 shows left 21’ is exposed from a top surface of 22 and 32 is disposed over 22; as modified, left 21’ would still be exposed from a top surface of 22 and 32 would still be disposed over 22). RE: Claim 7, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 1, wherein a top surface of the heat dissipating element is noncoplanar with a top surface of the electronic component (FIG. 6 Bernier shows a top side surface of the heat dissipating element 320 is noncoplanar with a top surface of the electronic component 302 as the top side of the heat dissipating element 320 has fins/protrusions; FIGs. 8-9 also show a fin heat sink embodiment; Bernier discloses Fins 452 may be machined, Col. 10, lines 44-20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the top side of the heat dissipating element 23 to have fins/protrusions as taught by Bernier in order to improve heat dissipation. As a result, a top side surface of the heat dissipating element 23 would be noncoplanar with a top surface of the electronic component 21’). RE: Claim 8, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 1, wherein the adhesive layer has a first vertical thickness at the first side of the thermal conductive layer and a second vertical thickness at the second side of the thermal conductive layer, and the first vertical thickness is different from the second vertical thickness (FIG. 6 shows the left side of the adhesive 324 has different vertical thicknesses, and the right side of the adhesive 324 has different vertical thicknesses since 324 surrounds an epoxy encapsulant labeled as 160 in FIG. 2, 220 in FIG. 3; FIG. 3 shows adhesive 226 surrounding an encapsulant 220; Col. 8, lines 5-10; Col. 8, lines 28-40; It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the heat dissipating adhesive 32 to surround the encapsulant 22 as taught by Bernier in order to further improve heat dissipation, causing the left portion 32 to have a different vertical thickness than a vertical thickness of the right portion 32). RE: Claim 11, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 3, wherein in a top view, the adhesive layer includes a plurality of segments (FIG. 3C in Lai shows segments of 32) defining at least one channel configured to reduce voids between the adhesive layer and the thermal conductive layer (At least one channel is defined by upper, bottom segments of 32 in FIG. 3C; FIG. 3C shows no voids between 31 and 32; if any air voids were present between 31 and 32, air would be able to escape through the channel defined by the segments of 32, reducing voids). RE: Claim 12, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 11, wherein in the top view, one of the plurality of segments of the adhesive layer is in an L shape (FIG. 3C shows each of the segments 32 is an L-shape). RE: Claim 13, Lai in view of Hu, Bernier, Sakamoto discloses The package structure of claim 11, wherein a portion of the thermal conductive layer is located within the at least one channel (FIG. 3C shows 31 is within the channel defined by upper and bottom segments of 32). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Hu, Bernier, Sakamoto as applied to claim 5, further in view of US20070296079A1 (“Huang”). RE: Claim 6, Lai in view of Hu, Bernier, Sakamoto does not explicitly disclose The package structure of claim 5, wherein the adhesive layer includes a first portion overlapping the electronic component along a direction substantially parallel to the top surface of the encapsulant. However, Lai discloses 32 is a heat dissipating adhesive material 32, pg. 13, lines 18-19. In a similar field of endeavor, Huang in FIG. 8 shows that heat dissipating element 75 includes a first portion overlapping the chip 41 (labelled in FIG. 5F) along a horizontal direction substantially parallel to the top surface of the encapsulant 44 (labelled in FIG. 5F), [0049]. FIG. 8 shows the heat dissipating element 75 is embedded in the encapsulant labeled as 44 in FIG. 5F, causing the heat dissipating element 75 to overlap the chip 41 in the horizontal direction. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to embed the heat dissipating adhesive material 32 in the encapsulant 22 as taught by Huang so that 32 includes a first portion overlapping left 21’ along a horizontal direction substantially parallel to the top surface of 22 to improve heat dissipation in the encapsulant 22. Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Hu, Bernier, Sakamoto as applied to claim 5, further in view of US 20240128145 A1 to Lee et al. (hereinafter “Lee”). RE: Claim 9, Lai in view of Hu, Bernier, Sakamoto does not explicitly disclose The package structure of claim 5, wherein the adhesive layer contacts the encapsulant and the heat dissipating element (FIG. 2 in Lai shows 32 contacting 22 and 23; As modified, 32 would still contact 22 and 23). Lai in view of Hu, Bernier, Sakatmoto does not explicitly disclose: the adhesive layer is configured to reduce a warpage of the package structure. However, in the same field of endeavor, Lee discloses the encapsulant 270 is generally formed of an epoxy material (e.g., the CTE of epoxy resin is about 50-80×10.sup.−6/° C.), the CTE of the redistribution substrate 220 is smaller than that of the encapsulant 270. Therefore, a heat dissipation structure with a much smaller CTE value than that of the encapsulant 270, such as silicon (e.g., the CTE of silicon is about 3×10.sup.−6/° C.), is formed in the area designated for the encapsulant 270. The heat dissipation structure is then encapsulated, reducing the difference between the CTE of the encapsulant 270 and the heat dissipation structure 250, and the CTE of the redistribution substrate 220. Accordingly, warpage deformation caused by differences in thermal expansion coefficient is reduced, [0052], [0053]. Lee further discloses The heat dissipation structure 250 containing crystalline silicon serves as a heat sink or radiator that efficiently dissipates the heat generated from the semiconductor chip, [0049]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the coefficient of thermal expansion of the heat sink 23 lower than the coefficient of thermal expansion of the encapsulation layer 22 as taught by Lee to reduce warpage of the package 2 as further taught by Lee. As a result, the heat dissipating adhesive 32 would transfer heat from the encapsulation layer 22 to the heat sink 23 and therefore reduce warpage of the package 2 as the heat sink 23 would change in size at a smaller rate than that of the encapsulation layer 22. RE: Claim 10, Lai in view of Hu, Bernier, Sakamoto, Lee discloses The package structure of claim 9, wherein a coefficient of thermal expansion of the heat dissipating element is less than a coefficient of thermal expansion of the encapsulant (As modified the coefficient of thermal expansion of the heat sink 23 is lower than the coefficient of thermal expansion of the encapsulation layer 22). Claim(s) 14, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Bernier, further in view of US20070228530A1 (“Sato”). RE: Claim 14, Lai discloses A package structure (2 in FIG. 2 or 2’ in FIG. 2’), comprising: an electronic component (left 21’ in FIG. 2, 2’) including a top surface (top surface of 21’) and a lateral surface (left or right surface of 21’) abutting the top surface, the electronic component extending along a first direction (horizontal direction in FIGs. 2, 2’); an encapsulant (22) encapsulating the electronic component and having a first surface (top surface of 22) exposing the top surface of the electronic component (top surface forms an opening exposed the top surface of 21’), a heat dissipating element (23 in FIG. 2 or 23’ in FIG. 2’) disposed over the first surface of the encapsulant; a thermal conductive layer (31); and a block layer (32), wherein the block layer has a first portion (left portion of 32 at left side of 21’ in FIG. 2, 2’) at a first side of electronic component and a second portion (right portion of 32 at right side of 21’) at a second side of the electronic component in a cross-sectional view. Lai does not explicitly disclose: wherein an elevation of a first portion of the first surface of the encapsulant is lower than that of the top surface of the electronic component; the thermal conductive layer is disposed over the first portion of the encapsulant and abutting the lateral surface of the electronic component; the first portion and the second portion of the block layer at least partially overlapping the electronic component in the first direction; a thickness of the first portion being different from a thickness of the second portion in a second direction perpendicular to the first direction. However, Lai discloses the thermal conductivity coefficient of the first heat dissipation adhesive material 31 is greater than that of the second heat dissipation adhesive material 32, pg. 13, lines 7-8. In the same field of endeavor, Bernier discloses in FIG. 3: wherein an elevation of a first portion of the first surface of the encapsulant (left or right portion of 220 in FIG. 3) is lower than that of the top surface of the electronic component (FIG. 3 shows an elevation of left and right portions of epoxy 220 are lower than that of the top surface of chip 202; FIG. 3 shows adhesive 226 surrounding an encapsulant 220; Col. 8, lines 28-40) Bernier further discloses in FIG. 6: an adhesive layer (322) is disposed over the first portion of the encapsulant (FIG. 6 shows adhesive 322 disposed over left, right portions of an epoxy encapsulant labeled as 220 in FIG. 3 as 322 bulges outward; Col. 8, lines 28-40; see Col. 9, lines 45-65); the first portion and the second portion of the block layer at least partially overlapping the electronic component in the first direction (FIG. 6 shows the left and right portions of 324 overlapping the electronic component 302 in the horizontal direction); a thickness of a first portion of the block layer being different from a thickness of a second portion of the block layer in a second direction perpendicular to the first direction (FIG. 6 shows the left portion of the adhesive 324 has different vertical thicknesses, and the right portion of the adhesive 324 has different vertical thicknesses since 324 surrounds an epoxy encapsulant labeled as 160 in FIG. 2, 220 in FIG. 3; Col. 8, lines 5-10; Col. 8, lines 28-40). FIG. 6 shows the left and right sides of 322 bulging or protruding outward, with the left side protruding further outward compared to the right side, causing 324 to have concave inner surfaces. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the encapsulant 22 to have a lower elevational surface than the top surface of 21’, and to modify the heat dissipating adhesives 31, 32 to bulge out with the adhesive 32 surrounding the encapsulant 22 as taught by Bernier in order to further improve heat dissipation, causing the left portion 32 to have a different vertical thickness than a vertical thickness of the right portion 32. In the same field of endeavor, Sato discloses in FIG. 2: a thermal conductive layer (heat conductive material 29 including 32, [0068]) abutting the lateral surface of the electronic component (FIG. 4 shows 29, 32 abutting the lateral surface of chip 25). Sato further discloses conductive bonding material 29 is formed with the first bonding region 31 transferring the heat of the semiconductor chip 25 to the heat spreader 30 and with the second bonding region 32 relaxing the thermal stress generated between the semiconductor chip 25 and the heat spreader 30, [0068]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the heat dissipating adhesive 31 to abut the lateral surface of 21’ as taught by Sato in order to relax thermal stress as further taught by Sato. RE: Claim 16, Lai in view of Bernier, Sato discloses The package structure of claim 14, wherein a top surface of the heat dissipating element is noncoplanar with the top surface of the electronic component (FIG. 6 Bernier shows a top side surface of the heat dissipating element 320 is noncoplanar with a top surface of the electronic component 302 as the top side of the heat dissipating element 320 has fins/protrusions; FIGs. 8-9 also show a fin heat sink embodiment; Bernier discloses Fins 452 may be machined, Col. 10, lines 44-20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the top side of the heat dissipating element 23 to have fins/protrusions as taught by Bernier in order to improve heat dissipation. As a result, a top side surface of the heat dissipating element 23 would be noncoplanar with a top surface of the electronic component 21’). RE: Claim 17, Lai in view of Bernier, Sato discloses The package structure of claim 16, wherein an inner surface of the block layer is concave toward an outer lateral surface of the block layer (FIG. 6 shows an inner surface of the block layer 324 is concave toward an outer lateral surface of the block layer 324; Accordingly as modified, an inner surface of the block layer 32 is concave toward an outer lateral surface of the block layer 32). Claim(s) 15, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Bernier, Sato as applied to claim 14 or 16, further in view of Sakamoto. RE: Claim 15, Lai in view of Bernier, Sato discloses The package structure of claim 14, wherein a top surface of the block layer is noncoplanar with the top surface of the electronic component (FIG. 6 shows that top left, top right surfaces of the block layer 324 are curved and therefore noncoplanar with the top surface of chip 302; Accordingly, as modified, the top left, top right surfaces of 32 would be curved and noncoplanar with the top surface of 21’). Further in the same field of endeavor, Sakamoto discloses in FIG. 1: a top surface of a block layer (13) is noncoplanar with the top surface of the electronic component (top surface of 11, 12, see pg. 7, lines 10-26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make modify the orientation of the bottom surface of the heat dissipating element 23 to be angled as taught by Sakamoto in order to accommodate differently sized electronic components. As the top surface of 32 is in contact with and extends along the bottom surface of 23, the top surface of 32 would also be angled and noncoplanar with the top of 21’. RE: Claim 19, Lai in view of Bernier, Sato disclose The package structure of claim 16, wherein the heat dissipating element has a bottom surface facing the electronic component (FIG. 2 Lai shows 23 having bottom surface facing 21’) Lai in view of Bernier, Sato does not explicitly disclose: the bottom surface of the heat dissipating element is noncoplanar with the top surface of the electronic component. In the same field of endeavor, Sakamoto discloses in FIG. 1: the bottom surface of the heat dissipating element (bottom surface of 15) is noncoplanar with the top surface of the electronic component (top surface of 11, 12, see pg. 7, lines 10-26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make modify the orientation of the bottom surface of the heat dissipating element 23 to be angled as taught by Sakamoto in order to accommodate differently sized electronic components. RE: Claim 20, Lai in view of Bernier, Sato does not explicitly disclose The package structure of claim 14, wherein a lower surface of the heat dissipating element is nonparallel to the top surface of the electronic component. In the same field of endeavor, Sakamoto discloses: wherein a lower surface of the heat dissipating element (bottom surface of 15) is nonparallel to the top surface of the electronic component (top surface of 11, 12, see pg. 7, lines 10-26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make modify the orientation of the bottom surface of the heat dissipating element 23 to be angled as taught by Sakamoto in order to accommodate differently sized electronic components. Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Hu, further in view of Sato, further in view of Bernier. RE: Claim 21, Lai discloses A package structure (2 in FIG. 2 or 2’ in FIG. 2’), comprising: an electronic component (left 21’ in FIG. 2, 2’) extending along a first direction (horizontal direction); a thermal conductive layer (31) disposed over the electronic component; a heat dissipating element (23 in FIG. 2 or 23’ in FIG. 2’) disposed over the thermal conductive layer; an adhesive layer (32) disposed between the electronic component and the heat dissipating element; and an encapsulant (22) encapsulating the electronic component. Lai does not explicitly disclose: the adhesive layer spaced apart from the electronic component by a space; wherein the thermal conductive layer has a portion in contact with the encapsulant and overlapping the electronic component in the first direction, and the adhesive layer has a portion overlapping the electronic component in the first direction. In the same field of endeavor, Hu shows in FIG. 3: wherein the thermal conductive layer (30) has a portion (left, right portions of 30) in contact with the encapsulant (23). Hu shows in FIG. 3, the ring shaped adhesive layer 60 is spaced apart from the chip 21. The thermal interface material layer 30 is shown disposed over the chip 21 and extending laterally from the left portion of the adhesive layer 60 to the right portion of the adhesive layer 60. The thermal interface material layer 30 is shown extending beyond the left and right edges of the chip 21. See pg. 20, line 23 to pg. 21 line 10 and pg. 21 lines 21-24, pg. 22, lines 10-17. Further, Lai discloses the thermal conductivity coefficient of the first heat dissipation adhesive material 31 is greater than that of the second heat dissipation adhesive material 32, pg. 13, lines 7-8. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the heat dissipating adhesive 31 extend beyond left, right edges of the left 21’ in FIG. 2 so that the heat dissipating adhesive 31 contacts 22, and so that 32 is spaced apart from the left 21’ as taught by Hu to improve heat dissipation, as the adhesive 31 has a greater thermal conductivity coefficient than the adhesive 32. As a result, the adhesive 32 would be spaced apart from left 21’ from a first space, and a left, right portion of 31 would contact 22. In the same field of endeavor, Sato discloses in FIG. 2: a thermal conductive layer (heat conductive material 29 including 32, [0068]) has a portion (left portion 29, 32) overlapping the electronic component (chip 25) in the first direction (FIG. 4 shows 29, 32 overlapping chip 25 in horizontal direction). Sato further discloses conductive bonding material 29 is formed with the first bonding region 31 transferring the heat of the semiconductor chip 25 to the heat spreader 30 and with the second bonding region 32 relaxing the thermal stress generated between the semiconductor chip 25 and the heat spreader 30, [0068]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the heat dissipating adhesive 31 to overlap 21’ horizontally as taught by Sato in order to relax thermal stress as further taught by Sato. In the same field of endeavor, Bernier discloses in FIG. 6: an adhesive layer (324; see Col. 9, lines 45-65) has a portion overlapping the electronic component (chip 302) in the first direction. FIG. 6 shows 324 surrounding the chip 302. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 32 to overlap 21’ in the horizontal direction in order to further improve heat dissipation. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL ANGUIANO/ Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 01, 2023
Application Filed
Nov 04, 2025
Non-Final Rejection mailed — §103
Jan 12, 2026
Interview Requested
Jan 27, 2026
Applicant Interview (Telephonic)
Feb 02, 2026
Examiner Interview Summary
Feb 03, 2026
Response Filed
May 07, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
39%
Grant Probability
69%
With Interview (+29.9%)
3y 6m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
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