Prosecution Insights
Last updated: April 19, 2026
Application No. 18/116,425

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Mar 02, 2023
Examiner
DINKE, BITEW A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
84%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
541 granted / 748 resolved
+4.3% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
52 currently pending
Career history
800
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
65.0%
+25.0% vs TC avg
§102
7.9%
-32.1% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 748 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “wherein a fourth opening passing through the first opening and the second opening are formed in the second insulating layer, the first insulating layer, the second gate insulating layer, and the first gate insulating layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Allowable Subject Matter Claims 8-10 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the above Drawing Objection overcomes. The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the display device further includes: a first gate insulating layer disposed between the semiconductor layer and the first gate electrode; a second gate insulating layer disposed between the first gate electrode and the first storage electrode; a first insulating layer disposed between the first storage electrode and the first electrode; and a second insulating layer disposed between the first electrode and the first data conductive layer, wherein a fourth opening passing through the first opening and the second opening are formed in the second insulating layer, the first insulating layer, the second gate insulating layer, and the first gate insulating layer”, as recited in claim 8. The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the display device further includes: a first gate insulating layer disposed between the first transistor and the first gate electrode; a second gate insulating layer disposed between the first gate electrode and the first storage electrode; a first insulating layer disposed between the first storage electrode and the first electrode; and a second insulating layer disposed between the first electrode and the first data conductive layer, wherein a fourth opening passing through the first opening and the second opening are formed in the second insulating layer, the first insulating layer, the second gate insulating layer, and the first gate insulating layer”, as recited in claim 17. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 6, 11-13, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsueda (U.S 2022/0199726 A1, hereinafter refer to Matsueda). Regarding Claim 1: Matsueda discloses a display device (see Matsueda, Fig.11 as shown below and ¶ [0002]) comprising: PNG media_image1.png 656 827 media_image1.png Greyscale a substrate (851/852) (see Matsueda, Fig.11 as shown above); a first semiconductor layer (811) disposed on the substrate (851/852) (see Matsueda, Fig.11 as shown above); a first gate electrode (621) disposed on the first semiconductor layer (811) (see Matsueda, Fig.11 as shown above); a first storage electrode (631) overlapping at least a portion of the first gate electrode (621) and forming a first capacitor with the first gate electrode (621) (see Matsueda, Fig.11 as shown above); and a first electrode (644) disposed on the first storage electrode (631) and forming a second capacitor together with the first storage electrode (631) (see Matsueda, Fig.11 as shown above), wherein the first storage electrode (631) includes a first opening (632) (see Matsueda, Fig.11 as shown above), the first electrode (644) includes a second opening (see Matsueda, Fig.11 as shown above), the first opening (632) and the second opening overlap each other (see Matsueda, Fig.11 as shown above), and the first electrode (644) further includes a third opening, the third opening overlaps the first storage electrode (631), wherein the first electrode (644) receives a driving voltage (see Matsueda, Fig.11 as shown above). Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Regarding Claim 2: Matsueda discloses a display device as set forth in claim 1 as above. Matsueda further teaches wherein the first capacitor is a storage capacitor (see Matsueda, Fig.11 as shown above), the second capacitor is a hold capacitor (see Matsueda, Fig.11 as shown above), and the first capacitor and the second capacitor overlap in a direction that is perpendicular to a surface of the substrate (851/852) (see Matsueda, Fig.11 as shown above). Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Regarding Claim 3: Matsueda discloses a display device as set forth in claim 1 as above. Matsueda further teaches wherein the first semiconductor layer (811) includes a first transistor, and the first transistor overlaps at least portions of the first gate electrode (621), the first storage electrode (631), and the first electrode (644) (see Matsueda, Fig.11 as shown above and Fig.10). Regarding Claim 4: Matsueda discloses a display device as set forth in claim 3 as above. Matsueda further teaches wherein the first transistor is a driving transistor (see Matsueda, Fig.11 as shown above and Fig.10). Regarding Claim 6: Matsueda discloses a display device as set forth in claim 1 as above. Matsueda further teaches wherein a size of the second opening is greater than a size of the first opening (632) (see Matsueda, Fig.11 as shown above). Regarding Claim 11: Matsueda discloses a display device (see Matsueda, Fig.11 as shown above and ¶ [0002]) comprising: a substrate (851/852) (see Matsueda, Fig.11 as shown above); a first transistor (811/812/813) disposed on the substrate (851/852) (see Matsueda, Fig.11 as shown above and Fig.10); a first gate electrode (621) disposed on the first transistor (811/812/813) (see Matsueda, Fig.11 as shown above); a first storage electrode (631) overlapping at least a portion of the first gate electrode (621) and forming a first capacitor with the first gate electrode (621) (see Matsueda, Fig.11 as shown above); and a first electrode (644) disposed on the first storage electrode (631) and forming a second capacitor together with the first storage electrode (631) (see Matsueda, Fig.11 as shown above), wherein the first capacitor and the second capacitor overlap in a direction that is perpendicular to a surface of the substrate (651/652) (see Matsueda, Fig.11 as shown above), the first storage electrode (631) includes a first opening (632) (see Matsueda, Fig.11 as shown above), the first electrode (644) includes a second opening (see Matsueda, Fig.11 as shown above), at least portions of the first opening (632) and the second opening overlap each other (see Matsueda, Fig.11 as shown above), and the first electrode (644) further includes a third opening, the third opening overlaps the first storage electrode (631), wherein the first electrode (644) receives a driving voltage (see Matsueda, Fig.11 as shown above). Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Regarding Claim 12: Matsueda discloses a display device as set forth in claim 11 as above. Matsueda further teaches wherein the first capacitor is a storage capacitor (see Matsueda, Fig.11 as shown above), and the second capacitor is a hold capacitor (see Matsueda, Fig.11 as shown above). Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Regarding Claim 13: Matsueda discloses a display device as set forth in claim 11 as above. Matsueda further teaches wherein the first transistor is a driving transistor (see Matsueda, Fig.11 as shown above and Fig.10), and the first transistor overlaps the first storage electrode (631) and the first electrode (644) (see Matsueda, Fig.11 as shown above and Fig.10). Regarding Claim 15: Matsueda discloses a display device as set forth in claim 11 as above. Matsueda further teaches wherein a size of the second opening is greater than a size of the first opening (see Matsueda, Fig.11 as shown above). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Matsueda (U.S 2022/0199726 A1, hereinafter refer to Matsueda) as applied to claims 3 and 13 above, and further in view of Cho et al. (U.S. 2017/0053975 A1, hereinafter refer to Cho). Regarding Claim 7: Matsueda discloses a display device as applied to claim 3 above. Matsueda further teaches wherein the display device further includes a first data conductive layer (641) disposed adjacent to the first electrode (644) (see Matsueda, Fig.11 as shown above), and a portion of the first data conductive layer (641) is electrically connected to the first gate electrode (621) (see Matsueda, Fig.11 as shown above). However, Matsueda is silent upon explicitly disclosing wherein a first data conductive layer disposed on the first electrode. Before effective filing date of the claimed invention the disclosed first data conductive layer were known to be disposed on the first electrode in order to obtain an OLED display having high resolution and improved image quality. For support see Cho, which teaches wherein a first data conductive layer (DE3) disposed on the first electrode (G3a) (see Cho, Fig.3 as shown below and ¶ [0009]). PNG media_image2.png 391 548 media_image2.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Matsueda and Cho to enable the Matsueda first data conductive layer to be disposed on the first electrode as taught by Cho in order to obtain an OLED display having high resolution and improved image quality. Regarding Claim 16: Matsueda discloses a display device as applied to claim 13 above. Matsueda further teaches wherein the display device further includes a first data conductive layer (641) disposed adjacent the first electrode (644) (see Matsueda, Fig.11 as shown above), and a portion of the first data conductive layer (641) is electrically connected to the first gate electrode (621) (see Matsueda, Fig.11 as shown above). However, Matsueda is silent upon explicitly disclosing wherein a first data conductive layer disposed on the first electrode. Before effective filing date of the claimed invention the disclosed first data conductive layer were known to be disposed on the first electrode in order to obtain an OLED display having high resolution and improved image quality. For support see Cho, which teaches wherein a first data conductive layer (DE3) disposed on the first electrode (G3a) (see Cho, Fig.3 as shown above and ¶ [0009]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Matsueda and Cho to enable the Matsueda first data conductive layer to be disposed on the first electrode as taught by Cho in order to obtain an OLED display having high resolution and improved image quality. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Mar 02, 2023
Application Filed
Jun 02, 2025
Non-Final Rejection — §102, §103
Aug 26, 2025
Interview Requested
Aug 29, 2025
Examiner Interview Summary
Aug 29, 2025
Applicant Interview (Telephonic)
Sep 04, 2025
Response Filed
Sep 10, 2025
Final Rejection — §102, §103
Nov 03, 2025
Response after Non-Final Action
Dec 15, 2025
Request for Continued Examination
Jan 20, 2026
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
84%
With Interview (+12.0%)
2y 5m
Median Time to Grant
High
PTA Risk
Based on 748 resolved cases by this examiner. Grant probability derived from career allow rate.

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