DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/29/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (20200258987) in view of Sridhar (20150187937) further in view of Lei et al. (CN111769160) (Prior art submitted by the applicant on 1/27/2026)
Regarding Claim 1, in Fig. 1A-1E and paragraphs 0002, 0003, 0012, 0017, 0021, 0022, 0026 and 0029-0034, Chuang et al. discloses a method of making a semiconductor device, the method comprising: a) etching a substrate (126, examiner calls the element 126 as substrate) to form a trench 140 in the substrate (Fig. 1C); b) forming a liner oxide layer 111/131/135 on side surfaces and a process bottom portion of the trench through an oxide layer formation method (Fig. 1D). ; and c) wherein an oxidation time of a junction between an upper surface of the semiconductor substrate and side walls of the trench is increased by the oxide layer formation process, in order to smoothen the junction (see Figs. 1C and 1D, see top left corner of the trench 140). Chuang et al. fails to disclose the added limitation with respect to “forming at least two layers of liner oxide layer on side surfaces and a bottom portion of the trench through an oxide layer formation process”. However, Sridhar discloses an LDMOS device where in Figs. 3B and 3C, element 404/408 along with paragraphs 0014,0015, 0016, 0020, 0021,0027 and 0029, the required limitation with respect to “forming at least two layers of liner oxide layer on side surfaces and a bottom portion of the trench through an oxide layer formation process” is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required first and second oxide liner oxide in Chuang et al. as taught by Sridhar in order to have rounded trench corners in order to have reduced channel hot carriers in order to have higher reliability.
Chuang and Sridhar combination fails to disclose the newly added limitations
d) filling the trench with an insulating material; and forming a field oxide layer on the insulating material and a part of the substrate,
e) wherein a junction formed by the insulating material, the field oxide layer, and the substrate is a smooth transition structure.
However, Lei et al. discloses a semiconductor device where d) filling the trench with an insulating material; and forming a field oxide layer on the insulating material and a part of the substrate is disclosed in Figs 6e and 6k and e) wherein a junction formed by the insulating material, the field oxide layer, and the substrate is a smooth transition structure is disclosed in Fig. 6m (please note the formation of bird’s beak which inherently has round/smooth interface)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the require limitation as listed as d and as listed as e in Chuang and Sridhar combination as taught by Lei et at in order to prevent sharp corners and electric field/carrier/charge overcrowding at the junction.
Regarding Claim 2, in paragraphs 0019, 0029 and 0030 of Chuang et al., a growth time of forming the liner oxide layer 111/131/135 is increased in the trench to make the junction between the upper surface of the semiconductor substrate and the side wall of the trench smooth.
Regarding Claim 3, in paragraphs 0019, 0029 and 0030 of Chuang et al., a number of times of forming the liner oxide layer 111/131/135 in the trench 140 is increased to make the junction between the upper surface of the semiconductor substrate and the side wall of the trench smooth (see top left corner of the trench 140).
Regarding Claim 4, in Chuang et al, the forming the liner oxide layer 111/131/135 comprises: a) forming a first oxide layer 111/131/135 in the trench to cover the bottom portion and side walls of the trench; and b) forming a second oxide layer 111/131/135 on the surface of the first oxide layer.
Regarding Claim 5, in Chuang et al., the forming the liner oxide layer 111/131/135 comprises removing the first oxide layer before forming the second oxide layer.
Regarding Claim 6, in Chuang et al., a) forming a first oxide layer 111/131/135 in the trench 140 to cover the bottom portion of the trench and the side wall of the trench; b) removing the first oxide layer 111/131/135; and c) forming a second oxide layer 111/131/135 on the bottom portion and the side walls of the trench.
Regarding Claim 7, in paragraph 0029 of Chuang et al., a thickness of the first oxide layer is 100A, and a thickness of the second oxide layer is 300A.
Regarding Claim 8, in paragraphs 0026 and 0027 of Chuang et al, removing the liner oxide layer by a wet etching process.
Regarding Claim 9, in paragraphs 0029 and 0030 of Chuang et al, the liner oxide layer is formed by at least two oxidation processes in the trench, a thickness of a last formed oxide layer is greater than or equal to a thickness of any previous formed oxide layer.
Regarding Claim 10, in Chuang et al, in Fig. 1D, side walls of the trench 140 are inclined to the outside at an inclination angle that is less than or equal to 90 degrees.
Regarding Claim 11, in Chuang et al, in Figs. 1D, a section shape of the trench 140 is an inverted trapezoid having an inclination angle from 65 degrees to 70 degrees.
Regarding Claim 12, in Chuang et al., in Fig. 1D, a) filling the trench 140 with an insulating material layer 135; b) forming a body region and a drift region in the trench by ion doping implantation process; and d) forming a gate structure on the field oxide layer and the semiconductor substrate (Fig. 1E)
Regarding Claim 13, in Chuang et al.,forming a source region in the body region by an ion doping implantation process; and b) forming a drain region in the drift region by the ion doping implantation process (Fig. 1E)
Regarding Claim 14, in Chuang et al., in Fig. 1E, it is disclosed that the semiconductor structure comprising: a) the trench 140 formed in the substrate; b) an insulating material layer 135 filled in the trench; and c) a field oxide layer (see paragraphs 0002, 0003 and 0012) located on the insulating material layer and part of semiconductor substrate, wherein a corner at a top of the trench where the field oxide layer is connected with the trench is a round corner (see top left corner of the trench 140 in Fig. 1D).
Regarding Claim 15, in paragraph 0012 of Chuang et al. along with paragraphs 0009, 0013, 0014, 0016 and 0029 of Sridhar, forming a gate structure on the field oxide layer and the substrate, wherein the gate structure comprises a gate oxide layer and a polysilicon layer.
Regarding Claim 16, in paragraph 0012 of Chuang et al. along with paragraphs 0009, 0013, 0014, 0016 and 0029 of Sridhar, the gate oxide layer is on the substrate, and the polysilicon layer is on the gate oxide layer and the field oxide layer.
Regarding Claim 17, in paragraph 0012 of Chuang et al. along with paragraphs 0009, 0013, 0014, 0016 and 0029 of Sridhar, wherein the polysilicon layer fully covers the gate oxide layer, and the polysilicon layer only partially covers the field oxide layer.
Regarding Claim 18, in paragraph 0012 of Chuang et al. along with paragraphs 0009, 0013, 0014, 0016 and 0029 of Sridhar, wherein a height of the gate oxide layer is not higher than a thickness of the field oxide layer.
Relevant Art That is Not Relied Upon
Examiner is including Wang 20210217878 as a relevant prior art that is not relied upon the discloses smooth interface/corner/junction in paragraphs 0066, 0067k, 0072, 0087, 0102-0105 (especially 0103) and 0125 along with Figs. 3a-3j
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 2/3/2026