DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species Group I, and Sub-Species I-16, direct to Claim(s) 1, 13-15l, and 21-36 in the reply filed on 03/06/2026 is acknowledged and is under consideration.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 03/07/2023 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim 13 filed on 03/06/2026 have been fully considered for examination based on their merits. The previously presented claims 1, and 14-15 have been considered. The New Claims 21-30 have been fully considered for examination based on their merits. Claims 2-12, and 16-20 are canceled.
Response to Arguments
The Applicant elected (see Remarks, page 9) without traverse, the Invention I, Species Group I, and the Sub-Species I-16 that are acknowledged and entered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jerry W. Yancey, (hereinafter YANCEY), US 20110039459 A1, in view of Hao Howard Wang et al, (hereinafter WANG), US 20090232991 A1, and Garrit Johannes Hendrikus et al, (hereinafter HENDRIKUS), US 20120127661 A1.
Regarding Claim 1, YANCEY teaches an electronic package structure (Fig. 17, BGA package/LGA package, [0009]), comprising:
a first electronic component (Fig. 21, 2102, bare die #2);
a first thermal conductive structure (Fig. 21, 1002/402, bare die #1/retainer/heat sink) disposed over the first electronic component (Fig. 21, 2102, bare die #2); and
a second thermal conductive structure (Fig. 21, 210, flexible CNT or nanowire forests) disposed between the first electronic component (Fig. 21, 2102, bare die #2) and the first thermal conductive structure (Fig. 21, 1002/402, bare die #1/retainer/heat sink).
YANCEY does not explicitly disclose an electronic package, comprising, wherein a first heat transfer rate of the second thermal conductive structure along a first direction from the first electronic component to the first thermal conductive structure is greater than a second heat transfer rate of the second thermal conductive structure along a second direction nonparallel with the first direction from the first electronic component to an element other than the first thermal conductive structure.
WANG teaches an electronic package (Fig. 4, thermal interface materials in electronic packaging, [0007], [0056]), comprising:
wherein a first heat transfer rate of the second thermal conductive structure (Fig. 4, 403, nano-scale fibers) along a first direction (perpendicular direction to the surface [0013]) from the first electronic component (Fig. 4, 401, device surfaces) to the first thermal conductive structure (Fig. 4, 401, device surfaces) is greater ([0013]) than a second heat transfer rate of the second thermal conductive structure (Fig. 4, 403, nano-scale fibers) along a second direction nonparallel with the first direction (perpendicular direction to the surface [0013]) from the first electronic component (Fig. 4, 403, nano-scale fibers) to an element other than the first thermal conductive structure (Fig. 4, 402/404, sintered metal paste/filler).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YANCEY to incorporate the teachings of WANG, such that an electronic package, comprising: wherein a first heat transfer rate of the second thermal conductive structure along a first direction from the first electronic component to the first thermal conductive structure is greater than a second heat transfer rate of the second thermal conductive structure along a second direction nonparallel with the first direction from the first electronic component to an element other than the first thermal conductive structure, so that the attachment between two surfaces to achieve heat transport between those surfaces, such that interfacial resistances between the CNT and the surfaces are acceptably small, and enable making the thermally interface material (TIM) independently manufacturable from the device and the heat spreader at high volume and low cost (WANG, [0013]).
Though WANG teaches heat spreading is preferable in perpendicular or near perpendicular to the microprocessor surface ([0013]), YANCEY as modified by WANG does not explicitly disclose an electronic package, comprising, wherein a first heat transfer rate along a first direction is greater than a second heat transfer rate along a second direction nonparallel with the first direction.
HENDRIKUS teaches an electronic package (Fig. 2, 30, electronic components), comprising, wherein a first heat transfer rate along a first direction is greater than a second heat transfer rate along a second direction nonparallel with the first direction (Figs. 2/3, the heat transfer rate increases in the perpendicular direction compared to a tangent flow, [0091]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG to incorporate the teachings of HENDRIKUS, such that an electronic package, comprising: wherein a first heat transfer rate along a first direction is greater than a second heat transfer rate along a second direction nonparallel with the first direction, so that the turbulence along the perpendicular directions, promoting further the heat exchanging surface area and thus improving the heat transfer rate of the electronic component (HENDRIKUS, [0092]).
Regarding Claim 27, YANCEY as modified by WANG, and HENDRIKUS teaches the electronic package structure of claim 1.
YANCEY further teaches an electronic package structure (Fig. 17, BGA package/LGA package, [0009]), wherein the second thermal conductive structure (Fig. 19, 210, flexible CNT or nanowire forests) includes a plurality of wires (annotated Figure 19), wherein the plurality of wires (annotated Figure 19) form a high-density wire distribution region (annotated Figure 19) and two low-density wire distribution regions (annotated Figure 19), an amount of the plurality of wires in the high-density wire distribution region is greater than an amount the plurality of wires in the low-density wire distribution region (annotated Figure 19), wherein the low-density wire distribution region is closer to the first electronic component (Figs. 19/20, 902/1002, flip-chip die) than the high-density wire distribution region is (annotated Figure 19), wherein the low-density wire distribution region is closer to the first thermal conductive structure (Figs. 19/20, 902/1002, flip-chip die) than the high-density wire distribution region is (annotated Figure 19).
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Regarding Claim 28, YANCEY as modified by WANG, and HENDRIKUS teaches the electronic package structure of claim 1.
YANCEY further teaches an electronic package structure (Fig. 17, BGA package/LGA package, [0009]), wherein a gap (annotated Figure 20) is between the second circuit pattern structure (Fig. /21, 1002/402, bare die #1/retainer/heat sink) and the electronic component (Fig. 21, 2102, bare die #2), the gap includes a first portion and a second portion (annotated Figure 20).
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Claim(s) 13, is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG as applied to Claim(s) 1, and 27-28 above.
Regarding Claim 13, YANCEY teaches an electronic package structure (Fig. 17, BGA package/LGA package, [0009]), comprising:
a first circuit pattern structure (Fig. 21, 306, PCB/IC package/hybrid substrate);
an electronic component (Fig. 21, 2102, bare die #2) disposed over the first circuit pattern structure (Fig. 21, 306, PCB/IC package/hybrid substrate);
a second circuit pattern structure (Fig. 20, 1002/402, bare die #1/retainer/heat sink) disposed over the electronic component (Fig. 21, 2102, bare die #2), wherein a gap (annotated Figure 20) is between the second circuit pattern structure (Fig. /21, 1002/402, bare die #1/retainer/heat sink) and the electronic component (Fig. 21, 2102, bare die #2), the gap includes a first portion and a second portion (annotated Figure 20), a height of the first portion is different from a height of the second portion (annotated Figure 20); and
a plurality of wires (Fig. 21, 210, flexible CNT or nanowire forests) disposed in the first portion and the second portion (annotated Figure 20).
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Though YANCEY teaches the different heights of the gap portion due to the wires/CNTs alignment, YANCEY does not explicitly disclose an electronic package structure, comprising: wherein a gap is between the second circuit pattern structure and the electronic component, the gap includes a first portion and a second portion, a height of the first portion is different from a height of the second portion; a plurality of wires disposed in the first portion and the second portion.
WANG teaches an electronic package structure (Fig. 4, thermal interface materials in electronic packaging, [0007], [0056]), comprising:
wherein a gap (annotated Figure 4) is between the second circuit pattern structure (Fig. 4, 401, device surfaces) and the electronic component (Fig. 4, 401, device surfaces), the gap includes a first portion and a second portion (annotated Figure 4), a height of the first portion is different from a height of the second portion (annotated Figure 4);
a plurality of wires (Fig. 4, 403, nano-scale fibers) disposed in the first portion and the second portion (annotated Figure 4).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YANCEY to incorporate the teachings of WANG, such that an electronic package, comprising: wherein a gap is between the second circuit pattern structure and the electronic component, the gap includes a first portion and a second portion, a height of the first portion is different from a height of the second portion; a plurality of wires disposed in the first portion and the second portion, so that to achieve a high bulk thermal conductivity due to the deformable buffer layer with good interfacial adhesion with fibers and device surfaces (WANG, [0072-0073]).
Claim(s) 14, is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG as applied to Claim(s) 1, 13, and 27-28 above, and further in view of Koustav Sinha et al, (hereinafter SINHA), US 20220285281 A1.
Regarding Claim 14, YANCEY as modified by WANG teaches the electronic package structure of claim 13.
WANG further teaches the electronic package structure (Fig. 4, thermal interface materials in electronic packaging, [0007], [0056]), wherein the height of the first portion is less than the height of the second portion (annotated Figure 4).
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Though YANCEY and WANG teaches the single wire or nanowire in the electronic package structure, YANCEY as modified by WANG does not explicitly disclose the electronic package structure, wherein the wires include a first wire and a second wire, the first wire is disposed in the first portion and has a bended portion with a first included angle, the second wire is disposed in the second portion and has a bended portion with a second included angle, wherein the first included angle is less than the second included angle.
SINHA teaches the electronic package structure (Fig. 2B, 200, assembly), wherein the wires (annotated Figure 2B) include a first wire (annotated Figure 2B, 220, flexible connector) and a second wire (annotated Figure 2B, 220, flexible connector), the first wire is disposed in the first portion and has a bended portion with a first included angle (annotated Figure 2B), the second wire is disposed in the second portion and has a bended portion with a second included angle (annotated Figure 2B), wherein the first included angle is less than the second included angle (annotated Figure 2B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG to incorporate the teachings of SINHA, such that the electronic package structure, wherein the wires include a first wire and a second wire, the first wire is disposed in the first portion and has a bended portion with a first included angle, the second wire is disposed in the second portion and has a bended portion with a second included angle, wherein the first included angle is less than the second included angle, so that the flexible connector arrays are expected to improve the reliability and robustness of semiconductor devices, particularly in applications involving temperature and/or power cycling or other harsh filed usage conditions such automotive applications (SINHA, [0017]).
Claim(s) 15, is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG as applied to Claim(s) 1, 13-14, and 27-28 above, and further in view of Seiji Sato, (hereinafter SATO), US 20200185326 A1.
Regarding Claim 15, YANCEY as modified by WANG teaches the electronic package structure of claim 13.
YANCEY as modified by WANG does not disclose the electronic package, further comprising a plurality of re-flowable contactors disposed between the first circuit pattern structure and the second circuit pattern structure, wherein the plurality of wires support the second circuit pattern structure and are configured to inhibit the second circuit pattern structure from moving toward the first circuit pattern structure.
SATO teaches the electronic package (Fig. 1A, 1, semiconductor package), the electronic package, further comprising a plurality of re-flowable contactors ([0071]) disposed between the first circuit pattern structure (Fig. 4A, 30, substrate) and the second circuit pattern structure (Fig. 4A 40, semiconductor chip), wherein the plurality of wires (Fig. 4A, 50, joint portions) support the second circuit pattern structure (Fig. 4A 40, semiconductor chip) and are configured to inhibit ([0071]) the second circuit pattern structure (Fig. 4A 40, semiconductor chip) from moving ([0071]) toward the first circuit pattern structure (Fig. 4A, 30, substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG to incorporate the teachings of SATO, such that the electronic package structure, further comprising a plurality of re-flowable contactors disposed between the first circuit pattern structure and the second circuit pattern structure, wherein the plurality of wires support the second circuit pattern structure and are configured to inhibit the second circuit pattern structure from moving toward the first circuit pattern structure, so that to enhance the reliability while space saving, of the semiconductor package structure (SATO, [0001-0005]).
Claim(s) 21, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG and HENDRIKUS as applied to Claim(s) 1, and 27-28 above, and further in view of Benjamin N. Eldridge et al, (hereinafter ELDRIDGE), US 20110057018 A1.
Regarding Claim 21, YANCEY as modified by WANG and HENDRIKUS teaches the electronic package structure of claim 1.
YANCEY further teaches the electronic package structure (Fig. 17, BGA package/LGA package, [0009]), wherein the plurality of first wires (Fig. 20, 210, flexible CNT or nanowire forests) and the plurality of third wires (Fig. 20, 210, flexible CNT or nanowire forests) are entangled with each other (annotated Figure 20).
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YANCEY as modified by WANG and HENDRIKUS does not explicitly disclose the electronic structure, wherein the second thermal conductive structure includes a plurality of first wires protruding from the first electronic component and a plurality of third wires protruding from the first thermal conductive structure.
ELDRIDGE teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein the second thermal conductive structure (Fig. 6A, 602/604/614, contact structures) includes a plurality of first wires (Fig. 6A, 614, contact structures) protruding from the first electronic component (Fig. 6A, 618) and a plurality of third wires (Fig. 6A, 602/604, contact structures) protruding from the first thermal conductive structure (Fig. 6A, 606, electronic component).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG and HENDRIKUS to incorporate the teachings of ELDRIDGE, such that the electronic package structure, wherein the second thermal conductive structure includes a plurality of first wires protruding from the first electronic component and a plurality of third wires protruding from the first thermal conductive structure, so that to create a resilient contact structures originating from same surface of the same substrate all terminate in a different plane which is not coplanar with the substrate or with a plane at which the first group of resilient contact structures terminate (ELDRIDGE, [0577]).
Regarding Claim 22, YANCEY as modified by WANG, HENDRIKUS, and ELDRIDGE teaches the electronic package structure of claim 21.
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein the plurality of first wires (Fig. 6A, 614, contact structures) protrude from a seed layer of the first electronic component (Fig. 6A, 618), and the plurality of third wires (Fig. 6A, 602/604, contact structures) protrude from a first inner bond pad of the first thermal conductive structure (Fig. 6A, 606, electronic component).
Claim(s) 23-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG, HENDRIKUS, ELDRIDGE and SINHA as applied to Claim(s) 1, 14, 21-22, and 27-28 above.
Regarding Claim 23, YANCEY as modified by WANG, HENDRIKUS, and ELDRIDGE teaches the electronic package structure of claim 22.
YANCEY as modified by WANG, HENDRIKUS, and ELDRIDGE does not explicitly disclose the electronic structure, wherein the plurality of first wires are inserted into a gap between the plurality of third wires, and the plurality of third wires are inserted into a gap between the plurality of first wires.
SINHA teaches the electronic package structure (Fig. 2B, 200, assembly), wherein the plurality of first wires (annotated Figure 2B, 220, flexible connector) are inserted into a gap between the plurality of third wires (annotated Figure 2B, 220, flexible connector), and the plurality of third wires (annotated Figure 2B, 220, flexible connector) are inserted into a gap between the plurality of first wires (annotated Figure 2B, 220, flexible connector).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG, HENDRIKUS, and ELDRIDGE to incorporate the teachings of SINHA, such that the electronic package structure, wherein the plurality of first wires are inserted into a gap between the plurality of third wires, and the plurality of third wires are inserted into a gap between the plurality of first wires, so that the flexible connector arrays are expected to improve the reliability and robustness of semiconductor devices, particularly in applications involving temperature and/or power cycling or other harsh filed usage conditions such automotive applications (SINHA, [0017]).
Regarding Claim 24, YANCEY as modified by WANG, HENDRIKUS, ELDRIDGE and SINHA teaches the electronic package structure of claim 23.
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein a combination of the plurality of first wires (Fig. 6A, 614, contact structures) and the plurality of third wires (Fig. 6A, 602/604, contact structures) is configured to inhibit a shift between the first thermal conductive structure (Fig. 6A, 606, electronic component) and the first electronic component (Fig. 6A, 618).
Regarding Claim 25, YANCEY as modified by WANG, HENDRIKUS, ELDRIDGE and SINHA teaches the electronic package structure of claim 23.
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein a combination of the plurality of first wires (Fig. 6A, 614, contact structures) and the plurality of third wires (Fig. 6A, 602/604, contact structures) is configured to inhibit a warpage ([0567]) of the first thermal conductive structure (Fig. 6A, 606, electronic component).
Regarding Claim 26, YANCEY as modified by WANG, HENDRIKUS, ELDRIDGE and SINHA teaches the electronic package structure of claim 23.
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein the plurality of first wires (Fig. 6A, 614, contact structures) do not contact the first thermal conductive structure (Fig. 6A, 606, electronic component), and the plurality of third wires (Fig. 6A, 602/604, contact structures) do not contact the first electronic component (Fig. 6A, 618).
Claim(s) 29, is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG, HENDRIKUS and SINHA as applied to Claim(s) 1, and 21-28 above.
Regarding Claim 29, YANCEY as modified by WANG, and HENDRIKUS teaches the electronic package structure of claim 28.
WANG further teaches the electronic package structure (Fig. 4, thermal interface materials in electronic packaging, [0007], [0056]), wherein the height of the first portion is less than the height of the second portion (annotated Figure 4).
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Though YANCEY and WANG teaches the single wire or nanowire in the electronic package structure, YANCEY as modified by WANG and HENDRIKUS does not explicitly disclose the electronic package structure, wherein the second thermal conductive structure includes a first wire and a second wire, the first wire is disposed in the first portion and has a bended portion with a first included angle, the second wire is disposed in the second portion and has a bended portion with a second included angle, wherein the first included angle is less than the second included angle.
SINHA teaches the electronic package structure (Fig. 2B, 200, assembly), wherein the second thermal conductive structure (annotated Figure 2B, 220, plurality of wires) includes a first wire (annotated Figure 2B, 220, flexible connector) and a second wire (annotated Figure 2B, 220, flexible connector), the first wire is disposed in the first portion and has a bended portion with a first included angle (annotated Figure 2B), the second wire is disposed in the second portion and has a bended portion with a second included angle (annotated Figure 2B), wherein the first included angle is less than the second included angle (annotated Figure 2B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG to incorporate the teachings of SINHA, such that the electronic package structure, wherein the second thermal conductive structure includes a first wire and a second wire, the first wire is disposed in the first portion and has a bended portion with a first included angle, the second wire is disposed in the second portion and has a bended portion with a second included angle, wherein the first included angle is less than the second included angle, so that the flexible connector arrays are expected to improve the reliability and robustness of semiconductor devices, particularly in applications involving temperature and/or power cycling or other harsh filed usage conditions such automotive applications (SINHA, [0017]).
Claim(s) 30-31, is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG and ELDRIDGE as applied to Claim(s) 1, 13-15, and 21-28 above.
Regarding Claim 30, YANCEY as modified by WANG teaches the electronic package structure of claim 13.
YANCEY further teaches the electronic package structure (Fig. 17, BGA package/LGA package, [0009]), wherein the plurality of first wires (Fig. 20, 210, flexible CNT or nanowire forests) and the plurality of third wires (Fig. 20, 210, flexible CNT or nanowire forests) are entangled with each other (annotated Figure 20).
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YANCEY as modified by WANG does not explicitly disclose the electronic structure, wherein the wires include a plurality of first wires protruding from the electronic component and a plurality of third wires protruding from the second circuit pattern structure.
ELDRIDGE teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein the wires (Fig. 6A, 602/604/614, contact structures) include a plurality of first wires (Fig. 6A, 614, contact structures) protruding from the electronic component (Fig. 6A, 618) and a plurality of third wires (Fig. 6A, 602/604, contact structures) protruding from the second circuit pattern structure (Fig. 6A, 606, electronic component).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG to incorporate the teachings of ELDRIDGE, such that the electronic package structure, wherein the wires include a plurality of first wires protruding from the electronic component and a plurality of third wires protruding from the second circuit pattern structure, so that to create a resilient contact structures originating from same surface of the same substrate all terminate in a different plane which is not coplanar with the substrate or with a plane at which the first group of resilient contact structures terminate (ELDRIDGE, [0577]).
Regarding Claim 31, YANCEY as modified by WANG, and ELDRIDGE teaches the electronic package structure of claim 30.
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein the plurality of first wires (Fig. 6A, 614, contact structures) protrude from a seed layer of the first electronic component (Fig. 6A, 618), and the plurality of third wires (Fig. 6A, 602/604, contact structures) protrude from a first inner bond pad of the first thermal conductive structure (Fig. 6A, 606, electronic component).
Claim(s) 32-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANCEY in view of WANG, ELDRIDGE and SINHA as applied to Claim(s) 1, 13-15, and 21-31 above.
Regarding Claim 32, YANCEY as modified by WANG, and ELDRIDGE teaches the electronic package structure of claim 31.
YANCEY as modified by WANG, and ELDRIDGE does not explicitly disclose the electronic structure, wherein the plurality of first wires are inserted into a gap between the plurality of third wires, and the plurality of third wires are inserted into a gap between the plurality of first wires.
SINHA teaches the electronic package structure (Fig. 2B, 200, assembly), wherein the plurality of first wires (annotated Figure 2B, 220, flexible connector) are inserted into a gap between the plurality of third wires (annotated Figure 2B, 220, flexible connector), and the plurality of third wires (annotated Figure 2B, 220, flexible connector) are inserted into a gap between the plurality of first wires (annotated Figure 2B, 220, flexible connector).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YANCEY as modified by WANG, and ELDRIDGE to incorporate the teachings of SINHA, such that the electronic package structure, wherein the plurality of first wires are inserted into a gap between the plurality of third wires, and the plurality of third wires are inserted into a gap between the plurality of first wires, so that the flexible connector arrays are expected to improve the reliability and robustness of semiconductor devices, particularly in applications involving temperature and/or power cycling or other harsh filed usage conditions such automotive applications (SINHA, [0017]).
Regarding Claim 33, YANCEY as modified by WANG, ELDRIDGE and SINHA teaches the electronic package structure of claim 32,
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein a combination of the plurality of first wires (Fig. 6A, 614, contact structures) and the plurality of third wires (Fig. 6A, 602/604, contact structures) is configured to inhibit a shift between the second circuit pattern structure (Fig. 6A, 606, electronic component) and the electronic component (Fig. 6A, 618).
Regarding Claim 34, YANCEY as modified by WANG, ELDRIDGE and SINHA teaches the electronic package structure of claim 32,
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein a combination of the plurality of first wires (Fig. 6A, 614, contact structures) and the plurality of third wires (Fig. 6A, 602/604, contact structures) is configured to inhibit a warpage ([0567]) of the second circuit pattern structure (Fig. 6A, 606, electronic component).
Regarding Claim 35, YANCEY as modified by WANG, ELDRIDGE and SINHA teaches the electronic package structure of claim 32.
ELDRIDGE further teaches the electronic structure (Fig. 6A, 600, semiconductor package, [0054]), wherein the plurality of first wires (Fig. 6A, 614, contact structures) do not contact the second circuit pattern structure (Fig. 6A, 606, electronic component), and the plurality of third wires (Fig. 6A, 602/604, contact structures) do not contact the electronic component (Fig. 6A, 618).
Regarding Claim 36, YANCEY as modified by WANG, ELDRIDGE and SINHA teaches the electronic package structure of claim 35.
YANCEY further teaches an electronic package structure (Fig. 17, BGA package/LGA package, [0009]), wherein the plurality of wires (annotated Figure 19) form a high-density wire distribution region (annotated Figure 19) and two low-density wire distribution regions (annotated Figure 19), an amount of the plurality of wires in the high-density wire distribution region is greater than an amount the plurality of wires in the low-density wire distribution region (annotated Figure 19), and the high-density wire distribution region is located between the two low-density wire distribution regions (annotated Figure 19).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220415776 A1 – Figure 14
STATEMENT OF RELEVANCE – The step involving the conductive terminals, 120A, 120B, 120C are attached onto the bonding pads, 106C through a reflow process [0043].
US 20120218715 A1 – Figure 14
STATEMENT OF RELEVANCE – The diagrammatic sectional view illustrating a structure of the electronic device using single or multi-walled carbon nanotubes , 14 as entangled wire structures connecting the heat spreader, 38 and the semiconductor element, 34.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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