DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 1/8/26.
Applicant’s amendment to claims 1, 2, 4, 7, 11, 12, 15, 16 is acknowledged.
Claims 10 and 20 are cancelled.
Claims 1-9, 11-19, 21 and 22 are pending and subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Regarding claim 1 and the Pan reference:
With a new interpretation, Pan teaches the limitations of amended claim 1 as set for below.
Allowable Subject Matter
Claims 4, 5, 7, 12-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 11, 14, 16, 17 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan et al., US Publication No. 2022/0302003 A1 (of record).
Pan anticipates:
1. A package structure, comprising (see fig. 2 and 10):
(see fig. 2) an interposer (e.g. 510/560; 500 in fig. 10) comprising a first interconnector (568) and a second interconnector (578), wherein the interposer comprises a first edge, a second edge opposite to the first edge, and an upper surface extending from the first edge to the second edge, and wherein the first interconnector (568) and the second interconnector (578) are disposed on the upper surface of the interposer;
(see fig. 10) a first electronic component (800 left) over the upper surface of the interposer (500); and
a second electronic component (700) over the upper surface of the interposer; and
a third electronic component (600 or 200) over the upper surface of the interposer;
wherein the first electronic component (800 left) and the second electronic component (700) are disposed at a first horizontal level and electrically connected to each other through the first interconnector (568),
wherein the second interconnector (578) is electrically connected to the third electronic
component (600 or 200) disposed at a second horizontal level different from the first horizontal level,
wherein a projection of the third electronic component (600 or 200) in a horizontal direction does not overlap a projection of the first electronic component (800 left) or second electronic component (700) in the horizontal direction; and
wherein a width of the interposer (500) is less than a width of the first electronic component (800 left) or a width of the second electronic component (800). See Pan at para. [0001] – [0126], figs. 1-19.
2. The package structure of claim 1, wherein the first interconnector (568) comprises a conductive pad having a first height protruding from the upper surface of the interposer, and the second interconnector (578) comprises a conductive pillar having a second height protruding from the upper surface of the interposer, and wherein the second height is different from the first height, and both of the conductive pad (568) and the conductive pillar (578) are in contact with a solder material (538), fig. 2.
3. The package structure of claim 2, (see fig. 10) wherein the third electronic component (600 or 200) is disposed over (e.g. over the bottom of) the first electronic component (800 left), and the second height is greater than the first height (e.g. height of 578 is greater than height of 568 in fig 2)
6. The package structure of claim 1, wherein the first interconnector (568) comprises a first
transmission path, and the second interconnector (578) comprises a second transmission path, and the second transmission path is not parallel to the first transmission path (In fig. 2A, the first interconnector (568) and the second interconnector (578) are directly connected so the transmission path is not parallel.)
11. A package structure, comprising (see fig. 2 and 10):
(see fig. 2) a bridge interposer (e.g. 510/560; 500 in fig. 10) comprising a first edge, a second edge opposite to the first edge, an active surface (e.g. surface above 510/560) extending from the first edge to the second edge, a plurality of conductive pads (568) and at least one conductive pillar (578), wherein the plurality of conductive pads and at least one conductive pillar are disposed on the active surface, wherein a height of the at least one conductive pillar (578) is greater than a height of the plurality of conductive pads (568);
a first electronic component (800 left) and a second electronic component (700) disposed at a first horizontal level and electrically connected to the plurality of conductive pads (568), wherein the bridge interposer (500) is disposed under a gap between the first electronic component (800 left) and the second electronic component (700); and
a third electronic component (811 or 812 or 600 or 200) disposed at a second horizontal level different from the first horizontal level and electrically connected to the at least one conductive pillar (578),
wherein a projection of the first electronic component (800 left) in a vertical direction covers the first edge (e.g. left edge) of the bridge interposer (500) and a projection of the second electronic component (700) in the vertical direction covers the second edge (e.g. right edge) of the bridge interposer (500). See Pan at para. [0001] – [0126], figs. 1-19.
14. The package structure of claim 11, wherein a width of the at least one conductive
Pillar (578) is greater than a width of one of the plurality of conductive pads (568), fig. 2.
16. The package structure of claim 11, further comprising a passive component (600) bonded to the first (800 left) or second (700) electronic component, wherein the passive component (600) and the bridge interposer (500) are disposed at substantially the same horizontal level and a backside surface of the bridge interposer (500) opposite to the active surface of the bridge interposer is substantially coplanar with a surface of the passive component (600), fig. 10.
17. The package structure of claim 16, wherein the passive component (600) is located under the first (800 left) or second (700) electronic component, fig. 10.
21. The package structure of claim 1, (see fig. 2) wherein the second interconnector (578)
comprises a first conductive pillar (e.g. 578 right) connected to a plurality of first conductive through vias (e.g. 512 right) penetrating through the interposer (510/560), and a second conductive pillar (e.g. 578 left) connected to a second conductive through via (e.g. 512 left) penetrating through the interposer (510/560).
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US Publication No. US 20190148330 A1.
Chen anticipates:
19. A package structure, comprising (see fig. 13):
a bridge component (140A/147/119) comprising an active surface, and a plurality of conductive pads (147) and at least one conductive structure (119) disposed on the active surface; and
a first electronic component (120) disposed on the bridge component and bonded (128) to the bridge component through the plurality of conductive pads (147),
wherein the at least one conductive structure (119) extends upwardly from the active surface of the bridge component and along a lateral surface of the first electronic component (120),
wherein a width of the bridge (140A/147/119) component is less than a width of the first electronic component (120). See Chen at para. [0001] – [0068], figs. 1-14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pan, as applied to claim 1 above, in further view of Lee et al., US Publication No. 2022/0139880 A1 (of record).
Regarding claim 8:
Pan teaches all the limitations of claim 1 above and further teaches:
the second interconnector (578) comprises a signal transmission path, para. [0027], para. [0055] – [0056].
Pan does not expressly teach a power transmission path.
In an analogous art, Lee teaches:
(see fig. 10D) wherein the second interconnector (141/142) comprises a power transmission path (141) and a signal transmission path (142), and the signal transmission path (142) is located closer to the first or second electronic component (200) than the power transmission path (141) is. See Lee[1] at para. [0069] – [0073].
Regarding claim 9:
Lee further teaches:
9. The package structure of claim 8, wherein the second interconnector (141/142) comprises a first conductive pillar (141) for the power transmission path and a second conductive pillar (142) for the signal transmission path, and wherein a width of the first conductive pillar is greater than a width of the second conductive pillar See Lee at para. [0029], [0059], figs. 1A and 10D.
Regarding claim 18:
Pan further teaches the passive component (600) is located adjacent to the first or second electronic component (700), fig. 10.
Pan does not expressly teach the first or second electronic component has a power pad.
In an analogous art, Lee teaches an electronic component (200) has a power pad (222P), figs. 6A and 7, para. [0034].
One of ordinary skill in the art modifying Pan with Lee[1] to form power pad would form “the passive component is located adjacent to a power pad of the first or second electronic component” as recited in the claim because Lee teaches the first or second electronic component is in a flip-chip orientation with the power pad (22P) facing in the downwards direction.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Pan with the teachings of Lee because “Semiconductor packages installed in electronic devices are desirable to have high performance and high capacity along with miniaturization... An aspect of the present inventive concept is to provide a semiconductor package in which a voltage drop is reduced, a switching time is shortened, and an occupied area is minimized.” See Lee[1] at para. [0003] – [0004].
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 19 above, in view of Jo et al., US Publication No. 2024/0170464 A1 (of record).
Regarding claim 22:
Chen teaches all the limitations of claim 19 above and further teaches:
22. The package structure of claim 19, wherein the at least one conductive structure (119) comprises a first conductive pad (147) on the active surface of the bridge component (140A/147/119), a first conductive pillar (119) on the first conductive pad (147), fig. 13.
Chen does not expressly teach:
a conductor on the first conductive pad, wherein the first conductive pad is bonded to the first conductive pillar by the conductor.
In an analogous art, Jo teaches:
(see fig. 2) a conductor (305) on the first conductive pad (150), and a first conductive pillar (300) on the conductor, and wherein the first conductive pad (150) is bonded to the first conductive pillar (300) by the conductor (305), para. [0030], [0066] - [0067].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chen with the teachings of Jo the conductor can serve as a seed layer for the formation of the conductive pillar. See Jo at para. [0067].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
16 March 2026