Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the election filed on 02/21/2026. Group I was elected without traverse. Currently claims 1-14, 24-28 and 30 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn et al. (Pub. No. US 2017/0236909 A1, herein Ahn).
Regarding claim 1, Ahn discloses a method of forming a transistor device, comprising: providing an epiwafer comprising a substrate 100 and one or more epitaxial layers 110-120 (Fig. 3 and Paragraph [0038]); forming source and drain contacts 130-140 on a surface of the epiwafer (Fig. 4 and Paragraph [0039]); forming a surface dielectric layer 150 on the surface of the epiwafer (Fig. 5 and Paragraph [0038]); forming a first opening 10a-150a in the surface dielectric layer, the opening having a first width and exposing a first region of the surface of the epiwafer (Fig. 6 and Paragraph [0038]); forming a mask layer 20 on the epiwafer, the mask layer having a second opening 20a that is offset from the first opening, wherein the second opening exposes a portion of the first region of the surface of the epiwafer and a portion of the surface dielectric layer adjacent the first region of the surface of the epiwafer (Figs. 7-8 and Paragraph [0068]); and forming a gate contact 160 in the second opening (Fig. 9 and Paragraph [0039]).
Regarding claim 7, Ahn discloses the method of Claim 1, wherein the gate contact 160 extends across the portion of the surface dielectric layer adjacent the first region of the surface of the epiwafer (Fig. 9 and Paragraph [0039]).
Regarding claim 8, Ahn discloses the method of Claim 1, wherein the portion of the surface dielectric layer adjacent the first region of the surface of the epiwafer is between the first region of the surface of the epiwafer and the drain contact (Fig. 8 and Paragraph [0070]).
Regarding claims 9-10, Ahn discloses the method of Claim 1, further comprising: after forming the gate contact, forming an insulation layer 180 on the epiwafer, wherein the insulation layer covers the gate contact and the surface dielectric layer, wherein the insulation layer has a different material composition than the surface dielectric layer (Fig. 10 and Paragraph [0079]).
Claim 30 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (Pub. No. US 2021/0327875 A1, herein Lin).
Regarding claim 30, Lin discloses a method of forming an integrated electronic device, comprising: providing a semiconductor die comprising a substrate 100 and an epitaxial structure 111/118 on the substrate (Paragraph [0044]); forming a depletion mode high electron mobility transistor (HEMT) device DE2 in a first region 100B of the semiconductor die; and forming an enhancement mode HEMT device DE1 in a second region 100A of the of the semiconductor die (Paragraphs [0047], [0081]); wherein the depletion mode HEMT comprises first source and drain contacts 125-127, a first gate contact 115 between the first source and drain contacts (Paragraph [0066]), and an insulation layer 116 above the first gate contact, wherein the first gate contact directly contacts the epitaxial structure; and wherein the enhancement mode HEMT comprises second source and drain contacts 121-123 and a second gate contact 113 between the second source and drain contacts, wherein the insulation layer is between the second gate contact and the epitaxial structure (Figs. 3, 5-6 and paragraphs [0062]-[0065], The insulation layer 116 is between the second gate contact 113 an the epitaxial structure 118. The insulation layer 116 is also horizontally between the epitaxial layer 111 and the second gate contact 113. The terms “on” and “between” are broad terms and are different from the terms such as “directly on”, “physically in contact”, “directly above” or “consecutively formed”.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn.
Regarding claims 11-13, Ahn discloses the surface dielectric layer comprises silicon nitride (Paragraph [0038]) but does not specifically state insulation layer comprises aluminum oxide, wherein the insulation layer has a thickness of about 10 nanometers and before forming the gate contact, forming an insulation layer on the epiwafer, wherein the insulation layer covers the surface dielectric layer and the first region of the surface of the epiwafer; wherein forming the gate contact comprises forming the gate contact on the insulation layer. However, the claimed materials, passivating/protecting layers and thickness are recognized as a result-effective variable, i.e., a variable which achieves a recognized result. Passivation layers and inter-device dielectric layers are generally understood in the art to be applicable to various layers or surfaces of a device to protect the underlying material from environmental exposure, chemical reactions, or electrical degradation. Such passivation layers may comprise Al2O3, which is known for its insulating properties, chemical stability and ability to protect underlying layers from oxidation and other forms of degradation. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed thickness because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another value. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 14, Ahn discloses the method of Claim 13, wherein the epiwafer comprises an epitaxial structure including a channel layer and a barrier layer that are configured to form a two dimensional electron gas (2DEG) at an interface between the channel layer and the barrier layer, and wherein a material composition and thickness of the insulation layer are selected to deplete the 2DEG of carriers under zero bias conditions (Ahn: Paragraphs [0033]-[0036]).
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 24-28 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the portion of the first region of the surface of the epiwafer that is exposed by the second opening has a second width that is smaller than a first width of the first opening in the surface dielectric layer. Claims 3-5 are included likewise as they depend from claim 2.
With respect to claim 6, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the mask layer extends into the first opening in the surface dielectric layer, the method further comprising: removing the mask layer; wherein removing the mask layer exposes a portion of the first region of the surface of the epiwafer that was covered by the mask layer.
With respect to claim 24, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, forming a second opening in the surface dielectric layer between the second source and drain contacts, the second opening having a second width and exposing a second region of the surface of the epiwafer; forming a first gate contact in the first opening, the first gate contact having a first gate width that is less than the first width; forming an insulation layer on the surface of the epiwafer, wherein the insulation layer covers the surface dielectric layer, the first and second source and drain contacts, the first gate contact, and the second opening; and forming a second gate contact in the second opening, the second gate contact having a second gate width that is less than the second width. Claims 25-28 are included likewise as they depend from claim 24.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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September 16, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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