Prosecution Insights
Last updated: August 17, 2026
Application No. 18/120,862

LIGHT EMITTING STRUCTURE, DISPLAY APPARATUS, AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS

Final Rejection §103
Filed
Mar 13, 2023
Priority
Jul 28, 2022 — RE 10-2022-0094026
Examiner
VU, DAVID
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
576 granted / 747 resolved
+9.1% vs TC avg
Strong +18% interview lift
Without
With
+18.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
16 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
8.7%
-31.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 747 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C.102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pcrtains. Patentability shall not be negated by the manner in which the invention was made. 1. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wildeson et al. (US 2019/0198709; hereinafter Wildeson) in view of Nomura et al. (US 6,954,478; hereinafter Nomura) Regarding claim 1, Wildeson, in fig. 1H, discloses a light emitting structure comprising: a substrate 106; a first epitaxial structure 101 disposed on the substrate 106; a second epitaxial structure 103 disposed on the first epitaxial structure 101; and a third epitaxial structure 105 disposed on the second epitaxial structure 103; wherein each of the first epitaxial structure 101, the second epitaxial structure 103, and the third epitaxial structure 105 comprises, in a sequentially stacked structure, a first semiconductor layer of a first conductivity 107 (n-type), an active layer 108, and a second semiconductor layer of a second conductivity 109 (p-type) ([0044]). Wildeson discloses a semiconductor device as above but fails to discloses an active layer is formed between a first and a second carrier blocking layer. However, Nomura, fig. 3, discloses an epitaxial structure comprises a first carrier blocking layer 53, an active layer 52, a second carrier blocking layer 55, in a sequentially stacked structure. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form an epitaxial structure as taught by Nomura for preventing the internal electric field arisen from the semiconductor layer pass into the active layer so the energy band of the active layer is not bent and the light emitting efficiency is not reduced. Regarding claim 2, Nomura discloses wherein the first n-type carrier blocking layer 53 comprises a hole blocking layer (col. 8, lines 52-54). Regarding claim 3, Nomura discloses wherein the second p-type carrier blocking layer 55 is an electron blocking layer (col. 8, lines 61-63). Regarding claim 4, Wildeson discloses further comprising a first junction layer 102 and a second junction layer 104 each doped with a high concentration to have the first conductivity, respectively between the first epitaxial structure 101 and the second epitaxial structure 103, and between the second epitaxial structure 103 and the third epitaxial structure 105 (fig. 1H & [0054]). Regarding claim 5, Wildeson discloses wherein the active layer 108 of each of the first epitaxial structure 101, the second epitaxial structure 103, and the third epitaxial structure 105 is configured to emit light at different wavelengths (In the epitaxial structure 101, the active layer 108 is a blue light emitting layer ([0051]). In the epitaxial structure 103, the active layer 108 is a green light emitting layer ([0052]. In the epitaxial structure 105, the active layer 108 is a red light emitting layer ([0053])). Allowable Subject Matter 2. Claims 6-18 are allowed. The following is an examiner's statement of reason for allowance: the prior art of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of "each of the plurality of mesa structures being configured to generate colored light of a corresponding light emitting device in the active layer of the epitaxial structure farthest from the first surface, the active layer of the first epitaxial structure and the active layer of each of the at least one second epitaxial structure being configured to generate light of different wavelengths; wherein the first surface corresponds to one surface of the first semiconductor layer of the first epitaxial structure; and wherein the plurality of light emitting devices are formed in a monolithic shape connected through a partial thickness part of the first semiconductor layer of the first epitaxial structure" (claims 6 and 18) as instantly claimed and in combination with the remaining elements. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance". Response to Arguments 3. Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion 4. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. 5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID VU/ Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Mar 13, 2023
Application Filed
Dec 31, 2025
Non-Final Rejection (signed) — §103
Feb 18, 2026
Non-Final Rejection mailed — §103
May 04, 2026
Applicant Interview (Telephonic)
May 04, 2026
Examiner Interview Summary
May 18, 2026
Response Filed
Jul 24, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707639
SEMICONDUCTOR MEMORY DEVICE
2y 7m to grant Granted Aug 11, 2026
Patent 12701904
DISPLAY DEVICE
2y 7m to grant Granted Aug 04, 2026
Patent 12696562
IMAGE SENSOR
2y 8m to grant Granted Jul 28, 2026
Patent 12696583
MICRO LIGHT EMITTING ELEMENT AND ITS PREPARATION METHOD
2y 7m to grant Granted Jul 28, 2026
Patent 12690485
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND LEAD FRAME
2y 5m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.1%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 747 resolved cases by this examiner. Grant probability derived from career allowance rate.

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