DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the second resistor" in page 4 line 11 of the response dated 02/06/2026. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination the above limitation will be interpreted as “a second resistor”.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite since it depends upon and requires all the limitations of claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7-8, 15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki et al. (US 20020140024 A1; hereinafter Aoki) in view of Brech (US 20130313653 A1; hereinafter Brech).
Regarding claim 1, FIG. 2 of Aoki teaches a transistor (e.g. FIG. 2), comprising: a plurality of gate fingers (1 ¶ [0036]) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction (second direction) that is perpendicular to the first direction (first direction); a gate pad (5 ¶ [0036]); a first gate bus (12) that is electrically connected to the gate pad (5 ¶ [0036]); a first segment (first segment of first instance of 1) of a first gate finger (first instance of 1) in the plurality of gate fingers (1); and a second segment of the first gate finger (second segment of first instance of 1, see Examiner annotated FIG. 2 below).
Aoki does not teach a first resistor electrically connected between the first gate bus and the first segment of the first gate finger in the plurality of gate fingers; and a second resistor electrically connected between the first gate bus and the second segment of the first gate finger.
FIGS. 2A & 4 of Brech teach a transistor (e.g. FIG. 4), comprising: a plurality of gate fingers (23 ¶ [0019]) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction (second direction) that is perpendicular to the first direction (first direction); a gate bus (24’ ¶ [0023]); a first resistor (RG2 ¶ [0023]) among a plurality of resistors (RG1, RG2, R-G3, RG4, etc.) electrically connected between the gate bus (24’) and a first gate finger (instance of 23) in the plurality of gate fingers (23).
Thus Aoki in view of Brech teach the first resistor (RG2 of Brech, i.e. RG2-1 – resistor connected to first segment) electrically connected between the first gate bus (12 of Aoki) and the first segment of the first gate finger in the plurality of gate fingers (first segment of first instance of 1 of Aoki); and a second resistor (resistor having similar properties to RG2 of Brech, i.e. RG2-2 – resistor connected to second segment) electrically connected between the first gate bus (12) and a second segment of the first gate finger (second segment of first instance of 1 of Aoki, see Examiner annotated FIG. 2 below).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor taught by Aoki with the transistor comprising resistors taught by Brech for the purpose of reducing parasitic oscillations (¶ [0015],[0022]-[0023]).
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Regarding claim 2, Aoki as modified teaches the transistor of Claim 1, and FIG. 2 of Aoki further teaches further comprising a gate jumper (4) that electrically connects the first gate bus (12) to the second segment of the first gate finger (second segment of first instance of 1 ¶ [0029]).
Regarding claim 3, Aoki as modified teaches the transistor of Claim 2.
Aoki does not teach wherein the second resistor is electrically connected between the first gate bus and the gate jumper.
However, FIG. 2 of Aoki in view of FIG. 4 of Brech further teaches wherein the second resistor (RG2-2) is electrically connected between the first gate bus (12) and the gate jumper (4, see Examiner annotated FIG. 2 above).
Regarding claim 4, Aoki as modified teaches the transistor of Claim 1, and FIG. 2 of Aoki further teaches wherein the first segment of the first gate finger (first segment of first instance of 1) and the second segment of the first gate finger (second segment of first instance of 1) are separated from each other in the first direction (first direction) by a gap region (region between first segment and second segment, see Examiner annotated FIG. 2 above).
Regarding claim 5, Aoki as modified teaches the transistor of Claim 1.
Aoki does not teach wherein the first resistor is also electrically connected between the first gate bus and a first segment of a second gate finger in the plurality of gate fingers.
However, FIG. 2 of Aoki in view of FIG. 4 of Brech further teaches wherein the first resistor (RG1-1) is also electrically connected between the first gate bus (12) and a first segment of a second gate finger in the plurality of gate fingers (first segment of second instance of 1, see Examiner annotated FIG. 2 above).
Regarding claim 7, Aoki as modified teaches the transistor of Claim 2, and FIG. 2 of Aoki further teaches further comprising a source contact (3 ¶ [0004],[0036]), wherein the gate jumper (4) vertically overlaps the source contact (3, see Examiner annotated FIG. 2 above).
Regarding claim 8, another interpretation of FIG. 2 of Aoki teaches a transistor (e.g. FIG. 2), comprising: a plurality of gate fingers (1 ¶ [0036]) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction (second direction) that is perpendicular to the first direction (first direction); a gate pad (5 ¶ [0036]); a first gate bus (first instance of 4) that is electrically connected to the gate pad (5 ¶ [0036]); a first segment (first segment of first instance of 1) of a first gate finger (first instance of 1) in the plurality of gate fingers (1); and a second segment of the first gate finger (second segment of first instance of 1, see Examiner annotated FIG. 2 below); a gate jumper (12) that electrically connects the first gate bus (first instance of 4) to the second segment of the first gate finger (second segment of first instance of 1 ¶ [0029]).
Aoki does not teach a first resistor electrically connected between the first gate bus and the first segment of the first gate finger in the plurality of gate fingers; and a second resistor electrically connected between the first gate bus and the second segment of the first gate finger.
FIGS. 2A & 4 of Brech teach a transistor (e.g. FIG. 4), comprising: a plurality of gate fingers (23 ¶ [0019]) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction (second direction) that is perpendicular to the first direction (first direction); a gate bus (24’ ¶ [0023]); a first resistor (RG2 ¶ [0023]) among a plurality of resistors (RG1, RG2, R-G3, RG4, etc.) electrically connected between the gate bus (24’) and a first gate finger (instance of 23) in the plurality of gate fingers (23).
Thus Aoki in view of Brech teach the first resistor (RG2 of Brech, i.e. RG2-1 – resistor connected to first segment) electrically connected between the first gate bus (first instance of 4 of Aoki) and the first segment of the first gate finger in the plurality of gate fingers (first segment of first instance of 1 of Aoki); and a second resistor (resistor having similar properties to RG2 of Brech, i.e. RG2-2 – resistor connected to second segment) electrically connected between the first gate bus (first instance of 4 of Aoki) and a second segment of the first gate finger (second segment of first instance of 1 of Aoki, see Examiner annotated FIG. 2 below).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor taught by Aoki with the transistor comprising resistors taught by Brech for the purpose of reducing parasitic oscillations (¶ [0015],[0022]-[0023]).
FIG. 2 of Aoki further teaches further comprising a second gate bus (second instance of 4), where the first resistor (RG2-1) electrically connects the first gate bus (first instance of 4) to the second gate bus (second instance of 4, see Examiner annotated FIG. 2 below).
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Regarding claim 15, FIG. 2 of Aoki further teaches a transistor (e.g. FIG. 2), comprising: a plurality of gate fingers (1 ¶ [0036]) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction (second direction) that is perpendicular to the first direction (first direction); a gate pad (5 ¶ [0036]); a first gate bus (first instance of 4) that has a first longitudinal axis that extends in the second direction (second direction), the first gate bus (first instance of 4) electrically connected to the gate pad (5 ¶ [0036]); a second gate bus (second instance of 4) that is spaced apart from the first gate bus (first instance of 4) in the first direction (first direction) and that has a second longitudinal axis that extends in the second direction (second direction).
Aoki does not teach a first resistor that electrically connects the first gate bus to the second gate bus.
FIGS. 2A & 4 of Brech teach a transistor (e.g. FIG. 4), comprising: a plurality of gate fingers (23 ¶ [0019]) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction (second direction) that is perpendicular to the first direction (first direction); a gate bus (24’ ¶ [0023]); a first resistor (RG2 ¶ [0023]) among a plurality of resistors (RG1, RG2, R-G3, RG4, etc.) electrically connected between the gate bus (24’) and a first gate finger (instance of 23) in the plurality of gate fingers (23).
Thus, Aoki in view of Brech teach the first resistor (RG2 of Brech, i.e. RG2-1 – resistor connected to first gate bus) electrically connected between the first gate bus (first instance of 4 of Aoki) and a gate runner (12, see Examiner annotated FIG. 2 below).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor taught by Aoki with the transistor comprising resistors taught by Brech for the purpose of reducing parasitic oscillations (¶ [0015],[0022]-[0023]).
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Regarding claim 18, Aoki as modified teaches the transistor of Claim 15, and FIG. 2 of Aoki further teaches further comprising a source contact (8) and a gate jumper (12) that extends over the source contact (8).
Aoki does not teach wherein the first resistor is electrically connected between the first gate bus and a first segment of a first gate finger in the plurality of gate fingers, and the second resistor is electrically connected between the first gate bus and the gate jumper.
However, FIG. 2 of Aoki in view of FIG. 4 of Brech further teaches wherein the first resistor (RG2-1 of Brech) is electrically connected between the first gate bus (first instance of 4 of Aoki) and a first segment of a first gate finger in the plurality of gate fingers (first segment of instance of 1 of Aoki), and a second resistor (RG2-2 of Brech) is electrically connected between the first gate bus (first instance of 4 of Aoki) and the gate jumper (12 of Aoki, see Examiner annotated FIG. 2 above).
Regarding claim 19, Aoki as modified teaches the transistor of Claim 18, and FIG. 2 of Aoki further teaches wherein the gate jumper (12) electrically connects the first gate bus (first instance of 4) to a second segment of the first gate finger (second segment of instance of 1, see Examiner annotated FIG. 2 above).
Allowable Subject Matter
Claims 9, 11, 14, 16-17, 22-23, and 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 recites the transistor of Claim 8, wherein the second gate bus comprises a segmented gate bus that includes a plurality of segments that are spaced apart from each other along the second direction, and the first resistor electrically connects the first gate bus to a first segment of the plurality of segments of the second gate bus and the second resistor electrically connects the first gate bus to a second segment of the plurality of segments of the second gate bus.
Aoki in view of Brech teaches the transistor of Claim 8.
However, the prior art fails to teach or reasonably suggest “wherein the second gate bus comprises a segmented gate bus that includes a plurality of segments that are spaced apart from each other along the second direction, and the first resistor electrically connects the first gate bus to a first segment of the plurality of segments of the second gate bus and the second resistor electrically connects the first gate bus to a second segment of the plurality of segments of the second gate bus” together with all the limitations of claims 1-2 and 8-9 as claimed.
Claim 11 recites the transistor of Claim 8, wherein the first resistor and the second resistor each vertically overlap both the first gate bus and the second gate bus.
Aoki in view of Brech teaches the transistor of Claim 8.
However, the prior art fails to teach or reasonably suggest “wherein the first resistor and the second resistor each vertically overlap both the first gate bus and the second gate bus” together with all the limitations of claims 1-2, 8, and 11 as claimed.
Claim 14 recites the transistor of Claim 5, further comprising a third resistor that is electrically connected between the first gate bus and a first segment of a third gate finger in the plurality of gate fingers, wherein gate jumper also electrically connects the first gate bus to a second segment of the third gate finger.
Aoki in view of Brech teaches the transistor of Claim 5.
However, the prior art fails to teach or reasonably suggest “further comprising a third resistor that is electrically connected between the first gate bus and a first segment of a third gate finger in the plurality of gate fingers, wherein gate jumper also electrically connects the first gate bus to a second segment of the third gate finger” together with all the limitations of claims 1, 5, and 14 as claimed.
Claim 16 recites the transistor of Claim 15, wherein the second gate bus comprises a segmented gate bus that includes a plurality of segments that are spaced apart from each other along the second direction, and the first resistor electrically connects the first gate bus to a first segment of the plurality of segments of the second gate bus.
Aoki in view of Brech teaches the transistor of Claim 15.
However, the prior art fails to teach or reasonably suggest “wherein the second gate bus comprises a segmented gate bus that includes a plurality of segments that are spaced apart from each other along the second direction, and the first resistor electrically connects the first gate bus to a first segment of the plurality of segments of the second gate bus” together with all the limitations of claims 15-16 as claimed. Claims 17, 23, and 25-26 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 15-16.
Claim 22 recites the transistor of Claim 15, wherein the first resistor directly contacts both the first gate bus and the second gate bus.
Aoki in view of Brech teaches the transistor of Claim 15.
However, the prior art fails to teach or reasonably suggest “wherein the first resistor directly contacts both the first gate bus and the second gate bus” together with all the limitations of claims 15 and 22 as claimed.
Claims 27-28 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 27 recites a transistor, comprising: a plurality of gate fingers that have respective longitudinal axes that extend in a first direction and that are spaced apart from each other in a second direction that is perpendicular to the first direction; a first gate bus; a first resistor that is coupled between the first gate bus and a first segment of a first gate finger in the plurality of gate fingers; and a second resistor that is coupled between the first gate bus and a second segment of the first gate finger, wherein the first segment of the first gate finger is spaced apart from the second segment of the first gate finger, and wherein the first segment of the first gate finger is closer to the first gate bus than is the second segment of the first gate finger.
Brech teaches a transistor (e.g. FIG. 4), comprising: a plurality of gate fingers (23) that have respective longitudinal axes that extend in a first direction (first direction) and that are spaced apart from each other in a second direction that is perpendicular to the first direction (second direction); a first gate bus (24’); a first resistor (RG2) that is coupled between the first gate bus (24’) and a first segment of a first gate finger in the plurality of gate fingers (instance of 23 common to 22); and a second resistor (RG3) that is coupled between the first gate bus (24’) and a second segment of the first gate finger (other instance of 23 common to 22), wherein the first segment of the first gate finger (instance of 23 common to 22) is spaced apart from the second segment of the first gate finger (other instance of 23 common to 22).
However, the prior art fails to teach or reasonably suggest “wherein the first segment of the first gate finger is closer to the first gate bus than is the second segment of the first gate finger” together with all the limitations of claim 27 as claimed. Claim 28 is allowable insofar as it depends upon and requires all the limitations of claim 27.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891