DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 12/30/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 12/30/2025 in reply to the non-final rejection mailed on 10/01/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 5 is cancelled. Accordingly, pending in this Office action are claims 1-4 & 6-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 & 6-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yin (US 20220367605).
Regarding Claim 1, Yin (see, e.g., fig. 16) shows an integrated circuit, comprising:
a substrate 202 (see, e.g., para.0017);
an interconnection layer MLI Structure (see, e.g., para.0019, para.0026) disposed above the substrate,
wherein the interconnection layer comprises:
an interlayer dielectric layer 210, 220, 230 & 240 (dielectric layers mentioned, see, e.g., para.0019-0023);
and an interconnection structure (conductive features such as contacts, vias, and metal lines, see, e.g., para.0019) disposed in the interlayer dielectric layer;
an insulation layer (combination of 250, 256, 258, & 270, see, e.g., para.0024, para.0027-0028, para.0032) disposed on the interconnection layer;
a metal bump structure (combination of pads 253, 254, 255 and bumps 281, 285, 287, 289, (see, e.g., para.0026, para.0045) disposed on the insulation layer;
and a metal-insulator-metal (MIM) capacitor 260 (see, e.g., para.0030) disposed conformally on the metal bump structure and the insulation layer (see, e.g., annotated figure 1).
wherein the MIM capacitor comprises:
a bottom plate 262;
a capacitor dielectric layer 264 conformally formed on the bottom plate;
and a top plate 266 formed conformally on the capacitor dielectric layer,
wherein a part of the bottom plate 262, a part of the capacitor dielectric layer 264, and a part of the top plate 266 are lower than a top surface of the metal bump structure in a vertical direction (above layer 270, see, e.g., annotated figure 1).
Regarding Claim 2, Yin (see, e.g., fig. 16) shows the integrated circuit according to claim 1,
wherein the metal bump structure comprises:
a first bump 281 & 289 (see, e.g., para.0045) protruding upwards from a top surface of the insulation layer (top surface of 250) in the vertical direction,
wherein the bottom plate 262 is disposed conformally on the first bump and the insulation layer and directly connected with the first bump (see, e.g., para.0046).
Regarding Claim 3, Yin (see, e.g., fig, 16) shows the integrated circuit according to claim 2,
wherein a distance between a top surface of the first bump 281 & 289 and the top surface of the insulation layer (top surface of 250) in the vertical direction ranges from 5000 angstroms to 30000 angstroms.
Yin (see, e.g., para.0027-0028, para.0033, para.0037) states 256 has a thickness of 75 nm, 258 has a thickness of 300nm, 271 has a thickness of 150nm, and 272 has at thickness of 400 nm respectively. Combined the thickness is 9250 angstroms. The thickness of said layers is the distance between the top surface of the first bump 281 & 289 and the top surface of the insulation layer (top surface of 250). Thus, Yin anticipates the claimed range.
Regarding Claim 4, Yin (see, e.g., fig. 16) shows the integrated circuit according to claim 2,
wherein the metal bump structure further comprises:
a first connection pad 255 (see, e.g., para.0026),
wherein the bottom plate of the MIM capacitor is further disposed on and electrically connected with the first connection pad,
a part of the first connection pad 255 is disposed in a first opening (opening of 250, see, e.g., annotated figure 2) penetrating through the insulation layer in the vertical direction for being electrically connected with a first top connection portion of the interconnection structure,
and the bottom plate of the MIM capacitor 262 is electrically connected with the first top connection portion of the interconnection structure via the first connection pad (see, e.g., para.0108).
Regarding the limitation, “a first top connection portion of the interconnection structure,” Yin (see, e.g., para.0019, para.0026) states connection pads 253, 254, & 255 are top contacts connected to other conductive features, such as contacts vias, and metal lines, that are part of the MLI structure. Thus, a first top connection portion of the interconnection structure would correspond to connection pad 255.
Regarding the limitation, “the bottom plate of the MIM capacitor 262 is electrically connected with the first top connection portion of the interconnection structure via the first connection pad,” Yin (see, e.g., para.0046) states 289 is connected to the connection pad 255 and coupled to the bottom plate 262. Thus, bottom plate 262 would be connected to the connection pad 255 and to its corresponding first top connection portion of the interconnection structure.
Regarding Claim 6, Yin (see, e.g., fig. 8) shows the integrated circuit according to claim 4, further comprising:
a passivation layer 271 & 272 (see, e.g., para.0032),
wherein at least a portion of the passivation layer is disposed on the top plate and disposed corresponding to the top plate in the vertical direction completely (see, e.g., fig. 8, para.0032).
Regarding Claim 7, Yin (see, e.g., fig. 16, annotated figure 2) shows the integrated circuit according to claim 4,
wherein the metal bump structure further comprises:
a second connection pad 253 (see, e.g., para.0046) separated from the first bump and the first connection pad,
wherein a part of the second connection pad is disposed in a second opening (opening of 250, see, e.g., annotated figure 2) penetrating through the insulation layer in the vertical direction.
Regarding Claim 8, Yin (see, e.g., fig. 16, annotated figure 2) shows the integrated circuit according to claim 7,
wherein the MIM capacitor is electrically separated from the second connection pad,
the second connection pad 253 is electrically connected with a second top connection portion of the interconnection structure,
and another part of the top plate 266 is disposed in a third opening (opening of 270, see, e.g., annotated figure 2) penetrating through the insulation layer in the vertical direction for being electrically connected with a third top connection portion of the interconnection structure.
Regarding the limitation, “a second top connection portion of the interconnection structure,” Yin (see, e.g., para.0019, para.0026) states connection pads 253, 254, & 255 are top contacts connected to other conductive features, such as contacts vias, and metal lines, that are part of the MLI structure. Thus, a second top connection portion of the interconnection structure would correspond to connection pad 253 and top plate 266 would be electrically connected with the third top connection portion of the interconnection structure corresponding to pad 254.
Regarding Claim 9, Yin (see, e.g., fig.16, annotated figure 2) shows the integrated circuit according to claim 7,
wherein another part of the top plate is disposed in a third opening (opening of 270, see, e.g., annotated figure 2) penetrating through the insulation layer in the vertical direction for being electrically connected with the second connection pad via a fourth top connection portion of the interconnection structure.
Claim 9 does not depend on Claim 8 wherein second and third top connection portions are claimed. Thus, the limitation “a fourth top connection portion of the interconnection structure” is regarded as the third top connection portion established in claim 8, see paragraph 15 above.
Regarding Claim 10, Yin (see, e.g., fig. 16) shows the integrated circuit according to claim 7,
wherein the top plate 266 is further disposed above the second connection pad 253.
Regarding Claim 11, Yin (see, e.g., fig. 16, annotated figure 3) shows the integrated circuit according to claim 1,
wherein the metal bump structure comprises:
a second bump 281 & 287 (see, e.g., para.0045),
wherein the second bump comprises:
a first portion 281 disposed in a recess penetrating through the insulation layer in the vertical direction;
and a second portion 287 disposed on the insulation layer and connected with the first portion,
wherein a top surface of the second portion is higher than a top surface of the insulation layer (270 of the insulation layer) in the vertical direction (see, e.g., annotated figure 3),
and a top surface of the first portion is lower than the top surface of the insulation layer in the vertical direction (see, e.g., annotated figure 3).
Regarding Claim 12, Yin (see, e.g., figs. 1-16) shows a manufacturing method of an integrated circuit, comprising:
forming an interconnection layer MLI Structure (see, e.g., para.0019, para.0026) above a substrate 202 (see, e.g., para.0017),
wherein the interconnection layer comprises:
an interlayer dielectric layer 210, 220, 230 & 240 (dielectric layers mentioned, see, e.g., para.0019-0023);
and an interconnection structure (conductive features such as contacts, vias, and metal lines, see, e.g., para.0019) disposed in the interlayer dielectric layer;
forming an insulation layer (combination of 250, 256, & 258, see, e.g., para.0024, para.0027-0028) on the interconnection layer;
forming a metal bump structure (combination of pads 253, 254, 255 and bumps 281, 285, 287, 289, see, e.g., para.0026, para.0045) on the insulation layer;
and forming a metal-insulator-metal (MIM) capacitor 260 (see, e.g., para.0030) conformally on the metal bump structure and the insulation layer.
wherein the MIM capacitor comprises (see, e.g., para.0030):
a bottom plate 262;
a capacitor dielectric layer 264 conformally formed on the bottom plate;
and a top plate 266 formed conformally on the capacitor dielectric layer,
wherein a part of the bottom plate 262, a part of the capacitor dielectric layer 264, and a part of the top plate 266 are lower than a top surface of the metal bump structure in a vertical direction (above layer 270, see, e.g., annotated figure 1).
Regarding Claim 13, Yin (see, e.g., fig. 11, para.0045) shows the manufacturing method of the integrated circuit according to claim 12,
wherein a method of forming the metal bump structure comprises:
forming a metal layer (253, 254, 255, & metal fill layer, see, e.g., para.0045) on the insulation layer;
and performing a patterning process to the metal layer,
wherein the metal layer is patterned to be the metal bump structure by the patterning process (see, e.g., para.0045).
Regarding Claim 14, Yin (see, e.g., fig. 10) shows the manufacturing method of the integrated circuit according to claim 13, wherein the method of forming the metal bump structure further comprises:
forming a recess 284, 286, & 288 (see, e.g., para.0044) penetrating through the insulation layer in the vertical direction before the step of forming the metal layer,
wherein the metal layer is partly formed in the recess,
a portion of the metal layer is patterned to be a bump by the patterning process (see, e.g., para.0045),
and the bump comprises:
a first portion 281 disposed in the recess;
and a second portion 287 disposed on the insulation layer and connected with the first portion,
wherein a top surface of the second portion 287 is higher than a top surface of the insulation layer in the vertical direction (see, e.g., annotated figure 3),
and a top surface of the first portion 281 is lower than the top surface of the insulation layer in the vertical direction (see, e.g., annotated figure 3).
Regarding Claim 15, Yin (see, e.g., fig. 2, para.0019, para.0026) shows the manufacturing method of the integrated circuit according to claim 13, wherein the method of forming the metal bump structure further comprises:
forming a first opening (opening of 250 above 255) penetrating through the insulation layer (see, e.g., annotated figure 4) in the vertical direction and exposing a part of a first top connection portion of the interconnection structure before the step of forming the metal layer (see paragraphs 10 & 15 above),
wherein the metal layer is partly formed in the first opening,
and a portion of the metal layer (metal fill formed in first opening forms 255, see, e.g., para.0026) is patterned to be a first connection pad 253 partly located in the first opening by the patterning process.
Regarding Claim 16, Yin (see, e.g., fig. 16, annotated figure 2) shows the manufacturing method of the integrated circuit according to claim 15,
wherein the bottom plate 262 is formed on and electrically connected with the first connection pad,
and the bottom plate is electrically connected with the first top connection portion of the interconnection structure via the first connection pad 255 (see paragraph 11 above).
Regarding Claim 17, Yin (see, e.g., fig. 16, annotated figure 2) shows the manufacturing method of the integrated circuit according to claim 13, wherein the method of forming the metal bump structure further comprises:
forming a second opening (opening of 250 above 253) penetrating through the insulation layer in the vertical direction before the step of forming the metal layer,
wherein the metal layer is partly formed in the second opening,
and a portion of the metal layer (metal fill formed in first opening forms 253, see, e.g., para.0026) is patterned to be a second connection pad 253 partly located in the second opening by the patterning process.
Regarding Claim 18, Yin (see, e.g., fig. 16, annotated figure 2) shows the manufacturing method of the integrated circuit according to claim 17, further comprising:
forming a third opening (opening of 270 above 254, see, e.g., annotated figure 2) penetrating through the insulation layer in the vertical direction after the patterning process,
wherein the top plate 266 is partly formed in the third opening.
Regarding Claim 19, Yin (see, e.g., fig. 16) shows the manufacturing method of the integrated circuit according to claim 18, further comprising:
wherein the second opening exposes a part of a second top connection portion of the interconnection structure,
the third opening (opening of 270 above 254, see, e.g., annotated figure 2) exposes another part of the second top connection portion (corresponding to pad 254, see paragraph 15 above),
and the top plate of the MIM capacitor 266 is electrically connected with the second connection pad via the second top connection portion of the interconnection structure (through conductive features within MLI structure, pads 253, 254, & 255, and 287, see, e.g., para.0019, para.0026, para.0046).
Regarding Claim 20, Yin (see, e.g., fig. 8) shows the manufacturing method of the integrated circuit according to claim 12, further comprising:
forming a passivation layer 270 (see, e.g., para.0032) conformally on the top plate,
wherein the bottom plate is formed conformally on the metal bump structure,
and at least a portion of the passivation layer is located corresponding to the top plate in the vertical direction completely (see, e.g., fig. 8 ).
Response to Arguments
Applicant’s arguments, see pages 1-11 filed 12/30/2025, with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814