Prosecution Insights
Last updated: October 27, 2026
Application No. 18/124,674

MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES

Non-Final OA §102§103§112
Filed
Mar 22, 2023
Priority
Feb 07, 2023 — IN 202341007770
Examiner
LINDSEY, COLE LEON
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
3 (Non-Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
124 granted / 139 resolved
+21.2% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
17 currently pending
Career history
170
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.3%
+13.3% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 139 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The Request for Continued Examination filed on 09/04/2026 has been accepted and entered. Response to Arguments Applicant’s arguments, see section titled “Claim Rejections – 35 U.S.C. 112,” filed 09/04/2026, with respect to the rejection of claims 1-3, 5, 7, 9-17, and 21-26 under 35 U.S.C 112(b) have been fully considered and are persuasive. The rejection of claims 1-3, 5, 7, 9-17, and 21-26 under 35 U.S.C 112(b) has been withdrawn. Applicant's arguments filed 09/04/2026 have been fully considered but they are not persuasive. Regarding amended claim 1, Lin (US20200373404A1) discloses a method of manufacturing a semiconductor device, the method comprising: forming a P-dipole stack and an N-dipole stack on a substrate, each of the P- dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the substrate (See below annotated fig. 3A P-dipole/N-dipole stacks comprising interfacial layer 210, high-k dielectric 212, and dipole film 214 formed on substrate 202 on channels 206 between source/drains 204a/204b); and depositing a fill layer comprising a mid-gap fill material on each of the P-dipole stack and the N-dipole stack (Par. 59 teaches that “a capping layer may be deposited on the exposed surface of the dipole region 208”), wherein the mid-gap fill material comprises a metal layer, a metal silicide. a metal nitride, a metal sulfide, or a metal germanide (Par. 59 teaches that “a capping layer may be deposited on the exposed surface of the dipole region 208” and that “the capping layer may comprise… titanium nitride (TiN)” and TiN is a claimed metal nitride from below): the metal layer including one or more of magnesium (Mg), yttrium (Y),manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn)1 niobium (Nb), tin (Sn), or antimony (Sb), or an alloy thereof, the metal silicide comprising one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), and PNG media_image1.png 870 1657 media_image1.png Greyscale the metal nitride, the metal sulfide, and the metal germanide of each comprising one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 9-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US20200373404A1, hereinafter Lin). Regarding claim 1, Lin discloses a method of manufacturing a semiconductor device, the method comprising: forming a P-dipole stack and an N-dipole stack on a substrate, each of the P- dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the substrate (See above annotated fig. 3A P-dipole/N-dipole stacks comprising interfacial layer 210, high-k dielectric 212, and dipole film 214 formed on substrate 202 on channels 206 between source/drains 204a/204b); and depositing a fill layer comprising a mid-gap fill material on each of the P-dipole stack and the N-dipole stack (Par. 59 teaches that “a capping layer may be deposited on the exposed surface of the dipole region 208”), wherein the mid-gap fill material comprises a metal layer, a metal silicide. a metal nitride, a metal sulfide, or a metal germanide (Par. 59 teaches that “a capping layer may be deposited on the exposed surface of the dipole region 208” and that “the capping layer may comprise… titanium nitride (TiN)” and TiN is a claimed metal nitride from below): the metal layer including one or more of magnesium (Mg), yttrium (Y),manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn)1 niobium (Nb), tin (Sn), or antimony (Sb), or an alloy thereof, the metal silicide comprising one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), and the metal nitride, the metal sulfide, and the metal germanide of each comprising one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb). Regarding claim 2, Lin discloses the method of claim 1, wherein depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material (Par. 59 teaches that “[i]n one or more embodiments, a capping layer may be deposited on the exposed surface of the dipole region 208” and par. 20 teaches generally that ALD involves “expos[ing] separately…the two or more reactive compounds which are introduced into a reaction zone of a processing chamber” to deposit the layer. Therefore, Lin discloses depositing their capping layer by exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the TiN film). Regarding claim 9, Lin discloses the method of claim 1, wherein each of the P-dipole stack and the N-dipole stack comprises an interfacial layer on the top surface of the channel (See above annotated fig. 3A interfacial layer 210 on channel 206); a high-K dielectric layer on the interfacial layer (See above annotated fig. 3A high-k dielectric 212 disposed on interfacial layer 210); and a dipole film on the high-K dielectric layer (See above annotated fig. 3A dipole film 214 disposed on high-k dielectric layer 212). Regarding claim 10, Lin discloses the method of claim 9, wherein the interfacial layer comprises a dielectric material (Par. 46 teaches that ”in one or more embodiments, the interlayer dielectric 210 comprises a low-κ dielectric” and that “the low-κ dielectric is selected from…silicon oxide”). Regarding claim 11, Lin discloses the method of claim 10, wherein the dielectric material is selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics (Par. 46 teaches that ”in one or more embodiments, the interlayer dielectric 210 comprises a low-κ dielectric” and that “the low-κ dielectric is selected from…silicon oxide”). Regarding claim 12, Lin discloses the method of claim 1, wherein the channel comprises n-type material (Par. 50 teaches that “[i]n one or more embodiments,…the channel 206 comprises n-type material”). Regarding claim 13, Lin discloses the method of claim 1, wherein the channel comprises p-type material (Par. 52 teaches that “[i]n one or more embodiments,…the channel 206 comprises p-type material”). Regarding claim 14, Lin discloses the method of claim 9, wherein the dipole film comprises one or more of a metal, a metal carbide, a metal nitride, or a metal oxide (Par. 50 teaches that “in one or more embodiments…the dipole layer 214 comprises…titanium magnesium nitride (TiMgN)”. Regarding claim 15, Lin discloses the method of claim 9, wherein the high-K dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium (HfZr) (Par. 47 teaches that “In one or more embodiments, the high-κ dielectric material 212 comprises hafnium oxide”). Regarding claim 16, Lin discloses a method of manufacturing a semiconductor device, the method comprising: forming a P-dipole stack on a substrate by: depositing an interfacial layer on a top surface of a channel located between a source and a drain on the substrate; depositing a high-K dielectric layer on the interfacial layer; and depositing a dipole film on the high-K dielectric layer (See above annotated fig. 3A P-dipole stack comprising interfacial layer 210, high-k dielectric 212, and dipole film 214 formed on substrate 202 on channels 206 between source/drains 204a/204b); forming an N-dipole stack on the substrate by: depositing an interfacial layer on a top surface of a channel located between a source and a drain on the substrate; depositing a high-K dielectric layer on the interfacial layer; and depositing a dipole film on the high-K dielectric layer (See above annotated fig. 3A N-dipole stack comprising interfacial layer 210, high-k dielectric 212, and dipole film 214 formed on substrate 202 on channels 206 between source/drains 204a/204b); annealing the P-dipole stack and the N-dipole stack to drive in metal atoms from the respective dipole film (Par. 54 teaches that “in one or more embodiments, a high temperature thermal annealing is conducted to drive both X1 and X2 in the high-κ material 212 to form n and p dipole”); etching the P-dipole stack and the N-dipole stack to expose the respective high-K dielectric layer (Par. 4B teaches etching P-dipole stack to expose high-k dielectric layer 212); and depositing a mid-gap material on the respective exposed high-K dielectric layer, wherein the mid-gap material comprises a metal layer, a metal silicide, a metal nitride, a metal sulfide, or a metal germanide (Par. 59 teaches that “a capping layer may be deposited on the exposed surface of the dipole region 208” and that “the capping layer may comprise… titanium nitride (TiN)” which is a claimed metal nitride from below): the metal layer including one or more of magnesium (Mg), yttrium (Y), manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn)1 niobium (Nb), tin (Sn), or antimony (Sb)1 or an alloy thereof, the metal silicide comprising one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), and the metal nitride, the metal sulfide, and the metal germanide of each comprising one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (AI), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb). Regarding claim 17, Lin discloses the method of claim 16, wherein depositing the mid-gap material comprises exposing each of the P-dipole stack and the N-dipole stack to one or more of a metal halide precursor or an organometallic precursor and a reactant (Par. 59 teaches that “[i]n one or more embodiments, a capping layer may be deposited on the exposed surface of the dipole region 208” and par. 20 teaches generally that ALD involves “expos[ing] separately…the two or more reactive compounds which are introduced into a reaction zone of a processing chamber” to deposit the layer. Therefore, Lin discloses depositing their capping layer by exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the TiN film). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 5, 7, and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US20200373404A1) in view of Ganguli et al. (US20140120712A1, hereinafter Ganguli). Regarding claim 3, Lin teaches the method of claim 2. Lin does not appear to teach wherein the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor. Ganguli teaches wherein the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor (Par. 12 teaches that “the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because, as Lin is silent as to the specifics of their metal precursors, this would motivate a person of ordinary skill in the art to seek out references such as Ganguli who do explicitly teach the use of a metal halide precursor. Regarding claim 5, the combination of Lin and Ganguli teaches the method of claim 2. Lin does not appear to teach wherein the reactant used to form the metal layer comprises one or more of hydrogen (H2), 1-methyl-3,6- bis(trimethylsilyl)-1,4-cyclohexadiene (CHD) or 1,4-bis(trimethylsilyl)-1,4- dihydropyrazine (DHP). Ganguli teaches wherein the reactant used to form the metal layer comprises one or more of hydrogen (H2), 1-methyl-3,6- bis(trimethylsilyl)-1,4-cyclohexadiene (CHD) or 1,4-bis(trimethylsilyl)-1,4- dihydropyrazine (DHP) (Ganguli par. 35 teaches that “[t]he nitrogen-free reactive gas may be a hydrogen based gas, a carbon-containing reactive gas, a silicon-containing reactive or reducing gas, or combinations thereof. The hydrogen based gas may include hydrogen gas”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because, as Lin is silent as to the specifics of their reactants, this would motivate a person of ordinary skill to seek out references such as Ganguli who do explicitly teach reactants such as hydrogen. Regarding claim 7, Lin and teaches the method of claim 2. Lin does not appear to teach wherein the reactant used to form the silicide comprises one or more of silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H10). Ganguli teaches wherein the reactant used to form the silicide comprises one or more of silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H10) (Ganguli par. 37 teaches “[t]he silicon-containing reactive gas may be used for silicon-containing material depositions, such as silicides. Silicon-containing precursors include silanes and organosilanes. Silanes include silane (SiH4)”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because, as Lin is silent as to the specifics of their reactants, this would motivate a person of ordinary skill to seek out references such as Ganguli who do explicitly teach reactants to form a silicide such as silane. Regarding claim 21, Lin teaches a method of manufacturing a semiconductor device, the method comprising: forming a P-dipole stack and an N-dipole stack on a substrate, each of the P- dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the substrate (See above annotated fig. 3A P-dipole stack comprising interfacial layer 210, high-k dielectric 212, and dipole film 214 formed on substrate 202 on channels 206 between source/drains 204a/204b); and depositing a fill layer comprising a mid-gap fill material on each of the P-dipole stack and the N-dipole stack (Par. 58 teaches that “[i]n one or more embodiments, a gate…may optionally be formed or deposited on the exposed surface of the dipole region 208” and “the gate metal comprises…titanium (Ti)”). Lin does not appear to teach wherein the mid-gap fill material comprises a metal layer, a metal silicide, or a metal carbide: the metal layer including one or more of magnesium (Mg), yttrium (Y),manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn)1 niobium (Nb), tin (Sn), or antimony (Sb), or an alloy thereof, the metal silicide comprising one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), and the metal carbide comprising one or more of magnesium (Mg), yttrium (Y), aluminum (AI), manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb). Ganguli teaches in par. 19 that “metal carbide silicide, and metal boride materials may be used as a NMOS material for a metal gate structure” and “metal carbide nitride materials may be used as a PMOS material for a gate electrode structure. Ganguli further teaches the use of aluminum carbides in par. 25, which examiner notes is one of the claimed materials. Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because as both Lin and Ganguli teach suitable materials for use as gate electrodes in NMOS/PMOS structures, it would have been obvious to substitute Lin’s titanium gate with Ganguli’s aluminum carbide gate to achieve the predictable result of forming a gate electrode comprising aluminum carbide for use in NMOS/PMOS structures. Regarding claim 22, the combination of Lin and Ganguli teaches the method of claim 21, wherein each of the P-dipole stack and the N-dipole stack comprises an interfacial layer on the top surface of the channel; a high-K dielectric layer on the interfacial layer; and a dipole film on the high-K dielectric layer (See above annotated fig. 3A P-dipole/N-dipole stacks comprising interfacial layer 210, high-k dielectric 212, and dipole film 214 formed on substrate 202 on channels 206 between source/drains 204a/204b). Regarding claim 23, the combination of Lin and Ganguli teaches the method of claim 21, wherein depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material (Lin par. 59 teaches that “[i]n one or more embodiments, a capping layer may be deposited on the exposed surface of the dipole region 208” and par. 20 teaches generally that ALD involves “expos[ing] separately…the two or more reactive compounds which are introduced into a reaction zone of a processing chamber” to deposit the layer. Therefore, the combination of Lin and Ganguli teaches depositing their gate layer by exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the gate material). Regarding claim 24, the combination of Lin and Ganguli teaches the method of claim 23. Ganguli further teaches wherein the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor (Par. 12 teaches that “the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Ganguli with additional teachings from Ganguli because, as Lin is silent as to the specifics of their metal precursors, this would motivate a person of ordinary skill in the art to seek out references such as Ganguli who do explicitly teach the use of a metal halide precursor. Regarding claim 25, the combination of Lin and Ganguli teaches The method of claim 23. Ganguli further teaches wherein the reactant used to form the metal layer comprises one or more of hydrogen (H2), 1-methyl-3,6- bis(trimethylsilyl)-1,4-cyclohexadiene (CHD) or 1,4-bis(trimethylsilyl)-1,4- dihydropyrazine (DHP) (Ganguli par. 35 teaches that “[t]he nitrogen-free reactive gas may be a hydrogen based gas, a carbon-containing reactive gas, a silicon-containing reactive or reducing gas, or combinations thereof. The hydrogen based gas may include hydrogen gas”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Ganguli with additional teachings of Ganguli because, as Lin is silent as to the specifics of their reactants, this would motivate a person of ordinary skill to seek out references such as Ganguli who do explicitly teach reactants such as hydrogen. Regarding claim 26, the combination of Lin and Ganguli teaches the method of claim 23. Ganguli further teaches wherein the reactant used to form the metal silicide comprises one or more of silane (SiH4), disilane (Si2He), trisilane (Si3H8), or tetrasilane (Si4H10) (Ganguli par. 37 teaches “[t]he silicon-containing reactive gas may be used for silicon-containing material depositions, such as silicides. Silicon-containing precursors include silanes and organosilanes. Silanes include silane (SiH4)”). Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Ganguli with additional teachings of Ganguli because, as Lin is silent as to the specifics of their reactants, this would motivate a person of ordinary skill to seek out references such as Ganguli who do explicitly teach reactants to form a silicide such as silane. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/Examiner, Art Unit 2812 /EVREN SEVEN/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Mar 22, 2023
Application Filed
Sep 30, 2025
Non-Final Rejection mailed — §102, §103, §112
Mar 02, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §102, §103, §112
Sep 04, 2026
Request for Continued Examination
Sep 09, 2026
Response after Non-Final Action
Sep 28, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+12.5%)
2y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 139 resolved cases by this examiner. Grant probability derived from career allowance rate.

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