Is Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5, 7, 9-17, and 21-26 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. When reciting the material of the mid-gap fill, the claim recites (Examiner notes that the ellipses are to simplify and the bold is to highlight the issue):
“wherein the mid-gap fill material comprises:
a metal layer including…antimony (Sb) or an alloy thereof,
a silicide of one or more of zirconium (Zr)…or rhenium (Re), or
a nitride, a sulfide, or a germanide of one or more of hafnium (Hf)…or antimony (Sb).”
The combination of beginning with “wherein the mid-gap fill material comprises” and “or” after the second of the three above limitation with renders the claim indefinite as examiner is unable to determine if the alternative only refers to the final two limitations, or if the claim only requires one of the above three limitations to be present to satisfy the claim. In the interest of compact prosecution, examiner interprets the claim to mean that at least one of the above three limitations to be present to satisfy the claim.
Claims 2-3, 5, 7, 9-15 are rejected as being dependent upon a claim rejected under 35 U.S.C 112.
Regarding independent claims 16 and 21, as similar arguments apply as those above, they will not be repeated for brevity.
Claims 17 and 22-26 are rejected as being dependent upon a claim rejected under 35 U.S.C 112.
Response to Arguments
Applicant's arguments filed 03/02/2026 have been fully considered but they are not persuasive.
Regarding amended claims 1, and 16, and new claim 21. As discussed above, in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the above listed limitations.
Lin (US20200373404A1) additionally teaches the amended limitation
wherein the mid-gap fill material comprises:
a metal layer including one or more of magnesium (Mg), yttrium (Y),manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn) niobium (Nb), tin (Sn), ruthenium (Ru), or antimony (Sb) or an alloy thereof (Lin par. 58 teaches that “[t]he gate metal may be…ruthenium (Ru)”).
Therefore, Lin still discloses amended claims 1 and 16, see below for full claims mapping.
Similar arguments apply to independent claims 16 and 21 and will not be repeated for brevity.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 9-16, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US20200373404A1, hereinafter Lin).
Regarding claim 1, Lin discloses a method of manufacturing a semiconductor device, the method comprising:
forming a P-dipole stack and an N-dipole stack on a substrate (Lin fig. 3A p-dipole stack on PFET side 250 and n-dipole stack on other side), each of the P-dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the substrate (Fig. 3A channels 206 between source/drain 204a/204b on substrate 202); and
depositing a fill layer comprising a mid-gap fill material on each of the P-dipole stack and the N-dipole stack (Par. 58 “a gate comprising one or more of a gate metal (not illustrated) or a gate contact (not illustrated) may optionally be formed or deposited on the exposed surface of the dipole region 208”), wherein the mid-gap fill material comprises:
a metal layer including one or more of magnesium (Mg), yttrium (Y), manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn) niobium (Nb), tin (Sn), ruthenium (Ru), or antimony (Sb) or an alloy thereof (Lin par. 58 teaches that “[t]he gate metal may be…ruthenium (Ru)”),
a silicide of one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), or a nitride, a sulfide (See above rejection under 112(b) for how in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the listed limitations), or
a germanide of one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb) (See above rejection under 112(b) for how in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the listed limitations).
Regarding claim 9, Lin discloses the method of claim 1, wherein
each of the P-dipole stack and the N-dipole stack comprises one or more of
an interfacial layer on the top surface of the channel (Fig. 3A both stacks have one interlayer dielectric layer 210 on channel 206);
a high-K dielectric layer on the interfacial layer (Fig. 3A both stacks have high-k dielectric material 212 disposed on interlayer dielectric layer 210); and
a dipole film on the high-K dielectric layer (Fig. 3A both stacks have dipole layer 214 disposed on high-k dielectric layer 212).
Regarding claim 10, Lin discloses the method of claim 9,
wherein the interfacial layer comprises a dielectric material (Par. 46 “the interlayer dielectric 210 comprises a low-κ dielectric”).
Regarding claim 11, Lin discloses the method of claim 10,
wherein the dielectric material is selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics (Lin par. 46 “the low-κ dielectric is…silicon oxide”).
Regarding claim 12, Lin discloses the method of claim 1,
wherein the channel comprises n-type material (Par. 50 “[i]n one or more embodiments, when the channel 206 comprises n-type material”).
Regarding claim 13, Lin discloses the method of claim 1,
wherein the channel comprises p-type material (Par. 52 “[i]n one or more embodiments, when the channel 206 comprises p-type material”).
Regarding claim 14, Lin discloses the method of claim 9,
wherein the dipole film comprises one or more of a metal, a metal carbide, metal nitride, or a metal oxide (Par. 50 “the dipole layer 214 comprises…titanium yttrium nitride (TiYN)”).
Regarding claim 15, Lin discloses the method of claim 9,
wherein the high-K dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium (HfZr) (Par. 47 “the high-κ dielectric material 212 comprises hafnium oxide”).
Regarding claim 16, Lin discloses a method of manufacturing a semiconductor device, the method comprising:
forming a P-dipole stack on a substrate by:
depositing an interfacial layer on a top surface of a channel located between a source and a drain on the substrate (Fig. 3A rightmost interlayer dielectric 210 deposited on channel 206 between source/drain 204a/204b);
depositing a high-K dielectric layer on the interfacial layer (Fig. 3A rightmost high-k dielectric 212 deposited on rightmost interlayer dielectric 210); and
depositing a dipole film on the high-K dielectric layer(Fig. 3A rightmost dipole film 214 deposited on rightmost high-k dielectric 212);
forming an N-dipole stack on the substrate by:
depositing an interfacial layer on a top surface of a channel located between a source and a drain on the substrate (Fig. 3A leftmost interlayer dielectric 210 deposited on channel 206 between source/drain 204a/204b);
depositing a high-K dielectric layer on the interfacial layer (Fig. 3A leftmost high-k dielectric 212 deposited on leftmost interlayer dielectric 210); and
depositing a dipole film on the high-K dielectric layer (Fig. 3A leftmost dipole film 214 deposited on leftmost high-k dielectric 212);
annealing the P-dipole stack and the N-dipole stack to drive in metal atoms from the respective dipole film (Par. 54 “[i]n one or more embodiments, a high temperature thermal annealing is conducted to drive both X1 and X2 in the high-κ material 212 to form n and p dipole”);
etching the P-dipole stack and the N-dipole stack to expose the respective high-K dielectric layer (Par. 58 “[i]n one or more embodiments, a gate comprising one or more of a gate metal…may optionally be formed or deposited on the exposed surface of the dipole region 208.” Lin par. 3B additionally teaches removing dipole film 214 to expose high-k dielectric layer 212 on PFET side 250); and
depositing a mid-gap material on the respective exposed high-K dielectric layer (Par. 58 “[i]n one or more embodiments, a gate comprising one or more of a gate metal…may optionally be formed or deposited on the exposed surface of the dipole region 208”), wherein the mid-gap material comprises:
a metal layer including one or more of magnesium (Mg), yttrium (Y), manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn) niobium (Nb), tin (Sn), ruthenium (Ru), or antimony (Sb) or an alloy thereof (Lin par. 58 teaches that “[t]he gate metal may be…ruthenium (Ru)”),
a silicide of one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), or a nitride, a sulfide (See above rejection under 112(b) for how in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the listed limitations), or
a germanide of one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (AI), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb) (See above rejection under 112(b) for how in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the listed limitations).
Regarding claim 21, Lin discloses a method of manufacturing a semiconductor device, the method comprising:
forming a P-dipole stack and an N-dipole stack on a substrate (Lin fig. 3A p-dipole stack on PFET side 250 and n-dipole stack on other side), each of the P- dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the substrate (Fig. 3A channels 206 between source/drain 204a/204b on substrate 202); and
depositing a fill layer comprising a mid-gap fill material on each of the P-dipole stack and the N-dipole stack (Par. 58 “a gate comprising one or more of a gate metal (not illustrated) or a gate contact (not illustrated) may optionally be formed or deposited on the exposed surface of the dipole region 208”), wherein the mid-gap fill material comprises:
a metal layer including one or more of magnesium (Mg), yttrium (Y),manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn) niobium (Nb), tin (Sn),ruthenium (Ru), or antimony (Sb) or an alloy thereof (Lin par. 58 teaches that “[t]he gate metal may be…ruthenium (Ru)”),
a silicide of one or more of zirconium (Zr), molybdenum (Mo), chromium (Cr), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re) (See above rejection under 112(b) for how in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the listed limitations), or
a carbide of one or more of magnesium (Mg), yttrium (Y), aluminum (AI), manganese (Mn), zirconium (Zr), vanadium (V), zinc (Zn), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb) (See above rejection under 112(b) for how in the interest of compact prosecution examiner interprets the claim to mean that the mid-gap fill material must comprise at least one of the listed limitations).
Regarding claim 22, Lin discloses the method of claim 21,
wherein each of the P-dipole stack and the N- dipole stack comprises
an interfacial layer on the top surface of the channel (Fig. 3A both stacks have one interlayer dielectric layer 210 on channel 206);
a high-K dielectric layer on the interfacial layer (Fig. 3A both stacks have high-k dielectric material 212 disposed on interlayer dielectric layer 210); and
a dipole film on the high-K dielectric layer (Fig. 3A both stacks have dipole layer 214 disposed on high-k dielectric layer 212).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 2-3, 5, 7, 17, and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US20200373404A1) in view of Ganguli et al. (US20140120712A1, hereinafter Ganguli).
Regarding claim 2, Lin teaches the method of claim 1.
Lin does not appear to teach wherein
depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material.
Ganguli teaches wherein
depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material (Par. 86 “[t]he metal, metal carbide, metal silicide, metal carbide silicide, or metal carbide nitride material contained within metal-containing gate electrodes 210 or 214 may be formed or deposited by a thermal decomposition process, a CVD process, a pulsed-CVD process, a PE-CVD process, an ALD process, a PE-ALD process, or derivatives thereof, using the metal halide precursors described herein” and par. 43 states that “the metal-containing material may be deposited on the substrate while the reactive gas is previously or is concurrently being exposed to the substrate”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because, as Lin is silent as to the specifics of their gate deposition method, this would motivate a person of ordinary skill in the art to seek out references such as Ganguli who do explicitly teach specifics of a gate deposition method.
Regarding claim 3, the combination of Lin and Ganguli teach the method of claim 2, wherein
the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor (Lin teaches the specific metal precursor, see rejection of claim 2, and par. 86 teaches “[t]he metal, metal carbide, metal silicide, metal carbide silicide, or metal carbide nitride material contained within metal-containing gate electrodes 210 or 214 may be formed or deposited by a thermal decomposition process…using the metal halide precursors described herein”).
Regarding claim 5, the combination of Lin and Ganguli teaches the method of claim 2,
wherein the reactant used to form the metal layer comprises one or more of hydrogen (H2), 1-methyl-3,6- bis(trimethylsilyl)-1,4-cyclohexadiene (CHD) or 1,4-bis(trimethylsilyl)-1,4- dihydropyrazine (DHP) (Ganguli par. 35 teaches that “[t]he nitrogen-free reactive gas may be a hydrogen based gas, a carbon-containing reactive gas, a silicon-containing reactive or reducing gas, or combinations thereof. The hydrogen based gas may include hydrogen gas” and as Ganguli teaches the process of forming the metal layer through the use of a reactant they also teach the specific reactant).
Regarding claim 7, the combination of Lin and Ganguli teaches the method of claim 2,
wherein the reactant used to form the silicide comprises one or more of silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H10) (Ganguli par. 37 teaches “[t]he silicon-containing reactive gas may be used for silicon-containing material depositions, such as silicides. Silicon-containing precursors include silanes and organosilanes. Silanes include silane (SiH4)” and as Ganguli teaches the process of forming the metal layer through the use of a reactant they also teach the specific reactant).
Regarding claim 17, Lin teaches the method of claim 16.
Lin does not appear to teach
wherein depositing the mid-gap material comprises exposing each of the P-dipole stack and the N-dipole stack to one or more of a metal halide precursor or an organometallic precursor and a reactant.
Ganguli teaches
wherein depositing the mid-gap material comprises exposing each of the P-dipole stack and the N-dipole stack to one or more of a metal halide precursor or an organometallic precursor and a reactant (Par. 86 “[t]he metal, metal carbide, metal silicide, metal carbide silicide, or metal carbide nitride material contained within metal-containing gate electrodes 210 or 214 may be formed or deposited by a thermal decomposition process, a CVD process, a pulsed-CVD process, a PE-CVD process, an ALD process, a PE-ALD process, or derivatives thereof, using the metal halide precursors described herein” and par. 43 states that “the metal-containing material may be deposited on the substrate while the reactive gas is previously or is concurrently being exposed to the substrate”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because, as Lin is silent as to the specifics of their gate deposition method, this would motivate a person of ordinary skill in the art to seek out references such as Ganguli who do explicitly teach specifics of a gate deposition method.
Regarding claim 23, Lin teaches the method of claim 21.
Lin does not appear to teach
wherein depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material.
Ganguli teaches wherein
depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material (Par. 86 “[t]he metal, metal carbide, metal silicide, metal carbide silicide, or metal carbide nitride material contained within metal-containing gate electrodes 210 or 214 may be formed or deposited by a thermal decomposition process, a CVD process, a pulsed-CVD process, a PE-CVD process, an ALD process, a PE-ALD process, or derivatives thereof, using the metal halide precursors described herein” and par. 43 states that “the metal-containing material may be deposited on the substrate while the reactive gas is previously or is concurrently being exposed to the substrate”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Ganguli because, as Lin is silent as to the specifics of their gate deposition method, this would motivate a person of ordinary skill in the art to seek out references such as Ganguli who do explicitly teach specifics of a gate deposition method.
Regarding claim 24, the combination of Lin and Ganguli teaches the method of claim 23,
wherein the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor (Lin teaches the specific metal precursor, see rejection of claim 2, and par. 86 teaches “[t]he metal, metal carbide, metal silicide, metal carbide silicide, or metal carbide nitride material contained within metal-containing gate electrodes 210 or 214 may be formed or deposited by a thermal decomposition process…using the metal halide precursors described herein”).
Regarding claim 25, the combination of Lin and Ganguli teaches the method of claim 23,
wherein the reactant used to form the metal layer comprises one or more of hydrogen (H2), 1-methyl-3,6-bis(trimethylsilyl)-1,4- cyclohexadiene (CHD) or 1,4-bis(trimethylsilyl)-1,4-dihydropyrazine (DHP) (Ganguli par. 35 teaches that “[t]he nitrogen-free reactive gas may be a hydrogen based gas, a carbon-containing reactive gas, a silicon-containing reactive or reducing gas, or combinations thereof. The hydrogen based gas may include hydrogen gas” and as Ganguli teaches the process of forming the metal layer through the use of a reactant they also teach the specific reactant).
Regarding claim 26, the combination of Lin and Ganguli teaches the method of claim 23,
wherein the reactant used to form the silicide comprises one or more of silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H10) (Ganguli par. 37 teaches “[t]he silicon-containing reactive gas may be used for silicon-containing material depositions, such as silicides. Silicon-containing precursors include silanes and organosilanes. Silanes include silane (SiH4)” and as Ganguli teaches the process of forming the metal layer through the use of a reactant they also teach the specific reactant).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights