DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 1/5/2026 is acknowledged.
Applicant amended claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2021/0083074) (hereafter Yang), in view of Wong et al. (US 2020/0411667) (hereafter Wong).
Regarding claim 21, Yang discloses a semiconductor device, comprising:
a substrate 106 (Fig. 1B, paragraph 0024);
a fin base 108A (Fig. 1B, paragraph 0024) disposed on the substrate 106 (Fig. 1B);
nanostructured channel regions 122 (Fig. 1B, paragraph 0024, wherein “nanowires” and “channel region”) disposed on the fin base 108A (Fig. 1B);
a source/drain (S/D) region 110 (Fig. 1B, paragraph 0031) disposed on the fin base 108A (Fig. 1B);
a silicon-rich dielectric layer 127 (Fig. 1D, paragraph 0051; and see paragraph 0052, wherein “ the non-NC dielectric material can include a layer of SiOCN, which can have a silicon concentration higher than carbon concentration”); and
an air spacer 129 (Fig. 1D, paragraph 0054) disposed between the silicon-rich dielectric layer 127 (Fig. 1D) and the S/D region 110 (Fig. 1D).
Yang does not disclose a silicon-rich dielectric layer disposed between a top surface of the fin base and a bottom surface of the S/D region.
Wong discloses a silicon-rich dielectric layer 216 (Fig. 22B, paragraph 0031) disposed between (see Fig. 22B, wherein 216 disposed diagonally between top surface of 204c and bottom surface of 230 which is above 232) a top surface of the fin base 204c (Fig. 22B, paragraph 0017) and a bottom surface of the S/D region (bottom surface of 230 above 232 in Fig. 22B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yang to form a silicon-rich dielectric layer disposed between a top surface of the fin base and a bottom surface of the S/D region, as taught by Wong, since implement inner spacers (Wong, paragraph 0055) that include either a low-k dielectric layer as in the case of the dielectric layer 220 (Wong, Fig. 22A, paragraph 0055) or air as in the case of the air gap 232 (Wong, Fig. 22B, paragraph 0055) to reduce the overall parasitic capacitance between the S/D features 230 (Wong, Fig. 22B, paragraph 0055) and the HKMGs 260 (Wong, Fig. 22B, paragraph 0055).
Regarding claim 22, Yang further discloses the semiconductor device of claim 21, further comprising spacers 123 (Fig. 1D) disposed directly on the fin base (element number is not shown in Fig. 1D but see 108A in Fig. 1C) and on ends of the silicon-rich dielectric layer 127 (Fig. 1D).
Regarding claim 23, Yang further discloses the semiconductor device of claim 21, wherein the silicon-rich dielectric layer (see paragraph 0051, wherein “Varying concentrations of silicon, oxygen, carbon, and nitrogen in the non-NC dielectric material can vary the desired dielectric constant of non-NC dielectric layers 127. The non-NC dielectric material can include SiOC, SiCN, SiOCN, SiN, silicon oxide (SiO.sub.x), silicon oxynitride (SiO.sub.yN) and/or a combination thereof”) comprises a silicon-rich nitride layer or a silicon-rich oxynitride layer.
Allowable Subject Matter
1. Claim 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 24 would be allowable because a closest prior art, Yang et al. (US 2021/0083074), discloses a fin base 108A (Fig. 1B, paragraph 0024) disposed on the substrate 106 (Fig. 1B); and a silicon-rich dielectric layer 127 (Fig. 1D, paragraph 0051; and see paragraph 0052, wherein “ the non-NC dielectric material can include a layer of SiOCN, which can have a silicon concentration higher than carbon concentration”) disposed between (see Figs. 1C and 1D, wherein 127 (Fig. 1D) is diagonally between 108A (Fig. 1C) and 110 (Fig. 1C)) the fin base 108A (Fig. 1C) and the S/D region 110 (Fig. 1C) but fails to disclose an undoped silicon layer disposed between the silicon-rich dielectric layer and the fin base. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device, comprising: an undoped silicon layer disposed between the silicon-rich dielectric layer and the fin base in combination with other elements of the base claim 21.
Claims 1-16 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Yang et al. (US 2021/0083074), discloses a fin base 108A (Fig. 1B, paragraph 0024) disposed on the substrate 106 (Fig. 1B); a source/drain (S/D) region 110 (Fig. 1B, paragraph 0031) disposed on a second portion (portion of 108A vertically below 110 in Fig. 1B) of the fin base 108A (Fig. 1B); and a silicon-rich dielectric layer 127 (Fig. 1D, paragraph 0051; and see paragraph 0052, wherein “the non-NC dielectric material can include a layer of SiOCN, which can have a silicon concentration higher than carbon concentration”) but fails to disclose an undoped semiconductor layer disposed on the second portion of the fin base; and a silicon-rich dielectric layer disposed on the undoped semiconductor layer. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: an undoped semiconductor layer disposed on the second portion of the fin base; and a silicon-rich dielectric layer disposed on the undoped semiconductor layer in combination with other elements of claim 1.
In addition, a closest prior art, Yang et al. (US 2021/0083074), discloses a fin base 108A (Fig. 1B, paragraph 0024) disposed on the substrate 106 (Fig. 1B); a source/drain (S/D) region 110 (Fig. 1B, paragraph 0031) disposed on the fin base 108A (Fig. 1B); and a silicon-rich dielectric layer 127 (Fig. 1D, paragraph 0051; and see paragraph 0052, wherein “the non-NC dielectric material can include a layer of SiOCN, which can have a silicon concentration higher than carbon concentration”) but fails to disclose an undoped semiconductor layer disposed between the fin base and the S/D region; and a silicon-rich dielectric layer disposed between the undoped semiconductor layer and the S/D region. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: an undoped semiconductor layer disposed between the fin base and the S/D region; and a silicon-rich dielectric layer disposed between the undoped semiconductor layer and the S/D region in combination with other elements of claim 11.
A closest prior art, Yang et al. (US 2021/0083074), discloses a semiconductor device, comprising: a substrate 106 (Fig. 1B, paragraph 0024); a fin base 108A (Fig. 1B, paragraph 0024) disposed on the substrate 106 (Fig. 1B); nanostructured channel regions 122 (Fig. 1B, paragraph 0024, wherein “nanowires” and “channel region”) disposed on a first portion (portion of 108A vertically below 122 in Fig. 1B) of the fin base 108A (Fig. 1B); a gate structure 112 (Fig. 1E, paragraph 0024) surrounding the nanostructured channel regions 122 (Fig. 1E); a source/drain (S/D) region 110 (Fig. 1B, paragraph 0031) disposed on a second portion (portion of 108A vertically below 110 in Fig. 1B) of the fin base 108A (Fig. 1B); and an isolation structure (element number is not shown in Fig. 1B but see 123 in Fig. 1D, paragraph 0050), disposed between the S/D region 110 (Fig. 1B) and the second portion (portion of 108A vertically below 110 in Fig. 1B) of the fin base 108A (Fig. 1B), comprising: a silicon-rich dielectric layer 127 (Fig. 1D, paragraph 0051; and see paragraph 0052, wherein “ the non-NC dielectric material can include a layer of SiOCN, which can have a silicon concentration higher than carbon concentration”); and an air spacer 129 (Fig. 1D, paragraph 0054) disposed on the silicon-rich dielectric layer 127 (Fig. 1D) but fails to teach an undoped semiconductor layer disposed on the second portion of the fin base; and a silicon-rich dielectric layer disposed on the undoped semiconductor layer as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-10 depend on claim 1.
In addition, a closest prior art, Yang et al. (US 2021/0083074), discloses a semiconductor device, comprising: a substrate 106 (Fig. 1B, paragraph 0024); a fin base 108A (Fig. 1B, paragraph 0024) disposed on the substrate 106 (Fig. 1B); nanostructured channel regions 122 (Fig. 1B, paragraph 0024, wherein “nanowires” and “channel region”) disposed on the fin base 108A (Fig. 1B); a source/drain (S/D) region 110 (Fig. 1B, paragraph 0031) disposed on the fin base 108A (Fig. 1B); and a silicon-rich dielectric layer 127 (Fig. 1D, paragraph 0051; and see paragraph 0052, wherein “ the non-NC dielectric material can include a layer of SiOCN, which can have a silicon concentration higher than carbon concentration”) but fails to teach an undoped semiconductor layer disposed between the fin base and the S/D region; and a silicon-rich dielectric layer disposed between the undoped semiconductor layer and the S/D region as the context of claim 11. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 12-16 depend on claim 11.
Response to Arguments
1. Applicant's arguments filed 1/5/2026 have been fully considered.
2. Applicant's arguments with respect to claims 21-23 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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