DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 in the reply filed on 9/9/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over More US 2022/0059703 and Kim et al. US 2006/0115934.
Re claim 1, More teaches a method of manufacturing a semiconductor device (fig22), comprising:
forming a fin structure (29, fig3, [44]) in which first semiconductor layers (20, fig3, [44]) and second semiconductor layers (25, fig3, [44]) are alternately stacked over a substrate (10, fig3, [46]);
forming a sacrificial gate structure (40, fig4B, [49]) over the fin structure;
etching a source/drain region of the fin structure (21, fig5, [53]), which is not covered by the sacrificial gate structure (40, fig5, [49]), thereby forming a source/drain space (21, fig5, [53]);
forming a bottom epitaxial layer (49, fig9A and 20, [60]) in the source/drain space;
forming a first epitaxial layer (50-1 and 50-2, fig20, [91]) over the bottom epitaxial layer (49, fig9A and 20, [60]); and
forming a second epitaxial layer (50-3, fig20, [93]) over the first epitaxial layer (50-1 and 50-2, fig20, [91]),
wherein: the forming the first epitaxial layer comprises a first process (forming 50-2, fig20, [91]) and a second process (forming 50-1 followed by forming 50-2, fig20, [91]) followed by the first process, both of which includes a deposition phase ([86, 91]) and an etching phase ([86, 91]) followed by the deposition phase.
More does not explicitly show a process time ratio of the deposition phase to the etching phase in the first process is greater than a process time ratio of the deposition phase to the etching phase in the second process.
More teaches Ge and B concentration in 50-2 greater than 50-1 in fig20 [91].
Kim teaches an alternating gas supply process (fig4) with a deposition phase (420 and 440, fig4, [59, 64]) with process time of 5-10 seconds ([59,83]) and an etching phase (460, fig4, [67]) with process time of 10-90 seconds ([67]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Kim to adjust the deposition duration of the secondary element with step 440 longer in formation of 50-2 than step 440 in formation of 50-1. The motivation to do so is to achieve the composition profile as shown in More fig20 with fast deposition rate and low process temperature (Kim, [8]).
Re claim 2, More modified above teaches the method of claim 1, wherein the process time ratio of the deposition phase to the etching phase in the first process is in a range from 1.3 to 1.5 (Kim, Silane 7 seconds, germane 7 seconds and etching for 10 seconds used to form More 50-2, [81]).
Re claim 3, More does not explicitly show the method of claim 1, wherein the process time ratio of the deposition phase to the etching phase in the second process is in a range from 1.11 to 1.15.
More teaches Ge and B concentration in 50-2 greater than 50-1 in fig20.
Kim teaches an alternating gas supply process (fig4) with a deposition phase (420 and 440, fig4, [59, 64]) with process time of 5-10 seconds ([59,83]) and an etching phase (460, fig4, [67]) with process time of 10-90 seconds ([67]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Kim to decrease the deposition duration of the secondary element with step 440 during formation of 50-1. The motivation to do so is to achieve the composition profile as shown in More fig20 with fast deposition rate and low process temperature (Kim, [8]).
Re claim 6, More modified above teaches the method of claim 1, wherein a process gas for the deposition phase includes SiH2Cl2 (More, [86, 91]) and a process gas for the etching phase includes HCl (More, [86, 91]).
Claim(s) 21-22 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over More US 2022/0059703 and Lee et al. US 2022/0278198.
Re claim 21, More teaches a method of manufacturing a semiconductor device (fig22), comprising:
forming a fin structure (29, fig3, [44]) in which first semiconductor layers (20, fig3, [44]) and second semiconductor layers (25, fig3, [44]) are alternately stacked over a substrate (10, fig3, [46]);
forming a sacrificial gate structure (40, fig4B, [49]) including a sacrificial gate dielectric layer (41, fig4B, [49]) and sacrificial gate electrode layer (42, fig4B, [49]) over the fin structure;
etching a source/drain region of the fin structure (21, fig5, [53]), which is not covered by the sacrificial gate structure (40, fig5, [49]), thereby forming a source/drain space (21, fig5, [53]);
forming a bottom epitaxial layer (49, fig9A and 20, [60]) in the source/drain space;
forming a first epitaxial layer (50-1 and 50-2, fig20, [91]) over the bottom epitaxial layer (49, fig9A and 20, [60]);
forming a second epitaxial layer (50-3, fig20, [93]) over the first epitaxial layer (50-1 and 50-2, fig20, [91]);
More does not explicitly show reducing a width of the second epitaxial layer by performing a trimming operation, wherein: the width of the second epitaxial layer after the trimming operation is 70-90 % of the width of the second epitaxial layer before the trimming operation.
Lee teaches forming a second epitaxial layer (510C, fig8A-C, [31]) over the first epitaxial layer (510B, fig7A-C, [31]); and reducing a width of the second epitaxial layer (reducing width of 316 by forming 318, fig8D, [39]) by performing a trimming operation, wherein: the width of the second epitaxial layer after the trimming operation is 70-90 % of the width of the second epitaxial layer before the trimming operation ([39]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Lee to recess the second epitaxial layer and replace More 49-50 in fig 22A with Lee 510A-D in fig9D and fig11A-C. The motivation to do so is to achieve sufficient size to form local contact feature (Lee, [39])
The outcome of the combination will be forming a first epitaxial layer (More, 50-1 and 50-2, fig19A-D, [91]; More 50-1/50-2 in fig19D will be Lee 510B in fig7A-C) over the bottom epitaxial layer (More, 49, fig9A and 20, [60]; More 49 in fig19D will be Lee 510A in fig7C); forming a second epitaxial layer (More, 50-3, fig20, [93]; More 50-3 in fig19D will be Lee 510C in fig8C-D) over the first epitaxial layer (More, 50-1 and 50-2, fig20, [91]); and reducing a width of the second epitaxial layer by performing a trimming operation (recess More top surface of 50-1/50-2 as recess top surface of 510C in fig8D of Lee), wherein: the width of the second epitaxial layer after the trimming operation is 70-90 % of the width of the second epitaxial layer before the trimming operation (Lee, width of 316 reduced to form 318, fig8D, [39]).
Re claim 22, More modified above teaches the method of claim 21, wherein a variation of the width of the second epitaxial layer after the trimming operation is more than 0.3 nm to and less than 1.0 nm (Lee, recess 510C to achieve sufficient contact area, fig8D, [39]).
Re claim 25, More modified above teaches the method of claim 21, further comprising forming a third epitaxial layer (Lee, 510D, fig9D, [41]) over the second epitaxial layer (Lee, 510C, fig8A-C, [31]).
Re claim 26, More modified above teaches the method of claim 25, wherein after the trimming operation, the third epitaxial layer remains (Lee, 510D formed over recessed 510C, fig9D).
Claim(s) 29 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over More US 2022/0059703, Kim et al. US 2006/0115934 and Lee et al. US 2022/0278198.
Re claim 29, More modified above teaches a method of manufacturing a semiconductor device (fig22), comprising:
forming a fin structure (29, fig3, [44]) in which first semiconductor layers (20, fig3, [44]) and second semiconductor layers (25, fig3, [44]) are alternately stacked over a substrate (10, fig3, [46]);
forming a sacrificial gate structure (40, fig4B, [49]) over the fin structure;
etching a source/drain region (21, fig5, [53]) of the fin structure, which is not covered by the sacrificial gate structure (40, fig5, [49]), thereby forming a source/drain space (21, fig5, [53]);
forming a bottom epitaxial layer (49, fig9A and 20, [60]) in the source/drain space;
forming a dielectric layer (68, fig1A, [69]) over the bottom epitaxial layer (49, fig1A, [60]);
forming a first epitaxial layer (50-1 and 50-2, fig19A-D, [91]) over lateral end faces of the second semiconductor layers (25, fig19A, [44]);
forming a second epitaxial layer (50-3, fig20, [93]) over the first epitaxial layer; and
wherein: the forming the first epitaxial layer (50-1 and 50-2, fig19A-D, [91]) comprises a first process (forming 50-2, fig20, [91]) and a second process (forming 50-1 followed by forming 50-2, fig20, [91]) followed by the first process, the second process and the forming the second epitaxial layer each include a deposition phase ([86, 91, 94]) and an etching phase ([86, 91, 94]) followed by the deposition phase.
More does not explicitly show reducing a width of the second epitaxial layer by performing a trimming operation, and a process time ratio of the deposition phase to the etching phase in the second process is smaller than a process time ratio of the deposition phase to the etching phase for the second epitaxial layer.
Lee teaches forming a second epitaxial layer (510C, fig8A-C, [31]) over the first epitaxial layer (510B, fig7A-C, [31]); and reducing a width of the second epitaxial layer (reducing width of 316 by forming 318, fig8D, [39]) by performing a trimming operation.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Lee to recess the second epitaxial layer and replace More 49-50 in fig 22A with Lee 510A-D in fig9D and fig11A-C. The motivation to do so is to achieve sufficient size to form local contact feature (Lee, [39])
More teaches Ge and B concentration in 50-3 greater than 50-1 in fig20 [91].
Kim teaches an alternating gas supply process (fig4) with a deposition phase (420 and 440, fig4, [59, 64]) with process time of 5-10 seconds ([59,83]) and an etching phase (460, fig4, [67]) with process time of 10-90 seconds ([67]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Kim to adjust the deposition duration of the secondary element with step 440 longer in formation of 50-3 than step 440 in formation of 50-1. The motivation to do so is to achieve the composition profile as shown in More fig20 with fast deposition rate and low process temperature (Kim, [8]).
Re claim 30, More modified above teaches the method of claim 29, wherein the second epitaxial layer (More, 50-3, fig19D, [93]; Lee, 510D, fig9D and 1, [41]) is in contact with the dielectric layer (More, 68, fig1A, [69]; Lee 230 or 202, fig1 and 10A, [43, 23]).
Allowable Subject Matter
Claims 4-5, 7, 23-24, 27-28 and 31-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to improve contact in the S/D region for a gate-all-around FET structure.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812 .